JPH01283862A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01283862A JPH01283862A JP63114288A JP11428888A JPH01283862A JP H01283862 A JPH01283862 A JP H01283862A JP 63114288 A JP63114288 A JP 63114288A JP 11428888 A JP11428888 A JP 11428888A JP H01283862 A JPH01283862 A JP H01283862A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- film
- titanium nitride
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 16
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 12
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 65
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- 230000000694 effects Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に容量部を有する半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a capacitive portion.
ダイナミック・ランダム・アクセス・メモリのような、
構成要素として容量を備えた半導体装置の集積度は、年
々高くなっている。従来、高集積化は配線や回路素子の
パターンを微細化することで行われてきた。しかし、こ
のような微細化は信号に対応しした蓄積電荷量を少くす
ることになり、α線などの放射線によるメモリの誤動作
（ソフトエラー）を防止する上で好しくない。such as dynamic random access memory,
The degree of integration of semiconductor devices that include capacitors as constituent elements is increasing year by year. Conventionally, high integration has been achieved by miniaturizing wiring and circuit element patterns. However, such miniaturization reduces the amount of accumulated charge corresponding to a signal, which is not preferable in terms of preventing memory malfunctions (soft errors) caused by radiation such as alpha rays.
従来、容量の誘電体層を薄くし、メモリセルの容量値を
大きくすることによりこの問題を解決してきた。しかし
、誘電体層の薄膜化が進むと、例えば６ｎｍの５ｉ０２
層に５■の電圧を印加すると、トンネル電流が流れるた
め、原理的に絶縁膜として使用できないという問題があ
る。それ故、容量の占める面積が小さく、かつ大きい容
量値を得るために、誘電体材料として比誘電率の高いＴ
ａ２０５ 、’ｒ’ｉ０２ 、Ｎｂ２０５ 、ＨｆＯ２
。Conventionally, this problem has been solved by making the dielectric layer of the capacitor thinner and increasing the capacitance value of the memory cell. However, as dielectric layers become thinner, for example, 6 nm 5i02
When a voltage of 5 .mu. is applied to the layer, a tunnel current flows, so there is a problem that it cannot be used as an insulating film in principle. Therefore, in order to obtain a large capacitance value with a small area occupied by the capacitor, T
a205, 'r'i02, Nb205, HfO2
.
ＺｒＯ２等の誘電体層を用いることが試みられている。Attempts have been made to use dielectric layers such as ZrO2.
これらの誘電体層を用いた容量部の構造は、シリコン基
板やタングステン等の高融点金属電極上に前記の誘電体
層を設け、上部電極として高融点金属、珪化物あるいは
多結晶シリコンを用いる構造が試みられている。The structure of the capacitive part using these dielectric layers is such that the dielectric layer is provided on a silicon substrate or a high melting point metal electrode such as tungsten, and the upper electrode is made of a high melting point metal, silicide, or polycrystalline silicon. is being attempted.
上述した従来の容量構造では、容量部の製造後の種々の
熱処理でリーク電流が増加するという欠点がある。この
リーク電流増加は、熱処理により容量膜（誘電体膜）と
容量電極部との間に反応が生じて膜質が劣化すること、
あるいはピンホールや電気的絶縁性の悪い部分が局所的
に生じていることに起因している。従って、従来の容量
構造は実デバイスに用いることができないという問題が
ある。The conventional capacitor structure described above has a drawback in that leakage current increases during various heat treatments after manufacturing the capacitor section. This increase in leakage current is caused by a reaction occurring between the capacitive film (dielectric film) and the capacitive electrode part due to heat treatment, which deteriorates the film quality.
Alternatively, it may be caused by pinholes or areas with poor electrical insulation occurring locally. Therefore, there is a problem that the conventional capacitor structure cannot be used in an actual device.
本発明の半導体装置は、基板上に形成されている半導体
層または導電体層から成る第１の電極と、前記第１の電
極上に設けられた弁作用を有する金属酸化物から成る誘
電体層と、金属窒化物または金属酸化物層から成り前記
誘電体層を被覆する絶縁層と、前記第１の電極に対向し
て前記絶縁膜上に設けられた第２の電極とで構成される
容量部を備えている。The semiconductor device of the present invention includes a first electrode made of a semiconductor layer or a conductive layer formed on a substrate, and a dielectric layer made of a metal oxide having a valve action provided on the first electrode. , an insulating layer made of a metal nitride or metal oxide layer and covering the dielectric layer, and a second electrode provided on the insulating film opposite to the first electrode. It has a department.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
シリコン基板の上に容量膜の’１’ａ２０５膜２、窒化
チタン層３、導電体層の多結晶シリコン層４を順次堆積
する。電極は窒化チタン層３と多結晶シリコン層４の２
層からなっている。A '1'a205 film 2 as a capacitive film, a titanium nitride layer 3, and a polycrystalline silicon layer 4 as a conductive layer are sequentially deposited on a silicon substrate. The electrodes are a titanium nitride layer 3 and a polycrystalline silicon layer 4.
It consists of layers.
この第１の実施例の容量は、以下のように製造される。This first example capacitor is manufactured as follows.
まず、シリコン基板１の上に、反応性スパッタやＣＶＤ
等の方法でＴａ２０５層を堆積する方法、あるいはスパ
ッタでＴａ層を堆積した後熱酸化、してＴａ２０５１を
堆積する方法によりＴａ２０５層２を５〜３０ｎｍの厚
さに堆積する。次に、Ｔａ２０５層２の上に、スパッタ
法で窒化チタン層・を直接堆積する方法、あるいはスパ
ッタでチタン層を堆積した後ランプ・アニ°−ル等の熱
処理を行う方法によって窒化チタン層３を３０〜２００
ｎａｉ程度の厚さに堆積する。次に、ＣＶＤ等の方法を
用い、窒化チタン層３の上に多結晶シリコン層４を１０
０〜６００ ｎｍ程度の厚さに堆積する。First, reactive sputtering or CVD is applied onto the silicon substrate 1.
The Ta205 layer 2 is deposited to a thickness of 5 to 30 nm by a method such as Depositing a Ta205 layer, or by a method of depositing a Ta layer by sputtering and then thermally oxidizing it to deposit Ta2051. Next, a titanium nitride layer 3 is formed on the Ta205 layer 2 by directly depositing a titanium nitride layer by sputtering, or by depositing a titanium layer by sputtering and then subjecting it to heat treatment such as lamp annealing. 30-200
It is deposited to a thickness of approximately 300 ml. Next, using a method such as CVD, a polycrystalline silicon layer 4 of 100% is deposited on the titanium nitride layer 3.
It is deposited to a thickness of about 0 to 600 nm.
第２図は本発明の第１の実施例及び従来品の容量の電界
強度に対するリーク電流密度との関係を示す相関図であ
る。FIG. 2 is a correlation diagram showing the relationship between the leakage current density and the electric field strength of the capacitance of the first embodiment of the present invention and the conventional product.
リーク電流密度は、電極形成後に１０００°Ｃの熱処理
を行った後に測定した。また、電界強度はＴａ２０９層
２に印加される電界強度を示す。The leakage current density was measured after performing a heat treatment at 1000°C after electrode formation. Further, the electric field strength indicates the electric field strength applied to the Ta209 layer 2.
第２図に示すように、窒化チタン層３を”ｉ’ ａ ２
０、層２と多結晶層シリコン層４との間に入れることに
より、リーク電流を数桁以上大幅に減らすことができる
。これは多結晶シリコンとＴ ａ ２ｏ５との間に起る
次の反応
１３Ｓｉ ＋ ２Ｔａ２０ｇ−＋ ４ＴａＳｉ２モ５Ｓ
ｉ０２を窒化チタン層が効果的に防止しているためであ
る。これにより容量膜であるＴ’ａ２０５層２に生ずる
ピンホールやウィークスポットの発生を抑制し、容量膜
のリーク電流の増加や絶縁耐圧劣化や信頼性の低下を抑
制できる。As shown in FIG. 2, the titanium nitride layer 3 is
0. By inserting the polycrystalline silicon layer between the layer 2 and the polycrystalline silicon layer 4, leakage current can be significantly reduced by several orders of magnitude. This is the following reaction between polycrystalline silicon and Ta2o5: 13Si + 2Ta20g-+ 4TaSi2Mo5S
This is because the titanium nitride layer effectively prevents i02. This suppresses the occurrence of pinholes and weak spots in the T'a205 layer 2, which is a capacitive film, and suppresses an increase in leakage current of the capacitive film, deterioration of dielectric strength, and a decrease in reliability.
第３図は本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.
第１の実施例と同様にシリコン基板１にＴａ２０５層２
を５〜３０ｎｍの厚さに堆積し、次に窒化チタン層３を
３０〜２０ Ｏｒ＋ｍの厚さに堆積する。Similar to the first embodiment, a Ta205 layer 2 is formed on a silicon substrate 1.
is deposited to a thickness of 5 to 30 nm, and then a titanium nitride layer 3 is deposited to a thickness of 30 to 20 Or+m.
次に、スパッタやＣＶＤ等の方法でチタン層を１００〜
６００ ｎｍの厚さに堆積する。次に、ホトリソグラフ
ィ技術を用いてチタン層５をエツチングして電極を形成
する。ホトレジスト除去後、チタン層５をランプアニー
ル等で熱処理してチタン層５の周囲に窒化チタン層６を
形成してもよい。Next, a titanium layer of 100~
Deposit to a thickness of 600 nm. Next, the titanium layer 5 is etched using photolithography to form electrodes. After removing the photoresist, the titanium layer 5 may be heat-treated by lamp annealing or the like to form a titanium nitride layer 6 around the titanium layer 5.
本実施例では、電極はチタン層５と窒化チタン層３．６
とからなる。チタン層５を窒化チタン層３．６で囲むこ
とにより、チタン層５とＴａ２０５層２との反応を防ぎ
、かつチタン層５と層間膜との反応も防止できる。その
結果、容量部の電極形成後の熱処理を行っても、容量膜
のリーク電流の増加や絶縁耐圧の劣化がない容量が形成
できる。In this example, the electrodes are a titanium layer 5 and a titanium nitride layer 3.6.
It consists of. By surrounding the titanium layer 5 with the titanium nitride layer 3.6, a reaction between the titanium layer 5 and the Ta205 layer 2 can be prevented, and a reaction between the titanium layer 5 and the interlayer film can also be prevented. As a result, even if heat treatment is performed after forming the electrodes of the capacitor part, a capacitor can be formed without increasing the leakage current of the capacitor film or deteriorating the dielectric strength.
本実施例では、チタン層５とＴａ２０５層２との間の金
属窒化物層としての窒化チタン層３とチタン層５の周囲
を囲んでいる金属窒化物層としての窒化チタン層６とに
同じ窒化チタンを用いているが、これらの金属窒化物が
、例えば窒化チタンと窒化タングステンのように異なっ
ても、・その効果は本実施例と変わらない。他の金属窒
化物と他の導電体層との組合せは自由で、その効果は変
わらない。In this example, the titanium nitride layer 3 as a metal nitride layer between the titanium layer 5 and the Ta205 layer 2 and the titanium nitride layer 6 as a metal nitride layer surrounding the titanium layer 5 have the same nitride layer. Although titanium is used, even if these metal nitrides are different, such as titanium nitride and tungsten nitride, the effect is the same as in this embodiment. Other metal nitrides and other conductor layers may be freely combined, and the effect remains the same.
また、本発明の第１及び第２の実施例では、シリコン基
板上の容量を用いて本発明の説明を行ったが、多結晶シ
リコン、シリサイド、高融点金属等の電極上の容量に本
発明を用いても、その効果は同じである。容量膜にＴａ
２０５以外の金属酸化物、金属酸化物中にシリコンや他
の金属が混入している膜、あるいはシリコン酸化膜やシ
リコン酸化膜やシリコン窒化膜と金属酸化物とからなる
多層構造の容量膜を用いても、その効果は同じである。In addition, in the first and second embodiments of the present invention, the present invention was explained using a capacitor on a silicon substrate, but the present invention can also be applied to a capacitor on an electrode made of polycrystalline silicon, silicide, high melting point metal, etc. Even if you use , the effect is the same. Ta on the capacitive film
Using a metal oxide other than 205, a film in which silicon or other metal is mixed in the metal oxide, or a capacitive film with a multilayer structure consisting of a silicon oxide film, a silicon oxide film, a silicon nitride film, and a metal oxide. However, the effect is the same.
容量膜上の電極の導電体層及び導電体層と容量膜との間
の金属窒化物と導電体層の周囲のうちで容量膜と接しな
い部分を囲む金属窒化物との組み合せは自由であり、そ
の効果は本実施例の場合と変わらない、更に又、容量膜
上の電極を金属窒化物のみで形成してもよい。The combination of the conductor layer of the electrode on the capacitor film, the metal nitride between the conductor layer and the capacitor film, and the metal nitride surrounding the part of the periphery of the conductor layer that is not in contact with the capacitor film is free. The effect is the same as in this embodiment.Furthermore, the electrode on the capacitive film may be formed only of metal nitride.
以上説明したように、本発明は、容量部の電極と容量膜
との間に化学的に安定で比抵抗の小さい金属窒化物を挟
むことで、電極形成後の熱処理による容量膜と電極との
反応を抑制し、容量膜のリーク電流の増加や絶縁耐圧の
劣化がない優れた容量を得ることができるという効果が
ある。As explained above, in the present invention, by sandwiching a chemically stable metal nitride with low specific resistance between the electrode of the capacitive part and the capacitive film, the capacitive film and the electrode can be bonded by heat treatment after electrode formation. This has the effect of suppressing reactions and obtaining excellent capacitance without increasing leakage current or deteriorating dielectric strength of the capacitive film.
第１図は本発明の第１の実施例の断面図、第２図は第１
の実施例及び従来品の容量膜のリーク電流特性を示す特
性図、第３図は本発明の第２の実施例の断面図である。
１・・・シリコン基板、２・・・Ｔａ２０５層、３・・
・窒化チタン層、４・・・多結晶シリコン層、５・・・
チタン層、６・・・窒化チタン層。FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention.
FIG. 3 is a sectional view of the second embodiment of the present invention. 1... Silicon substrate, 2... Ta205 layer, 3...
・Titanium nitride layer, 4... Polycrystalline silicon layer, 5...
Titanium layer, 6...Titanium nitride layer.
Claims (1)
る第１の電極と、前記第１の電極上に設けられた弁作用
を有する金属酸化物から成る誘電体層と、金属窒化物ま
たは金属酸化物層から成り前記誘電体層を被覆する絶縁
層と、前記第１の電極に対向して前記絶縁膜上に設けら
れた第２の電極とで構成される容量部を備えたことを特
徴とする半導体装置。a first electrode made of a semiconductor layer or a conductor layer formed on a substrate; a dielectric layer made of a metal oxide having a valve action provided on the first electrode; and a metal nitride or a metal. A capacitor section comprising an insulating layer made of an oxide layer and covering the dielectric layer, and a second electrode provided on the insulating film opposite to the first electrode. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114288A JPH01283862A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114288A JPH01283862A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01283862A true JPH01283862A (en) | 1989-11-15 |
Family
ID=14634098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63114288A Pending JPH01283862A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01283862A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100294963B1 (en) * | 1991-09-19 | 2001-09-17 | 가네꼬 히사시 | Semiconductor device and its manufacturing method |
-
1988
- 1988-05-10 JP JP63114288A patent/JPH01283862A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100294963B1 (en) * | 1991-09-19 | 2001-09-17 | 가네꼬 히사시 | Semiconductor device and its manufacturing method |
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