JPH01283841A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01283841A
JPH01283841A JP63113255A JP11325588A JPH01283841A JP H01283841 A JPH01283841 A JP H01283841A JP 63113255 A JP63113255 A JP 63113255A JP 11325588 A JP11325588 A JP 11325588A JP H01283841 A JPH01283841 A JP H01283841A
Authority
JP
Japan
Prior art keywords
bonding
bonding pad
irregularity
wire
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63113255A
Other languages
English (en)
Inventor
Bunji Takeuchi
竹内　文二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63113255A priority Critical patent/JPH01283841A/ja
Publication of JPH01283841A publication Critical patent/JPH01283841A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/4805—Shape
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    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、ワイヤ・ボンディングによりチップと外部と
の接続を行う半導体装置に関する。
（従来の技術） 通常半導体集積回路チップのボンディング・パッドは、
配線材料と同じ金属材料１例えばＡｌやＡｕなどで形成
されている。最近、集積回路の高密度化に伴い、配線材
料により低抵抗の或いは安定性に優れた材料を用いるこ
とが検討されており、その場合にはボンディング性に問
題が生じる虞れがある。また高密度集積回路では端子数
が増えるにつれてボンディング・パッドの面積が小さく
なりつつある。その結果、ボンディング・ワイヤの接続
強度十分でなく、或いは接触抵抗が高くなり、信頼性や
特性の面で問題が生じる。
（発明が解決しようとする課題） 以上のように半導体集積回路では大規模化に伴って、配
線材料の変更やボンディング・パッドの面積縮小により
１機械的な或いは電気的なボンディング特性に問題が生
じてきている。集積回路に限らず１個別素子においても
、素子の多様化により同様の問題が生じる。
本発明は、この様な問題を解決して良好なボンディング
特性を実現した半導体装置を提供することを目的とする
。
［発明の構成］ （課題を解決するための手段） 本発明にかかる半導体装置は、素子形成された半導体チ
ップのボンディング・パッド表面に凹凸を設けたことを
特徴とする。
（作用） ボンディング昏パッド面に凹凸を設けることによって、
ボンディング・ワイヤとボンディング・パッドの接合面
積を実質的に大きくすることができる。従ってボンディ
ング・パッドにボンディング性に劣る材料を用いた場合
にも５十分なボンディング接続強度を得ることができる
。接続強度を従来と同程度とすれば、ボンディング・パ
ッドの面積を従来より小さくすることができる。このた
め、高密度集積回路等においてボンディング・パッド面
積を小さくした場合に特に有効であり。
各種半導体装置の信頼性向上を図ることができる。
（実施例） 以下１本発明の実施例を図面を参照して説明する。
第１図（ａ）（ｂ）は、一実施例の半導体素子のボンデ
ィング接続部の構造を示す平面図とそのＡ−Ａ″断面図
である。１は多数の素子が集積形成された半導体チップ
であり、その表面に配設された配線２の端部にボンディ
ング・パッド３が形成されている。ボンディング・パッ
ド３の表面は選択エツチングにより図示のようにモザイ
ク・パターンの凹凸が形成され、その面にこの実施例で
はボール・ボンディングによりワイヤが接続されている
。凹凸の段差は例えば０．２μｍ程度以上とする。ワイ
ヤの先端ボール部４は、ボンディング・パッド３の凹凸
の境界線が交差する中心を含んで四部と凸部に同時に接
合させている。
この実施例によれば、Ａｕ、Ａノ等通常の集積回路で用
いられる配線材料を用いた場合に、従来より１０〜２０
％程度ボンディング強度の向上が図られる。これにより
、半導体素子の信頼性は向上する。またボンディング・
ワイヤとボンディング・パッドの接合に要するチップ上
の面積は実質的に従来より小さくても、従来と同程度の
ボンディング強度が得られるため、ボンディング・パッ
ド等の縮小により集積回路の高集積化が容品になる。Ａ
ｕ、Ａ１等以外のボンディング性の劣る配線材料を用い
る場合にも、有効である。
第２図（ａ）（ｂ）は、他の実施例の構造を第１図（ａ
）（ｂ）に対応させて示す。この実施例では、第１図に
比べてボンディング・パッド３に形成する凹凸のモザイ
ク・パターンを細かくしている。
この実施例によっても、先の実施例と同様の効果が得ら
れる。モザイク・パターンの細かさは。
必要とする接合強度に応じて適当に選択することができ
る。
上記各実施例では、ボンディング・パッド表面の凹凸を
選択エツチングにより形成したが、他の方法で凹凸を形
成してもよい。例えば第３図は。
チップ１のボンディング・パッド部に予め凹凸を形成し
ておき、この上にボンディング・パッド３を通常の方法
で形成して下地の凹凸を表面に反映させるようにしたも
のである。第４図は、ボンディング・パッド３を第１の
金属層３１と第２の金属層３２により構成し、第２の金
属層３２をモザイク・パターンに選択エツチングして実
質的に凹凸を形成したものである。この構造は例えば、
第１の金属層３１がボンディング性の劣る配線材料であ
ってこれによりチップ内部配線が形成されている場合に
有効である。第２の金属層３２は、ボンディング性に優
れた材料であることが勿論好ましいが、この様な積層構
造は同種の金属層の場合にも有効である。凹凸のパター
ンも実施例のような単純なモザイク・パターンに限らず
９円形、多角形等適当に選択することができる。ボンデ
ィング法に関しても、実施例で説明したボール・ボンデ
ィングの他、ウェッジ・ボンディングでも本発明の適用
が可能である。
その池水発明は、その趣旨を逸脱しない範囲で種々変形
して実施することができる。
［発明の効果］ 以上述べたように本発明によれば、小さいボンディング
・パッド面積で大きいボンディング接続強度を実現した
半導体装置を得ることができる。
【図面の簡単な説明】
第１図（ａ）（ｂ）は１本発明の一実施例の一つのボン
ディング・パッド部の構造を示す平面図とそのＡ−Ａ−
断面図、第２図（ａ）（ｂ）は。 他の実施例のボンディング・パッド部の平面図とそのＡ
−Ａ−断面図、第３図および第４図は、更に他の実施例
のボンディング・パッド部の構造を示す断面図である。 １・・・半導体チップ、２・・・配線、３・・・ボンデ
ィング−パッド、４・・・ワイヤ先端ボール部。 出願人代理人　弁理士　鈴江武彦 第３目 第　４　図 第　２Ｆ （ｂ） 和

Claims (1)

    【特許請求の範囲】
  1. 　素子形成された半導体チップの表面にボンディング・
    パッドが形成され、このボンディング・パッドにワイヤ
    がボンディング接続された半導体装置において、ボンデ
    ィング・パッド表面に凹凸が形成されていることを特徴
    とする半導体装置。
JP63113255A 1988-05-10 1988-05-10 半導体装置 Pending JPH01283841A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63113255A JPH01283841A (ja) 1988-05-10 1988-05-10 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63113255A JPH01283841A (ja) 1988-05-10 1988-05-10 半導体装置

Publications (1)

Publication Number Publication Date
JPH01283841A true JPH01283841A (ja) 1989-11-15

Family

ID=14607514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63113255A Pending JPH01283841A (ja) 1988-05-10 1988-05-10 半導体装置

Country Status (1)

Country Link
JP (1) JPH01283841A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6871392B2 (en) * 2001-10-11 2005-03-29 Hitachi Global Storage Technologies Netherlands B.V. Method of constructing an integrated lead suspension
US7170172B2 (en) * 2001-12-13 2007-01-30 Nec Electronics Corporation Semiconductor device having a roughened surface
US7177276B1 (en) 2000-02-14 2007-02-13 Cisco Technology, Inc. Pipelined packet switching and queuing architecture

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177276B1 (en) 2000-02-14 2007-02-13 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
US7643486B2 (en) 2000-02-14 2010-01-05 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
US8018937B2 (en) 2000-02-14 2011-09-13 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
US8665875B2 (en) 2000-02-14 2014-03-04 Oracle International Corporation Pipelined packet switching and queuing architecture
US6871392B2 (en) * 2001-10-11 2005-03-29 Hitachi Global Storage Technologies Netherlands B.V. Method of constructing an integrated lead suspension
US6985335B2 (en) 2001-10-11 2006-01-10 Hitachi Global Storage Technologies Netherlands B.V. Integrated lead suspension and method of construction
US6989969B2 (en) 2001-10-11 2006-01-24 Hitachi Global Storage Technologies Netherlands B.V. Integrated lead suspension and method of construction
US7137189B2 (en) 2001-10-11 2006-11-21 Hitachi Global Storage Technologies Netherlands B.V. Method of constructing an integrated lead suspension
US7137188B2 (en) 2001-10-11 2006-11-21 Hitachi Global Storage Technologies Netherlands B.V. Method of constructing an integrated lead suspension
US7168154B2 (en) 2001-10-11 2007-01-30 Hitachi Global Storage Technologies Netherlands Bv Method of constructing an integrated lead suspension
US7170172B2 (en) * 2001-12-13 2007-01-30 Nec Electronics Corporation Semiconductor device having a roughened surface
US7560372B2 (en) 2001-12-13 2009-07-14 Nec Electronics Corporation Process for making a semiconductor device having a roughened surface

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