JPH01283828A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To arrange the constitution such that accumulation of charge does not occur in a gate electrode at ion implantation of impurity during transistor formation by forming a polycrystalline silicon layer which contains impurity in high concentration only at the rear side of a semiconductor substrate. CONSTITUTION:An oxide film 102 for element isolation, a gate insulation film 103, and impurity diffusion regions 104 and 105 are formed on a semiconductor substrate 101, and further polycrystalline silicon layers 106 and 107 are formed on the obverse and the reverse, respectively. Next, substance 108 which contains impurity such as spin-on-glass, etc., is applied on the polycrystalline silicon layer 107 and bardened. Subsequently, the semiconductor substrate is heat-treated and impurity is diffused in the polycrystalline silicon layer 107 to make it conductive, and then diffusion source 108 is removed so as to expose the polycrystalline silicon layer 107. Since the polycrystalline silicon layer 107 has conductivity this way, charge generated in a gate electrode 109 at ion implantation flows out to the outside, and it can avoid giving adverse effect on the gate insulation film 103.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing a semiconductor device, particularly a CMOS type semiconductor device having a different-polar gate transistor.

[Conventional technology]

FIG. 2 shows an example of a conventional method for manufacturing a CMOS type semiconductor device having different polarity transistors.

Step (1)...FIG. 2(a) Semiconductor substrate 201 on which element isolation oxide film 202, gate insulation 1 [1203, low concentration N-type impurity diffusion region 204, and low concentration P-type impurity diffusion region 205 are formed] A polycrystalline silicon layer 206 is formed on the front and back surfaces.

Step (2)...FIG. 2(b) The polycrystalline silicon 206 formed on the surface of the semiconductor substrate is patterned to form a gate electrode wiring 207.

Step (3)...Figure 2(c) Nch) Cover the transistor formation area with resist L
A P-type impurity 211 such as Bo is ion-implanted into the P ch transistor formation region, and the source/drain region 208 is
At the same time, when the gate electrode wiring 207 is applied, impurities of the same concentration are diffused into the gate electrode wiring 207.

Step (4)...Figure 2(d) Covering the Pch transistor formation area with resist LNc
h) Ion-implanting an N-type impurity 212 such as P+ into the transistor formation region to form a source/drain region 210;
At the same time, impurities of the same concentration are diffused into the gate electrode wiring 209 as well.

Through the above steps, a CMOS semiconductor device having gate electrodes of different conductivity types for Pch and Nch is formed on the same substrate.

[Problems to be Solved by the Invention] However, in the conventional technology described above, the back surface of the semiconductor substrate is insulated with a polycrystalline silicon layer that does not contain impurities and has a very high resistance value, so ion implantation is difficult. At this time, positive charges are accumulated in the gate electrode, and when they exceed a certain value, they flow into the substrate, causing destruction or deterioration of the gate insulating film. As a result, there is a problem that the functionality of the semiconductor device is impaired or the reliability is reduced.

The present invention is intended to solve these problems, and its purpose is to provide a method for manufacturing a semiconductor device that can manufacture a semiconductor device having a different polarity transistor at a high yield without impairing reliability. It is in a place where we provide.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a polycrystalline silicon layer on the front and back surfaces of a semiconductor substrate on which an oxide film for element isolation, a gate insulating film, an impurity diffusion region, etc. are formed. forming a thin film containing impurities on the back surface of the semiconductor substrate on which the polycrystalline silicon layer is formed; removing the thin film containing the impurity-containing thin film after heat-treating the semiconductor substrate; It is characterized by including a process.

Embodiment J An example of a method for manufacturing a semiconductor device having a different polarity gate according to the present invention is shown in FIGS. 1(a) to 1(d).

Each step will be explained below.

Step 1...FIG. 1(a) An oxide film 102 for element isolation, a gate insulating film 103, a low concentration N-type impurity diffusion region 104, and a low concentration P-type impurity diffusion region are formed on a semiconductor substrate 101 using a well-known technique. 105 is formed, and polycrystalline silicon layers 106, 1 are further formed on the front and back surfaces.
07 is formed.

Step 2...FIG. 1(b) A substance containing impurities such as SOG (spin, on, glass) is spin-coated onto the polycrystalline silicon layer 107 formed on the surface of the substrate and hardened by baking.

Step 3...FIG. 1(c) Heat treatment is performed on the semiconductor substrate on which a diffusion source is formed only on the back surface, and impurities are diffused into the polycrystalline silicon layer 107 formed on the back surface of the semiconductor substrate to make it conductive. After that, the diffusion source 108 is removed to expose the polycrystalline silicon layer 107.

Step 4...FIG. 1(d) The polycrystalline silicon layer 106 exposed on the substrate surface is patterned using a well-known technique to form a gate electrode 10 which also serves as a wiring.
form 9.

Thereafter, similarly to the conventional technique described above, impurity ions are implanted into the low concentration N-type impurity diffusion region 104 and the low concentration P-type impurity diffusion region 105, respectively, to form Pch and Nch transistors. At this time, since the polycrystalline silicon layer 107 that is electrically connected to the back surface of the substrate has impurity diffused and has conductivity, a large amount of charge generated on the substrate surface, especially the gate electrode 109, during ion implantation may be accumulated. It is possible to avoid leakage to the outside of the semiconductor device and adversely affect the gate insulating film 103.

In this example, a method of forming the diffusion source only on the back surface of the semiconductor substrate was shown, but if this is not possible due to the capability of the device, an oxide film containing impurities such as PSG may be formed all around the substrate. It is also possible to form the diffusion source only on the back surface by removing the portion formed on the top surface of the substrate by etching or the like.

[Effects of the Invention] As described above, according to the present invention, by forming a polycrystalline silicon layer containing a high concentration of impurities only on the back surface of a semiconductor substrate, the semiconductor substrate is back side and outside (part of ion implanter)
This makes it possible to avoid charge accumulation in the gate electrode, and as a result, it is possible to form a semiconductor device having a different polarity transistor without adversely affecting the gate insulating film. have

[Brief explanation of the drawing]

1(a) to 1(d) are main cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS.
(d) is a main process sectional view showing a manufacturing process of a semiconductor device according to a conventional technique. 101.201...Semiconductor substrate 102.202...Oxide film for element isolation 103.203...Gate insulating film 104.204...Low concentration N-type impurity diffusion region 105.
205...Low concentration P type impurity diffusion region 106.206...
・Polycrystalline silicon layer 107...Polycrystalline silicon layer 108...Impurity diffusion source 109...Wiring 207.2 that also serves as a gate electrode
09...Wiring that also serves as gate electrode 208.210...Source, drain region 211...P-type impurity 212...N-type impurity and above Applicant Seiko Epson Corporation Agent Patent Attorney Kamiyanagi Masa Homare (1 other person) $ 2 Figure

Claims (1)

[Claims] A step of forming a polycrystalline silicon layer on the front and back surfaces of a semiconductor substrate on which an oxide film for element isolation, a gate insulating film, an impurity diffusion region, etc. are formed, and a step of forming an impurity layer on the back surface of the semiconductor substrate on which the polycrystalline silicon layer is formed. A method for manufacturing a semiconductor device, comprising the steps of forming a thin film containing impurities, and removing the thin film containing impurities after heat-treating the semiconductor substrate.