JPH0128325B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a displacement conversion device that converts physical displacement based on changes in physical quantities such as pressure, tension, temperature, amount of light, etc. into electrical signals. Such displacement converters are used to detect flow rates or pressures in various processes, convert them into electrical signals, and transmit the detection results to a remote receiving unit. The structure shown in the figure is proposed in Japanese Patent Application Laid-Open No. 53-9565. That is, as shown in the block diagram of Figure 1,
The resonant circuit of the oscillator 101 includes a variable reactance element 102 whose capacitance or inductance changes depending on the physical displacement to be detected, and a fixed reactance element whose capacitance or inductance changes only in response to physical changes in the ambient conditions. Element 10
3, an oscillation circuit is constructed by switching each reactance element 102, 103 with a switch 104, and when the variable reactance element 102 is selected, the oscillator 101 outputs an oscillation output of frequency _f1 . If the fixed reactance element 103 is selected, the oscillator 101
generates an oscillation output with a frequency _f2 . Further, the output of the oscillator 101 is transmitted to the switch 105.
The switch 105 is connected to the addition terminal U or the subtraction terminal D of the addition/subtraction counter 106 through the addition/subtraction counter 106, and when the switch 104 is placed on the variable reactance element 102 side, the switch 105 is switched to the addition terminal U side, and the switch 105 is switched to the addition terminal U side. 104 is fixed reactance element 1
03 side, the switch 105 is switched to the subtraction terminal D side, and the switches 104 and 105 are switched synchronously. Therefore, if the switch 104 is initially on the variable reactance element 102 side, the frequency f ₁
The addition/subtraction counter 106 performs an addition count based on the output of , and the contents of the addition/subtraction counter 106 increase as shown in FIG. 2a. On the other hand, the count output of the addition/subtraction counter 106 is
It is applied to the logic circuit 107, and when the count output of the addition/subtraction counter 106 reaches the upper limit value US,
The output of the logic circuit 107 is generated and the switch 104,1
Switch 05 to the opposite side. Then, a subtraction count based on the output of frequency f ₂ is performed in the decrementable counter 106, and its contents decrease as shown in FIG. 2a. When this reaches the limit value DS, the output of the logic circuit 107 disappears. Then, the switches 104 and 105 return to their initial states, and the addition count is performed again using the output of the frequency _f1 , and the above operation is repeated. For these circuits, a DC power supply 108, resistors 109 and 110 of equal resistance value, and switch 1
11 is provided, and the switch 111 is also a logic circuit 1.
Since the output of the switch 111 is controlled by the switch 07 and switches to the side in synchronization with the switches 104 and 105, the output of the switch 111 is as shown in FIG.
As shown in , the time T ₁ is inversely proportional to the frequency f ₁ and
A return pulse signal corresponding to a time T ₂ which is inversely proportional to the frequency f ₂ is obtained, and when this is averaged in the low-frequency wave generator 112, a DC signal corresponding to the positive and negative waveform areas of the return pulse signal is obtained. , this is output terminal 11
3,114. Therefore, since the frequency f ₁ changes depending on the physical displacement to be detected, and the frequency f ₂ does not change if the physical conditions of the surroundings are constant, the duty ratio of the return pulse signal (T ₁ − T ₂ )/(T ₁ +T ₂ ) is
Since it changes based on the frequency f ₁ , the DC signal corresponding to the physical displacement to be detected is output to the output terminal 113,
Obtained at 114. Note that the influence of the ambient temperature and the like acts equally on the variable reactance element 102 and the fixed reactance element 103 as a physical change in the ambient condition, so the physical change in the ambient condition does not appear in the detection results. However, when using the configuration shown in FIG. 1, an expensive addition/subtraction counter 106 is used, a logic circuit 107 with a complicated configuration is required, and a DC power supply 108 to a switch 111 are required separately, so the manufacturing cost increases due to the complexity of the configuration. This has the disadvantage of being expensive. In addition, in Fig. 1, the value of capacitance is C,
When the value of inductance is L, the oscillation frequency f is determined by f = 1/2π√, so f does not change due to other constants, but it has the disadvantage of non-linear conversion characteristics and the oscillation The rise characteristic at the time of frequency switching is poor, and the oscillation waveform does not quickly become a predetermined oscillation waveform, which also has the disadvantage of causing measurement errors during this period. The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional technology, and uses, for example, a relaxation type oscillator whose oscillation frequency is determined by capacitance and resistance, and obtains linear conversion characteristics. The present invention provides an extremely effective displacement converting device whose circuit configuration is simplified by using a simple counter. The details of the present invention will be explained below with reference to FIG. 3 and subsequent figures showing embodiments. FIG. 3 is a block diagram showing the basic configuration.
It consists of a differential capacitor 301, a switching circuit 302, an oscillator 303, an arithmetic unit 304, and an output unit 305.
307 and a movable electrode 308, the movable electrode 308 responds to the physical displacement to be detected.
In order to move between the fixed electrodes 306 and 307, the capacitance between the fixed electrode 306 and the movable electrode 308
C ₁ and the capacitance C ₂ between the fixed electrode 307 and the movable electrode 308 change differentially, and these are used as the first and second impedance elements. Furthermore, the switching circuit 302 includes switches 309 and 310 such as gate circuits, which are turned on and off alternately _. , C ₂ are alternately switched and connected, and this switching is controlled by an arithmetic unit 304, which will be described later. Therefore, when the capacitance C ₁ is connected to the oscillator 303, the oscillation frequency is determined by this, and the oscillator 303 uses the frequency f ₁ as the first frequency.
If the capacitance C ₂ is connected in the same way, the oscillator 303 generates an oscillation output as the second frequency.
Generates an oscillation output of f ₂ . This oscillation output is given to the calculation section 304, where the calculation of (f ₂ −f ₁ )/(f ₁ +f ₂ ) is performed,
As a result, an output corresponding to the difference between frequencies f ₁ and f ₂ is obtained, and by calculating (f ₂ − f ₁ )/(f ₁ + f ₂ ),
It is assumed that equivalent changes in the frequencies f ₁ and f ₂ in the same direction and in response to physical changes in the ambient conditions are eliminated. The output of the calculation section 304 is given to the output section 305, where it is converted into a signal in a predetermined format indicating the measured value D, such as a unified signal current having a variation range of 4 to 20 mA used in the field of industrial measurement. It is converted and then sent. FIG. 4 is a circuit diagram showing a specific configuration,
MOSFET (Metal Oxide Semiconductor Field)
Effect Transistor) 401 and 402 constitute a switching circuit 302, and MOSFET 403
406 constitute a two-stage complementary inverting amplifier, and the stages are connected to the movable electrode 308 via a resistor 407 to form an oscillator 303. The calculation unit 304 also includes a counter 408 having count outputs 1 to n, and resistors 409 and 4.
10, consists of an averaging means using an integrating circuit consisting of capacitors 411 and 412, and an oscillator 3
A counter 408 counts a fixed number of outputs having frequencies f ₁ and f ₂ from 03, and turns on or off FETs 401 and 402 alternately depending on the "H" (high level) or "L" (low level) of the count output n. While in the off state, the "H" and "L" pulse signals obtained from the count output n are directly averaged by an integrating circuit, and the resulting DC signal is provided to the output section 305. The output section 305 includes a constant voltage diode 413, resistors 414 and 415, a potentiometer 416,
Resistor 417, operational amplifier 418, FET (Feeld
Effect Transistor.) 419, 420 and a feedback resistor 421, and the output terminal 11
The power supplied from the receiving section via the two-wire line connected to 3 and 114 is stabilized by a constant current circuit with FET 419 and a constant voltage diode 413, and is used as a power source for the operational amplifier 418 side, and the potentiometer 416 The difference between the reference voltage set by and the DC voltage from the integrating circuit is amplified by the operational amplifier 418, and its output
By controlling FET420, output terminals 113 and 11
The current between 4 is variable. Further, since negative feedback from the resistor 421 is applied to the non-inverting input of the operational amplifier 418 via the resistor 417, the voltage between both inputs of the operational amplifier 418 becomes almost zero. The electric current flowing from the FET 420 to the resistor 421 is balanced, and this becomes an output current corresponding to the DC voltage from the integrating circuit. FIG. 5 is a time chart showing the operating status of FIGS. 3 and 4. When the count output n of the counter 408 is "L", the MOSFET 401 is turned on and the MOSFET 402 is turned off, thereby turning on the oscillator 303. , capacitance C ₁ and resistor 407
The counter 408 generates an oscillation output with a frequency f ₁ that is inversely proportional to the product of the resistance value of
In order to maintain this state until the count number is counted again, the count output n is “H”.
During this period, MOSFET401 is off, MOSFET4
02 is turned on, and at this time the oscillator 303
generates an oscillation output with a frequency f ₂ that is inversely proportional to the product of the capacitance C ₂ and the resistance value of the resistor 407, which is counted by the counter 408. When the count number N is reached, the count output n is set to “ By returning to "L" and repeating this operation, the counter 4 is shown in FIG. 5a.
The count status of 08 is shown in the figure b as the count output n.
The counting period T ₁ for frequency f ₁ is shown as the change in
is N/f ₁ , and the count period T ₂ of frequency f ₂ is N/f ₂ . Here, the counter 408 is set to CMOS.
(Complementary Metal Oxide
Semiconductor.) If you use an integrated circuit, you can obtain an output with a peak value that is almost equal to the power supply voltages +E and -E. Therefore, when the count output n is "H", +E
occurs, and -E occurs when it is "H", so
When the pulse signal of the count output n is averaged in the integrating circuit, the output voltage is given by the following equation. =1/f ₂ /1/f ₂ +1/f ₁・(+E)1/f ₂ /1/f ₂
+1/f ₁ ·(-E) = f ₂ −f ₁ /f ₁ +f ₂ ·E (1) That is, the calculation unit 304 performs the predetermined calculation shown in equation (1). Note that the capacitances C ₁ and C ₂ are the fixed electrodes 306,
The dielectric between the oscillator 307 and the variable electrode 308 causes a change in dielectric constant due to temperature fluctuations, which causes the capacitance value to change, and the characteristics of the oscillator 303 itself also change due to changes in temperature, power supply voltage, etc. change,
These factors cause unplanned changes in the frequencies f ₁ and f ₂ , but if the fixed electrodes 306 and 307 and the movable electrode 308 are enclosed in the same case, the capacitances C ₁ and C ₂ will change in the same direction. And it becomes equal, and furthermore,
Since a single oscillator 303 is used, the frequency f ₁
The changes in and f ₂ are multiplied by the same coefficient u, and the changed frequencies f ₁ ' and f ₂ ' are expressed by the following equations. f ₁ ′=uf ₁ , f ₂ ′=uf ₂ ………(2) Now, from the relationship of equation (2), find the output voltage according to equation (1) = uf ₂ −uf ₁ /uf ₁ +uf ₂・E=f ₂ −f ₁ /f ₁ +f ₂・E……
...(3) That is, by calculating equation (1), changes in frequencies f ₁ and f ₂ due to fluctuations in temperature, power supply voltage, etc. do not appear in the output of the calculation unit 304, but only in the physical displacement to be detected. Accurate DC voltage can be obtained. Also,
By using CMOS circuits in each part. While low power consumption is achieved, the output of the counter 408 can be directly averaged. FIG. 6 is a block diagram when a square root calculation unit 601 is added to the one shown in FIG. When measuring the flow rate of a fluid, etc., the square root calculation unit 601 is inserted between the calculation unit 304 and the output unit 305 to obtain an output signal √ proportional to the flow rate, etc., since the detection result of the square characteristic is obtained. I am assuming that I will get it. Note that a known square root calculation circuit may be used as the square root calculation unit 601. FIG. 7 is a circuit diagram when a compensation circuit is added to compensate for the nonlinearity of the differential capacitor 301 or to more strictly compensate for the temperature characteristics as a whole. connects the movable electrode 308 to the reference potential, and connects the FET 7 of the same polarity that constitutes the switching circuit 302.
02, 703 with or without an inverter 704, a charge/discharge type oscillator 303 is configured by a resistor 705 and an inverter 706 having hysteresis characteristics, and further,
NAND gate 707, FET 708, resistor 70
9, 710 and the thermistor 711 constitute a temperature compensation circuit 712. Therefore, the count output n of counter 408
When is “H”, the NAND gate 707 is turned on, and the output of the inverter 706 causes the FET
708 performs on/off operation, resistor 709
The voltage obtained by dividing the power supply voltage +E by the resistor 710 and thermistor 711 is applied to the inverter 7 via
This is applied to the capacitance C ₁ via the FET 702 which is on at this time, giving an accelerating effect to the oscillation of the frequency f ₁ , but this effect causes the thermistor 711 to The temperature characteristics can be compensated by changing according to the resistance value. However, the inverter 70 is connected via FET 708.
The voltage applied to the input side of 6 is not limited to the thermistor 711, but various voltages can be used depending on the purpose. Note that by using the hysteresis characteristic of the inverter 706 such that the input side threshold level at which the output is inverted is high at the rising edge and low at the falling edge, charge/discharge type relaxation type oscillation can be performed. Further, if a NOR gate is used in place of the NAND gate 707, it can participate in the oscillation at the frequency _f2 , and the same result can be obtained. FIG. 8 shows a case in which capacitors 801 and 802 whose capacitances differentially change are used as the variable impedance elements shown in FIG. is a block diagram of an AND gate 803 having the same hysteresis characteristics as in FIG.
and resistors 804 and 805 for feedback charging constitute an oscillator 303, and an AND gate 80
A NAND gate 806 and an inverting input NAND gate 807 are inserted as a switching circuit 302 between the output of the counter 408 and the resistors 804 and 805, and when the count output n of the counter 408 is "H", the NAND gate is inserted.
The gate 806 is turned on, and when the output is "L", the inverting input NAND gate 807 is turned on, thereby completing the oscillation circuit alternately. In FIG. 8, when the n-bit output of the counter 408 is at a high level, the NAND gate 806 functions as an inverter, and the NAND gate 807
is in a state where its output is held at a high level. In this case, the high level output (+E) of the NAND gate 807 is connected to the capacitor 802 and the resistor 80.
The AND gate 803 functions as a Schmitt trigger because the potential at one input terminal of the AND gate 803 connected to the connection point with 5 is held at a high level +E. Therefore, in this case, capacitor 801, AND
An oscillation circuit including a gate 803, a NAND gate 806, and a resistor 804 is formed and repeats oscillation in accordance with the capacitance value of the capacitor 801. Counter 4 counts this oscillation frequency by n bits.
The output of 08 inverts its level. Due to this level reversal, NAND game 8
06 is fixed at a high level, and the NAND gate 807 side repeats oscillation in response to the capacitance value of the capacitor 802. Incidentally, the hysteresis width of the AND gate 803, which functions as a Schmitt trigger, has an important meaning in these oscillations. The above points will be explained using the waveform diagram shown in FIG. When the rising level UL at the input threshold level of the AND gate 803 is lower than zero potential, as shown in FIG. ), the terminal voltage rises due to charging of the capacitor 801 (or 802) and reaches the rising level UL. At this point, the output of AND gate 803 quickly becomes high level, so that NAND gate 806 (or inverting input NAND gate 807)
The output becomes low level and the discharge begins. On the other hand, if the rising level UL becomes higher than the zero potential, as shown in Figure 9 b and c, the point at which the gradual discharge begins will be delayed and the charging period t ₁ will be extended. The discharge period _t2 is shortened. However, if the difference between the rising level UL and the falling level DL is constant, there will be no change in frequencies f ₁ and f ₂ due to fluctuations between the rising level UL and the falling level DL, and errors based on this will be avoided. Ru. In addition, the integrated circuit is called AND gate 8.
03 is suitable because even if the absolute values of the rising level UL and the rising level DL change due to fluctuations in temperature, power supply voltage, etc., the difference between the two levels UL and DL remains approximately constant. FIG. 10 shows feedback charging resistors 804 and 80 used as first and second fixed impedances.
₅ is a circuit diagram in the case of using different resistance values to obtain non _- linear conversion characteristics.
1001 and 1002 are connected in parallel, and the counter 40 is connected with or without the inverter 704.
On/off control is performed by the count output n of FET 8, and in the oscillation circuit via resistor 804 or 805, the oscillation circuit on the side where FET 1001 or 1002 is turned on is completed, and oscillation at frequencies f ₁ and f ₂ is performed. The output is generated alternately. Therefore, if the calculation section 304 calculates equation (1), the resistance value R 1 of the resistor 804, the resistance value R ₁ of the resistor 804,
When the resistance value of 05 is _R2 , the value indicating the averaged DC voltage is given by the following equation. =1/C ₂・R ₂ −1/C ₁・R ₁ /1/C ₁・R ₁ +1/
C ₂・R ₂ ………(4) Therefore, for example, R ₁ = 80KΩ, R ₂ = 100KΩ
Assuming that the capacitances C ₁ and C ₂ vary differentially with respect to 50PF, the relationships shown in Table 1 are obtained.

[Table] In other words, taking the difference between capacitance C ₁ and C ₂ on the horizontal axis,
If the relationship in Table 1 is shown graphically, it will be shown in FIG. 11, and a non-linear conversion characteristic of curvature according to R ₁ and R ₂ can be obtained. In addition, if the relationship between R ₁ and R ₂ is switched, the 11th
A concave characteristic with a tendency opposite to that shown in the figure is obtained, and by selecting R ₁ and R ₂ , an arbitrary conversion characteristic can be realized, and the nonlinearity of the differential capacitive element 301 can be completely compensated. FIG. 12 shows NAND gates 1201, 120
2, the first and second oscillators 303A, 303
B and the same gates 1201, 120
2 is also used as a switching circuit 302, and the NAND gates 1201 and 1202 are turned on and off with or without an inverter 704.
The oscillation circuit is controlled to be off alternately, thereby completing the oscillation circuit, and the oscillation output having a frequency f ₁ from the NAND gate 1201 or the oscillation output having a frequency f ₂ from the NAND gate 1202 is connected to the NAND gate. Counter 40 via gate 1203
It is given to 8. FIG. 13 shows the oscillation waveform in FIG. 12, and when the input threshold level at which the outputs of the NAND gates 1201 and 1202 are inverted is V _TR , the discharge period t ₁ for the capacitance C ₁ or C ₂
, and the charging period t ₂ from the same capacity C ₁ or C ₂ is expressed by the following equation, where E is the power supply voltage. t ₁ = -R・C (l _o・E−V _TR /E) ………(5) t ₂ = −R・C (l _o・V _TR /E) ………(6) R is the resistance value of resistors 804 and 805,
C is the capacitance value of the capacitances C ₁ and C ₂ . Therefore, as shown in FIGS. 13a to 13c, waveforms corresponding to changes in the threshold level V _TR are as follows.
Even if the threshold level V _TR changes, frequency changes are suppressed and accurate conversion characteristics can be obtained. In addition, as shown in FIG. 10, resistors 804 and 805
It is also possible to obtain arbitrary conversion characteristics by making the resistance values different. In addition, the first and second oscillators 303
Keep the circuits of A and 303B in a complete state at all times,
The same applies if these outputs are alternately switched by a gate circuit or the like and fed to the counter 408. FIG. 14 is a block diagram showing a modified embodiment of the calculation unit 304, in which the first and second impedance elements are variable capacitance elements whose capacitance changes according to the physical displacement to be detected. and,
A capacitive element whose capacitance changes only in response to physical changes in ambient conditions is used, and only the frequency f ₁ changes depending on the physical displacement to be detected. Further, as the counter 408, it is possible to use a general counter whose peak value of the count output n is not particularly equal to the power supply voltage. In the figure, a CMOS type inverter 1401 is connected to the count output n, and its output is given to an integrating circuit consisting of a resistor 409 and a capacitor 411, and a pulse signal from the count output n is connected to a CMOS type inverter 1401. An inverting input of an operational amplifier 1405 is supplied through a buffer 1402 and an integrating circuit consisting of a resistor 1403 and a capacitor 1404, and the output of the amplifier 1405 is
Ec is the inverter 1401 and buffer 14
Since the output peak value of the CMOS type circuit is determined to be approximately equal to the power supply voltage Ec, the buffer 1402 and the operational amplifier 1
405, a negative feedback loop is formed. Therefore, when the reference voltage E _R applied to the non-inverting input of operational amplifier 1405 and the voltage at the inverting input become approximately equal, the negative feedback loop is balanced, and under this condition, the power supply The voltage Ec is determined, a counting operation similar to that shown in FIG. 5a is performed in the counter 408, and the pulse signal shown in FIG. is approximately equal to the power supply voltage Ec, and the output thereof is averaged by the resistor 1403 and the capacitor 1404, so that the following equation holds true. E _R = Ec・T ₂ /T ₁ +T ₂ ………(7) ∴Ec=E _R・T ₁ +T ₂ /T ₂ ………(8) Also, from the integrating circuit of resistor 409 and capacitor 411, The resulting output voltage Eout is shown in Figure 5b.
This is the result of inverting the waveform of , and averaging the waveforms whose peak values are approximately equal to the power supply voltage Ec, so it is expressed by the following equation. Eout=Ec・T ₁ /T ₁ +T ₂ ......(9) If we substitute equation (8) into equation (9), Eout=E _R・T ₁ /T ₂ ......(10) Therefore, , the output voltage Eout will be proportional to T ₁ /T ₂ , and if you use this to calculate the following formula using the subtraction circuit, 1-T ₁ /T ₂ = T ₂ - _{T 1} /T ₂ ...... (11) is obtained, and the DC voltage corresponds to the capacitance change of the variable capacitance element, so the purpose is achieved. Note that by slightly modifying the calculation unit 304, calculations of the following equations can be made, and can be applied depending on the conditions. T ₁ −T ₂ /T ₁ +T ₂ orT ₁ −T ₂ /T ₁ orT ₁ /T ₁ +T ₂ (12) FIG. 15 is a circuit diagram showing an open-loop type output section 305, The operational amplifier 418 is supplied with the DC voltage from the calculation unit 304 via input resistors 1501 and 1502, and the non-inverting input of the amplifier 418 is connected to the output terminal 114 as a reference potential via a resistor 1503. At the same time, negative feedback is applied to the inverting input by a resistor 1504, and the output of the operational amplifier 418 is connected to the operational unit 304.
The output voltage e 1 is generated in response to the DC voltage from the output voltage e ₁ . In addition, the power supply on the operational amplifier 418 side is as shown in FIG.
Constant current circuit 1505 using FET419 etc.,
On the other hand, a constant voltage circuit 1506 is connected between the output terminals 113 and 114 to generate a constant voltage e ₂ .
A resistor 1507 connected between this output and the operational amplifier 418 has a resistance value of R _Q
When , a current of (e ₂ /e ₁ )/R _Q flows through it. FIG. 16 is a circuit diagram showing a specific example of a constant voltage circuit 1506, in which a constant voltage e ₃ is obtained by a constant voltage circuit 1601 and a constant voltage diode 1602, and is used as a power source and a non-inverting input voltage for an operational amplifier 1603. , the gate of a transistor 1604 whose drain and source are connected to the output terminal 113 and the inverting input of the operational amplifier 1603 is controlled by the output of the amplifier 1603.
The source of 604 is fixed at a constant voltage _e2 . Therefore, the transistor 1604 has (e ₂ −
e ₁ )/R _Q current flows, and this current flows to output terminal 1
13 and flows into the operational amplifier 418 via the drain and source of the transistor 1604. Therefore, the current of resistor 1507 flows back to output terminal 114 via the output impedance of operational amplifier 418, and a current according to the DC voltage from calculation section 304 flows between output terminals 113 and 114. Note that if the operational amplifier 418 cannot sufficiently absorb the current, as shown in FIG.
Transistor 1701 for the output stage to the output side of 18
Just insert . In addition, when using the configuration shown in FIG. 15, there is no direct closed-loop negative feedback between the output terminals 113, 114 and the operational amplifier 418, but an open-loop configuration exists, so the output section Constant voltage circuit 1
It becomes easy to adjust the operational amplifier 418 side separately from the 506 side. FIG. 18 is a circuit diagram when the output current between the output terminals 113 and 114 is fed back to the input side of the output section 305 in a pulsed manner.
Invert NAND gates 1801-1804
as well as similar switches 1805~
1808 is used, and during the count output of the counter 408, the most significant bit Q ₇ and the adjacent lower bit Q ₆ are used to generate a negative pulse signal obtained from the most significant bit Q ₇ according to the output current. It is supposed to give you a return. That is, the oscillator 3 similar to that shown in FIG.
03 and the most significant bit of the counter 408
Switches 1805 and 1806 controlled by Q ₇ with or without inverter 1083
The inverter 1804 is configured by the lower bit _Q6 in the integrating circuit consisting of the resistor 409 and the capacitor 411.
switch 18 controlled with or without
07 and 1808 provide a signal obtained by inverting the pulse signal from the most significant bit _Q7 by an inverter 1803, and a signal obtained from a potentiometer for negative feedback of the output current. Further, the output section 305 is almost the same as that shown in FIG. The output current is controlled by the output of 418, and the output current is varied. Therefore, in the oscillator 303, when the most significant bit _Q7 of the counter 408 is "L", the switch 1805 is turned on, and an oscillation output with a frequency _f1 corresponding to the capacitance _C1 is generated, and by counting this, When the most significant bit _Q7 turns to "H", the switch 1806 is turned on to generate an oscillation output with a frequency _f2 corresponding to the capacitance _C2 , and this is repeated, but the most significant bit _Q7 The pulse signal from is inverted by an inverter 1803, and is then inverted by a switch 1807 controlled by the output of the lower bit _Q6 , which repeats "H" and " _L " at twice the frequency of the most significant bit Q7. When switch 1807 is turned off, switch 1
Since the switch 808 is turned on, the feedback voltage Ef from the potentiometer 1809 is inserted during this time. Note that CMOS type circuits are used for the inverters 1801 to 1804 and the counter 408, and the output peak value of the switch 1807 is approximately equal to the power supply voltage +E.
As shown in the figure, while the switch 1807 is on, a pulse signal having a peak value of the power supply voltage +E with respect to zero potential is obtained. Furthermore, since the switches 1807 and 1808 are controlled to be turned on and off by the lower bit _Q6 adjacent to the most significant bit _Q7 , the period _T1 corresponds to the frequency _f1 and the period _T2 corresponds to the frequency f2 _. This means that the feedback voltage Ef is inserted in the negative direction during the 1/2 period, and the periods T ₁ and T ₂ are differentially inserted as shown in FIGS. Change. However, due to the negative feedback effect caused by the insertion of the feedback voltage Ef, as shown in Figure 19c, equilibrium is reached in a state where the area of the negative waveform due to the feedback voltage Ef is equal to the area of the positive waveform due to the power supply voltage +E. However, since the difference between the voltage obtained by averaging this signal and the reference voltage Es set by the potentiometer 416 is proportional to the feedback voltage Ef, the following equation holds true. Es−+E・T ₁ /2 (T ₁ + T ₂ )=Ef (13) Therefore, in the equilibrium state shown in equation (13), T ₁
An output current corresponding to (T ₁ +T ₂ ) can be obtained, and the purpose can be achieved. FIG. 20 shows a circuit in which the influence of the distributed capacitance between the input and output of the inverter 706 and the AND gate 803 is eliminated in the charge/discharge type oscillator 303 shown in FIGS. 7, 8, and 10, and the inverter 2001 and By adding the capacitor 2002, the distributed capacitance between the input and output of the inverter 706 can be increased.
The influence on the oscillation frequency based on Cs is compensated. That is, when there is no inverter 2001 and capacitor 2002, the capacitance C ₁ or
When the output of impedance 706 is reversed from "H" to "L" or from "L" to "H" due to the rise or fall of the terminal voltage of _C2 , the distributed capacitance
Discharging or charging via Cs is performed on the capacitance _C1 or _C2 , and as shown in FIG. 21a, a sudden change occurs in the oscillation waveform near the rising level UL and falling level DL, As a result, the waveform that should originally change as shown by the dotted line in the figure changes as shown by the solid line, the charging and discharging cycle is shortened, and an error occurs in the oscillation frequency. Furthermore, the charging/discharging status due to this distributed capacitance Cs changes depending on the capacitance ratio between the capacitance C ₁ or C ₂ and the distributed capacitance Cs, and if the capacitances C ₁ and C ₂ change depending on the physical quantities, , the frequency error also changes accordingly, resulting in a nonlinear error in the conversion characteristics. Therefore, as shown in FIG.
Insert an inverter 2001 into the output side of the inverter 706, and connect a capacitor 2 with a capacitance equal to the distributed capacitance Cs between its output and the input of the inverter 706.
002, charging by the capacitor 2002 is performed when discharging by the distributed capacitance Cs, and discharging by the capacitor 2002 is performed when charging by the distributed capacitance Cs, as shown in Fig. 21b.
As shown in FIG. 2, the same oscillation period as the waveform indicated by the dotted line in FIG. In addition, in the above explanation, a differential capacitor element or a variable capacitor element and a fixed capacitor element are used as the first and second impedance elements, but strain gauges, thermistors, etc. are used as the first and second impedance elements. Using a differential resistance element or a variable resistance element and a fixed resistance element, the resistors 407, 705, 804, 80 of the oscillator 303
A capacitor may be inserted in place of 5. Alternatively, the same effect can be obtained by omitting the integrating circuit and the output section 305 as the averaging means, transmitting the pulse signal from the counter 408 as it is, and then providing an integrating circuit in the receiving section. The present invention can be modified in various ways, such as using an indicating instrument that indicates the average value of the pulse signal, such as a movable ring-type instrument, as the averaging means instead of the circuit. As is clear from the above explanation, according to the present invention, since it is mainly composed of a digital circuit, there is no need for adjustment, and it can also be used as a counter.
By using a CMOS type, an output with a peak value approximately equal to the power supply voltage can be obtained, which can be averaged immediately, simplifying the circuit configuration. In addition, by using CMOS type circuits in each part,
It has characteristics such as low power consumption current, and in the case of a two-wire transmitter, it is easy to set the power consumption current below the specified minimum current value between the output terminals,
Remarkable effects can be obtained in measurement of process quantities in various manufacturing processes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a time chart showing the operating status of FIG. Figure 3 is a circuit diagram showing the specific configuration, Figure 5 is a time chart showing the operating status of Figures 3 and 4, and Figure 6 is when a square root calculation section is added to Figure 3. 7 is a circuit diagram when a compensation circuit is added, FIG. 8 is a block diagram when the oscillation circuit is completed by a switching circuit, FIG. 9 is a diagram showing the oscillation waveform of FIG. 10
The figure is a circuit diagram when obtaining non-linear conversion characteristics, Figure 11 is a diagram showing the conversion characteristics of Figure 10, Figure 12 is a block diagram when NAND gates are used in the oscillator and switching circuit, Fig. 13 is a diagram showing the oscillation waveform of Fig. 12, Fig. 14 is a block diagram showing a modification of the arithmetic section, Fig. 15 is a circuit diagram showing an open-loop type output section, and Fig. 16 is a diagram showing the oscillation waveform of Fig. 12. Figure 15 is a circuit diagram showing a specific example of the constant voltage circuit, Figure 17 is a circuit diagram when an output stage is added to the operational amplifier in Figure 15, and Figure 18 is a circuit where the output current is fed back in a pulsed manner. Figure 19 is a diagram showing the waveform of the pulse signal in Figure 18, Figure 20 is a circuit diagram when compensating for an error in the oscillation frequency due to distributed capacitance between the input and output of the inverter, and Figure 21 is a diagram showing the waveform of the pulse signal in Figure 20. FIG. 3 is a diagram showing changes in oscillation waveform. C ₁ , C ₂ ... Capacitance (first and second impedance elements), 301 ... Differential capacitance element, 3
02... Switching circuit, 303... Oscillator (relaxation type oscillator), 408... Counter, 409, 401...
...Resistor, 411,412...Capacitor, 80
4,805...Resistor (first and second fixed impedance).

Claims (1)

[Scope of Claims] 1. First and second impedance elements whose respective ends are commonly connected and whose impedance changes in accordance with the physical displacement to be detected, and the other end of the first or second impedance element. and the commonly connected common connection point, the first or second impedance being determined by the resistance value and capacitance value, with the first or second impedance being one of the circuit elements.
and a relaxation type oscillator that oscillates a second frequency, a counter that counts the oscillation output of the relaxation type oscillator up to a predetermined number and changes its output level when the predetermined number is reached, and a counter that changes the output level of the counter. A displacement conversion device comprising: switching means for switching to either the first frequency or the second frequency according to the frequency; and averaging means for averaging the count output of the counter. 2 A differential type capacitive element whose capacitance changes differentially according to the physical displacement to be detected is connected to the first and second
2. The displacement converting device according to claim 1, wherein the displacement converting device is used as an impedance element. 3. A variable capacitance element whose capacitance changes in accordance with the physical displacement to be detected and a fixed capacitance element whose capacitance changes only in response to physical changes in ambient conditions are used as the first and second impedance elements. The displacement converting device according to claim 1, wherein the displacement converting device is used. 4. Displacement according to claim 1, characterized in that differential resistance elements whose resistance value differentially changes depending on the physical displacement to be detected are used as the first and second impedance elements. conversion device. 5. A variable resistance element whose resistance value changes according to the physical displacement to be detected and a fixed resistance element whose resistance value changes only according to physical changes in the surrounding conditions are used as the first
2. The displacement converting device according to claim 1, which is used as a second impedance element. 6. The displacement conversion device according to claim 1, characterized in that a single relaxation type oscillator is used and a switching path is used to alternately complete the oscillation circuit by the first or second impedance element. 7. The invention is characterized by using first and second relaxation type oscillators each having a first and second impedance element connected to each other, and using a switching circuit that alternately completes an oscillation circuit using the first and second relaxation type oscillators. A displacement converting device according to claim 1. 8. A relaxation type oscillator is used, which includes first and second fixed impedances that together with the first and second impedance elements determine the oscillation frequency, and in which the values of the first and second fixed impedances are different from each other. A displacement converting device according to claim 1. 9. The displacement converting device according to claim 1, characterized in that an integrating circuit is used as the averaging means. 10. The displacement converting device according to claim 1, characterized in that an indicator that indicates the average value of the pulse signal is used as the averaging means.