JPH01282864A - Manufacture of matrix wiring section of image sensor - Google Patents

Manufacture of matrix wiring section of image sensor

Info

Publication number
JPH01282864A
JPH01282864A JP63112023A JP11202388A JPH01282864A JP H01282864 A JPH01282864 A JP H01282864A JP 63112023 A JP63112023 A JP 63112023A JP 11202388 A JP11202388 A JP 11202388A JP H01282864 A JPH01282864 A JP H01282864A
Authority
JP
Japan
Prior art keywords
pattern
wiring
plating
film
output electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63112023A
Other languages
Japanese (ja)
Inventor
Daisuke Kobayashi
大介 小林
Hidetaka Sonohata
秀隆 園畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP63112023A priority Critical patent/JPH01282864A/en
Publication of JPH01282864A publication Critical patent/JPH01282864A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To reduce the wiring resistance of output electrodes and also to make a sensor smaller by film-forming a wiring pattern of output electrodes, and then by plating the wiring pattern electrolytically using the pattern as the negative electrode, and forming a plating film on the pattern. CONSTITUTION:Photoconductive films of CdS-CdSe, etc., are formed on a substrate 1 through evaporation, etc., and they are formed into photodetectors 2 through photoetching, etc. After that, they are heat-treated and given photoelectric transducing characteristics. Then, NiCr-Au, etc., are formed into a pattern on the substrate 1 through lift off, etc., to make common electrodes 3 and individual electrodes 4. Next, intermediate layer insulating films 6 are formed in a specified pattern. Then, NiCr-Au, etc., are formed into a pattern to get output electrodes 7 on them. After that, the output electrodes 7 are electrolytically plated and a film of Au, etc., is formed through the plating. This plating film reduces the wiring resisting of the output electrodes 7 greatly.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は、ファクシミリ装置などの画像読み取り部に
用いられるイメージセンサに関し、特に、センサ基板上
におけるマl−IJフックス線部の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an image sensor used in an image reading section of a facsimile machine, etc., and particularly relates to a method for manufacturing a multi-IJ Fuchs line section on a sensor substrate. .

従来の技術 密着型イメージセンサの代表的な配線レイアウト構造を
第2図に示している(例えば[日経メカニカルJ 19
86年12月1日号71〜78頁を参照)。
A typical wiring layout structure of a conventional technology-based image sensor is shown in Figure 2 (for example, [Nikkei Mechanical J 19
(See December 1, 1986 issue, pages 71-78).

第2図のように、基板1上に多数の受光素子2が直線上
に配列して形成されているとともに、共通電極3および
個別電極4からなる配線パターンが形成されている。こ
の例では6個の受光素子2を1つの群とし、各群ごとに
同じ配線パターンになっている。つまり、受光素子2列
の片側において6個の受光素子2の各一端が1つの共通
電極3に接続され、各受光素子2の他端はそれぞれ個別
電極4に接続されている。共通電極3は基板1の一端側
に配設されたバット部3aにつながっている。また、個
別電極4は6個1組のパターンでマトリックス配線部5
につながっている。
As shown in FIG. 2, a large number of light receiving elements 2 are formed on a substrate 1 in a linear arrangement, and a wiring pattern consisting of a common electrode 3 and individual electrodes 4 is formed. In this example, six light receiving elements 2 are made into one group, and each group has the same wiring pattern. That is, on one side of the two rows of light receiving elements, one end of each of the six light receiving elements 2 is connected to one common electrode 3, and the other end of each light receiving element 2 is connected to an individual electrode 4, respectively. The common electrode 3 is connected to a butt portion 3a provided at one end of the substrate 1. In addition, the individual electrodes 4 are arranged in a matrix wiring part 5 in a pattern of 6 pieces.
connected to.

このマトリックス配線部5が本発明の対象となる部分で
ある。マトリックス配線部5における個別電極4が下層
配線パターンであり、これの上に中間層の絶縁膜6のパ
ターンが形成され、さらにその上に上層配線パターンで
ある6本の平行な出力電極7が形成されている。出力電
極7は、中間層絶縁膜6のないコンタクト部8において
、下層の個別電極4と接続されている。
This matrix wiring section 5 is the part targeted by the present invention. The individual electrodes 4 in the matrix wiring section 5 are the lower layer wiring pattern, on which the pattern of the intermediate layer insulating film 6 is formed, and further on this, the six parallel output electrodes 7 which are the upper layer wiring pattern are formed. has been done. The output electrode 7 is connected to the lower layer individual electrode 4 at the contact portion 8 where the intermediate layer insulating film 6 is not provided.

発明が解決しようとする課題 ファクシミリ装置の密着型イメージセンサなどの場合、
受光素子2の配列数が非常に多く、センサ基板1は長尺
になる。前記出力電極7の配線パターンは基板1の全長
にわたって形成されるので、長尺ものでは配線長が非常
に長くなる。また機器の小型化の要求からセンサ基板1
の幅はできるだけ小さく設計されるので、出力電極7の
各線幅および線間ピッチも小さくしなければならない。
Problems to be solved by the invention In the case of contact type image sensors for facsimile machines, etc.
The number of arrays of light receiving elements 2 is very large, and the sensor substrate 1 becomes long. Since the wiring pattern of the output electrode 7 is formed over the entire length of the substrate 1, the wiring length becomes very long if it is long. In addition, due to the demand for miniaturization of equipment, the sensor board 1
Since the width of the output electrode 7 is designed to be as small as possible, the width of each line and the pitch between the lines of the output electrode 7 must also be made small.

通常、マトリックス配線部5の配線パターンは蒸着、リ
フトオフ法などによる薄膜技術を用いて作っている。薄
膜技術では電極膜厚をあまり大きくすることができない
ので、長尺もののイメージセンサにおいては、出力電極
7は薄くて細くてしかも長くなる。こうなると比抵抗の
小さい金属材料を用いても、出力電極7の配線抵抗が増
大する。
Usually, the wiring pattern of the matrix wiring section 5 is made using thin film technology such as vapor deposition or lift-off method. With thin film technology, the electrode film thickness cannot be made very large, so in a long image sensor, the output electrode 7 is thin and long. In this case, even if a metal material with a low specific resistance is used, the wiring resistance of the output electrode 7 increases.

イメージセンサのように微小電流のわずかな変化を情報
として利用するものでは、出力電極7の配線抵抗の存在
はセンサ性能上に大きな悪影響を与える。
In a device such as an image sensor that uses a slight change in a minute current as information, the presence of wiring resistance of the output electrode 7 has a large adverse effect on sensor performance.

この発明は上述した従来の問題点に鑑みなされたもので
、その目的は、簡単な方法で出力電極の導電性を向上さ
せ、出力電極が長くなっても配線抵抗を小さく抑えるこ
とができるようにすることにある。
This invention was made in view of the above-mentioned conventional problems, and its purpose is to improve the conductivity of the output electrode by a simple method and to suppress wiring resistance even if the output electrode becomes long. It's about doing.

課題を解決するだめの手段 そこでこの発明では、マトリックス配線部における出力
電極の配線パターンをリフトオフ法等により薄膜形成し
た後、その配線パターンを負極として電解メッキを行な
ってこれに所定の導電材料からなるメッキ膜を形成する
ようにした。
Means to Solve the Problem Therefore, in the present invention, the wiring pattern of the output electrode in the matrix wiring part is formed into a thin film by a lift-off method or the like, and then electrolytic plating is performed using the wiring pattern as a negative electrode to form a thin film made of a predetermined conductive material. A plating film was formed.

作用 リフトオフ法等の薄膜技術によれば、前記出力電極の微
細な配線パターンを簡単かつ高精度に形成することがで
きる。しかし前述のように膜厚をあまり大きくすること
ができない。この配線パターンに電解メッキを施すこと
で、出力電極の導電性が前記メッキ膜によって向上する
こととなり、配線抵抗が小さくなる。
According to a thin film technique such as a functional lift-off method, a fine wiring pattern of the output electrode can be formed easily and with high precision. However, as mentioned above, the film thickness cannot be made very large. By applying electrolytic plating to this wiring pattern, the conductivity of the output electrode is improved by the plating film, and the wiring resistance is reduced.

実施例 第1図は本発明の一実施例における製造途中の配線レイ
アウト構造を示している。まず、基板1上にCd5−C
dSe等の光導電膜を蒸着等で形成し、それをフォトエ
ツチング等により受光素子2の形にする。そのあとCd
C−e2等の蒸気中で450C〜600Cに加熱処理す
ることで光電的に活性化し、光電変換特性を付与する。
Embodiment FIG. 1 shows a wiring layout structure in the process of being manufactured in an embodiment of the present invention. First, Cd5-C on the substrate 1.
A photoconductive film such as dSe is formed by vapor deposition or the like, and then formed into the shape of the light receiving element 2 by photoetching or the like. Then Cd
It is photoelectrically activated by heat treatment at 450C to 600C in vapor such as C-e2 and imparts photoelectric conversion characteristics.

次に、NtCr  Au等をリフトオフ等により基板1
上にパターン形成し、共通電極3および個別電極4を作
る。次に、マトリックス配線部5を構成する部分の個別
電極4上に、ポリイミド樹脂等からなる中間層絶縁膜6
を所定パターンで被覆形成する。次に、これらの上にN
iCr−Au等をリフトオフ等によりパターン形成し、
出力電極7を得る。この出力電極7は絶縁膜6のないコ
ンタクト部8において個別電極4と接続され、マトリッ
クス配線部5が構成される。
Next, NtCr Au etc. is removed from the substrate 1 by lift-off etc.
A pattern is formed on the top to form a common electrode 3 and individual electrodes 4. Next, an intermediate insulating film 6 made of polyimide resin or the like is placed on the individual electrodes 4 that constitute the matrix wiring section 5.
is coated in a predetermined pattern. Then on top of these
Patterning iCr-Au etc. by lift-off etc.
An output electrode 7 is obtained. This output electrode 7 is connected to the individual electrode 4 at a contact portion 8 without an insulating film 6, thereby forming a matrix wiring portion 5.

出力電極7の一端は基板1上の所定位置に配設したパッ
ド部7aにつながっていると共に、図中でドツトを付け
て示したメッキ用リード部7bに共通接続されており、
このリード部7bには1つの大きなパッド部7cがつな
がっている。これらは出力電極7と同時にパターン形成
されたもので、出力電極7およびメッキ用リード部7b
等の厚みは数百A程度あれば充分である。なお、ドツト
を付けて図示したメッキ用リード部7bおよびパッド部
7cはセンサ基板1の有効部分の外側に配設してあり、
最後の基板カットの際にこの部分を基板lとともに切削
する。
One end of the output electrode 7 is connected to a pad portion 7a arranged at a predetermined position on the substrate 1, and is also commonly connected to a plating lead portion 7b shown with a dot in the figure.
One large pad portion 7c is connected to this lead portion 7b. These are patterned at the same time as the output electrode 7 and the plating lead part 7b.
A thickness of several hundred amps is sufficient. Note that the plating lead portion 7b and pad portion 7c, which are shown with dots, are arranged outside the effective portion of the sensor board 1.
This portion is cut together with the substrate 1 during the final substrate cutting.

次に、出力電極7に電解メッキを施してAu等のメッキ
膜を数千A〜数μm形成する。このメッキ膜によって出
力電極7の配線抵抗は大幅に低減する。メッキ用リード
部7bおよびパッド部7cはメノキ工程での配線作業の
便のために設けたもので、これは前述のように後で切削
する。
Next, the output electrode 7 is electrolytically plated to form a plating film of Au or the like with a thickness of several thousand amps to several μm. This plating film significantly reduces the wiring resistance of the output electrode 7. The plating lead portion 7b and the pad portion 7c are provided to facilitate wiring work in the agate wood process, and will be cut later as described above.

発明の効果 以上の説明から明らかなように、本発明によれば、セン
サ基板面積を小さくするだめの薄膜形成による細くて薄
い出力電極の配線パターンでも、そのあと電解メッキを
施すことにより配線抵抗を十分小さくすることができ、
なおかつ電解メッキという簡単な工程であるため品質を
損うことがない。したがってセンサを小型化することと
、配線抵抗を小さくすることが両立し、信頼性の高いイ
メージセンサを歩留り良く量産することができる。
Effects of the Invention As is clear from the above explanation, according to the present invention, even if the wiring pattern of the output electrode is thin and thin by forming a thin film to reduce the area of the sensor substrate, the wiring resistance can be reduced by applying electrolytic plating afterwards. can be made small enough,
Moreover, since it is a simple process of electrolytic plating, there is no loss of quality. Therefore, it is possible to reduce the size of the sensor and reduce the wiring resistance, and it is possible to mass-produce highly reliable image sensors with a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による製造過程の配線レイア
ウト構成を示す平面図、第2図はイメージセンサの代表
的な配線レイアウト構成を示す斜視図である。 1・・・基板、2・・・受光素子、3・・・共通電極、
4・・・個別電極、5・・・マトリクス配線部、6・・
・絶縁膜、7・・・出力電極、8・・コンタクト部、7
b・・・メッキ用リード部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 a \
FIG. 1 is a plan view showing a wiring layout configuration in a manufacturing process according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a typical wiring layout configuration of an image sensor. 1... Substrate, 2... Light receiving element, 3... Common electrode,
4... Individual electrode, 5... Matrix wiring section, 6...
・Insulating film, 7... Output electrode, 8... Contact part, 7
b...Lead part for plating. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure a \

Claims (1)

【特許請求の範囲】[Claims]  イメージセンサのマトリックス配線部における出力電
極配線パターンをリフトオフ法等により薄膜形成した後
、前記配線パターンを負極として電解メッキを行なって
前記配線パターンに所定の導電材料からなるメッキ膜を
形成することを特徴とするイメージセンサのマトリック
ス配線部の製造方法。
The output electrode wiring pattern in the matrix wiring part of the image sensor is formed into a thin film by a lift-off method or the like, and then electrolytic plating is performed using the wiring pattern as a negative electrode to form a plated film made of a predetermined conductive material on the wiring pattern. A method for manufacturing a matrix wiring part of an image sensor.
JP63112023A 1988-05-09 1988-05-09 Manufacture of matrix wiring section of image sensor Pending JPH01282864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63112023A JPH01282864A (en) 1988-05-09 1988-05-09 Manufacture of matrix wiring section of image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63112023A JPH01282864A (en) 1988-05-09 1988-05-09 Manufacture of matrix wiring section of image sensor

Publications (1)

Publication Number Publication Date
JPH01282864A true JPH01282864A (en) 1989-11-14

Family

ID=14576056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63112023A Pending JPH01282864A (en) 1988-05-09 1988-05-09 Manufacture of matrix wiring section of image sensor

Country Status (1)

Country Link
JP (1) JPH01282864A (en)

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