JPH01281733A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control the thickness and impurity concentration in the groove side surface of an impurity-introduced region by selectively forming the impurity- introduced region using a first mask formed on a semiconductor substrate, forming a second mask for etching on the side surface of the first mask, and forming a recess groove in the impurity-introduced region using the first and second masks. CONSTITUTION:A first mask 22c for introduction of any impurity is formed on a semiconductor substrate 21, by which mask 22c an impurity is introduced into the semiconductor substrate 21 to form an impurity-introduced region 25. Thereafter, a second mask 22d for etching is formed on the side surface of the first mask 22c. A recess groove 24b is formed in the impurity-introduced region by the first and second masks 22c, 22d. Accordingly, the thickness of a fraction of the side surface of the groove 24a in the impurity-introduced region 25a (the thickness of the second mask) can be made greater than in the conventional technique, making it difficult to etch the vicinity of the surface of the groove 24a in the impurity-introduced region 25a. Thus, the thickness and concentration of the fraction of the groove side surface of the impurity- introduced region can further be controlled.

Description

[Detailed Description of the Invention] [Summary] Provided is a method for manufacturing a semiconductor device that can improve the controllability of the thickness and the concentration of the groove side surface portion of the impurity-introduced region. a step of forming a first mask for impurity introduction on a semiconductor substrate, and using the first mask to introduce an impurity into the semiconductor substrate to selectively form an impurity introduction region. a step of forming a second mask for etching on the side surface of the first mask;
forming a concave groove in the impurity introduction region using the first mask and the second mask.

(Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, and more particularly, it is possible to control an impurity-introduced region (a region formed by ion implantation) on a concave groove side surface (also called a groove side wall). The present invention relates to a method for manufacturing a semiconductor device that can be easily formed.

In recent years, with the progress of miniaturization of semiconductor devices, in addition to the conventional planar technology, trenching technology has also become popular, and for example, trench isolation and trench capacitor structures are being adopted. Therefore, the impurity concentration of not only the bottom surface of the trench but also the impurity introduced region formed on the side surface of the trench must be well controlled.

[Conventional technology]

FIGS. 5A to 5C are diagrams for explaining an example of a conventional method for manufacturing a semiconductor device. The illustrated manufacturing method is applied to trench isolation.

In these figures, 1 is a substrate made of Si, for example, and has a p-type conductivity, and 2 is a resist, which functions as a mask for etching and ion implantation. Reference numeral 3 indicates a concave groove, and reference numeral 4 indicates an impurity introduction region, which is formed by ion implantation and has the function of cutting a channel. 5 is a gate, 6 is a source, 7 is a drain, 8 is an electrode,
9 is a cover film made of, for example, Sin, and 10 is a gate oxide film.

Next, the manufacturing process will be explained.

First, as shown in FIG. 5(a), a resist is applied onto a substrate 1, and then the resist is patterned to form a resist 2 for etching and ion implantation. Next, by anisotropic etching using the resist 2 as a mask, the base F
i1 is selectively etched to a depth of, for example, 1 to 2 μm.
groove 3 is formed.

Next, as shown in FIG. 5(b), using the resist 2 as a mask, ions of, for example, B' are implanted from an oblique direction (arrows A and B) to form an impurity-introduced region 4 on the side surface of the trench 3.

Then, for example, n-channel MO3F, which is normally carried out,
Through the ET process, a semiconductor device as shown in FIG. 5(C) is completed.

In the conventional semiconductor device manufacturing method described above, there is a problem in that when the depth of the trench 3 becomes larger than the width, it becomes difficult to implant ions into the side surfaces of the trench 3, and a region where ions are not implanted tends to occur. Ta.

In particular, if the angle with respect to the side surface of the groove 3 becomes small, ions will be reflected by the surface and will not be implanted into the side surface of the groove 3.

As a conventional means to solve the above problem, there is
It is described in No. 288462.

Hereinafter, this will be explained in detail with reference to the drawings.

FIGS. 6(a) and 6(b) are diagrams for explaining another example of the conventional method for manufacturing a semiconductor device.

In these figures, the same reference numerals as in FIGS. 5(a) to (c) indicate the same or corresponding parts, 13 is a concave groove, 14a
, 14b are impurity introduced regions, and the impurity introduced regions 14b are the portions left after the impurity introduced regions 14a are etched (at this time, the grooves 13 are formed).

Next, the manufacturing process will be briefly explained.

First, as shown in FIG. 6(a), a resist is applied onto a substrate 1, and then the resist is patterned to form a resist 2 for etching and ion implantation. Next, using the resist 2 as a mask, ions are implanted to selectively form impurity introduced regions 14a in the substrate 1. At this time, the reason why the width of the impurity-introduced region 14a becomes wider than the width X of the resist 2 (mask width) is due to secondary diffusion in the lateral direction during ion implantation. Since the deeper the implantation is in the depth direction of the substrate 1, the diffusion in the lateral direction tends to become larger, so if the depth of the impurity introduction region 14a is increased, the width of the impurity introduction region 14a can be increased. can.

Next, as shown in FIG. 6(b), the groove 13 is formed by selectively etching the impurity introduced region 14a by anisotropic etching using the resist 2 as a mask. At this time, an impurity introduced region 14b is formed on the side surface of the groove 13.

Then, for example, n-channel MO3F, which is normally carried out,
A semiconductor device having a structure as shown in FIG. 5(C) can be obtained by the ET process.

[Problem to be solved by the invention]

However, such conventional figures 6(a) and (b)
In the method for manufacturing a semiconductor device shown in FIG. 6, the thickness of the side surface of the groove 13 of the impurity-introduced region 14b is controlled using the phenomenon of lateral diffusion, as shown in FIG. 6(b). the width of the impurity introduced region 14b near the surface of the groove 13;
The width of the impurity introduced region 14b near the bottom of the trench 13 is significantly different (the width of the impurity introduced region 14b near the surface of the trench 13 is small, and the width of the impurity introduced region 14b near the bottom of the trench 13 is large). Due to the lateral spread during etching (even in vertical anisotropic etching, there is some lateral etching), the entire portion near the surface of the impurity introduced region 14b is likely to be etched, especially the groove 13 of the impurity introduced region 14b. There was a problem in that it was difficult to control the side parts. In addition, the portion of the side surface of the groove 13 of the impurity-introduced region 14b has 2
There was also the problem that it was difficult to appropriately control the concentration because of the following properties.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the controllability of the thickness and the concentration of the groove side surface portion of the impurity-introduced region.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first mask for introducing impurities on a semiconductor substrate, and introducing an impurity into the semiconductor substrate using the first mask. a step of forming a second mask for etching on the side surface of the first mask; The method includes a step of forming a concave groove within the introduction region.

[For production]

In the present invention, a first mask for impurity introduction is formed on a semiconductor substrate, and after the impurity is introduced into the semiconductor substrate by the first mask to form an impurity introduction region, a side surface of the first mask is formed. A second mask for etching is formed, and a concave groove is formed in the impurity introduced region using the first mask and the second mask.

Therefore, the thickness of the groove side surface portion of the impurity doped region (the thickness of the second mask) can be made larger than in the conventional method, and the vicinity of the groove surface of the impurity doped region is less likely to be etched.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(e) are diagrams for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention. The manufacturing method in the illustrated example is applied to trench isolation. .

In these figures, 21 is a substrate made of, for example, Si, whose conductivity type is, for example, p-type (corresponding to the semiconductor substrate according to the present invention), and whose resistivity is, for example, 100. 22a, 2
2b is an insulating film made of, for example, SiO□, and 22c is a first mask (corresponding to the first mask according to the present invention), which is the portion remaining after the insulating film 22a has been etched. 22
d is a second mask (corresponding to the second mask according to the present invention), which is a portion remaining after the insulating film 22b has been etched. 23 is a resist, 24a and 24b are concave grooves (the concave groove 24b corresponds to the concave groove according to the present invention), 2
5.25a is an impurity introduced region, impurity introduced region 25a
is the portion remaining after the impurity introduction region 25 has been etched, and has the function of cutting a channel.

Note that the groove 24a is formed by selectively etching the insulating film 22a, and the groove 24b is formed by selectively etching the impurity introduced region 25.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), SiO□ is deposited on a substrate 21 by, for example, the CVD method, and the film thickness is, for example, 1.0 μm.
After forming an insulating film 22a of m and applying a resist, the resist is patterned to form a resist 23 for an etching mask.

Next, as shown in FIG. 1B, using the resist 23 as a mask, the insulating film 22a is selectively etched by RIE using, for example, CH, F, or gas to form a first mask 22c for introducing impurities. form.

At this time, a groove 24a having a width of, for example, 1.5 μm is also formed at the same time. This corresponds to the step of forming a first mask for impurity introduction on a semiconductor substrate according to the present invention. Then,
Using the first mask 22c, ions are implanted into the substrate 21 to selectively form an impurity-introduced region 25 having a depth of, for example, 1.9 μm. This corresponds to the step of introducing impurities into the semiconductor substrate using the first mask to form an impurity-introduced region.

Next, as shown in FIG. 1C, after the resist 23 is removed, an insulating film 22b having a thickness of, for example, 4000 is formed by depositing Sin on the entire surface along the inside of the groove 24a by, for example, the CVD method. After forming, the impurity introduced region 25 is activated by heat treatment in a 900 inch C1N2 gas atmosphere, for example.

Next, as shown in FIG. 1(d), for example, CH.

The insulating film 22b is selectively removed by anisotropic full-surface etching using F2 gas (for example, a film thickness of 4000 is removed), and a second mask 22d for etching is formed on the side surface of the groove 24a of the first mask 22c. form.

This corresponds to the step of forming the second mask for etching on the side surface of the first mask according to the present invention.

Next, as shown in FIG. 1(e), the first mask 22C
Then, using the second mask 22d, the impurity introduced region 25 in the substrate 21 is selectively etched by, for example, the RIE method to form a concave groove 24b having a depth of, for example, 1.5 μm. This corresponds to the step of forming a concave groove in the impurity-introduced region using the first mask and the second mask according to the present invention. The conditions for RIE include that the etching gas is, for example, CBrF3 gas, and the pressure is, for example, Q, 37' or
r, the energy is, for example, 100W.

After removing the first mask 22c and the second mask 22d and filling the groove 24b with an insulating material, a conventional MOS FET process is carried out as shown in FIG. 5(c).
A semiconductor device having a structure as shown in can be obtained.

That is, in the above embodiment, as shown in FIG. 1(b), after the impurity implantation region 25 is formed using the first mask 22c for impurity implantation, as shown in FIG. A second mask 22d formed on the side surface of the mask 22c.
Since the concave groove 24b is formed using the first mask 22c, the thickness of the side surface of the groove 24b of the impurity-introduced region 25a is made thicker by the thickness of the second mask 22d than in the conventional method. The portion of the introduction region 25a near the surface of the groove 24b is difficult to be etched (this makes it difficult to etch the portion of the introduction region 25a).
The thickness and concentration of the side surface portions of the grooves 24b of a can be controlled as appropriate.

Next, FIGS. 2(a) to 2(f) are diagrams for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention.

In these figures, the same symbols as in FIGS. 1(a) to (e) indicate the same or corresponding parts, and 22e is, for example, SiO□
The insulating film 30 is a semiconductor layer made of poly-Si, for example.

Note that here, the second mask 22d is composed of an insulating film 22e and a semiconductor layer 30.

Next, the manufacturing process will be explained.

First, as shown in FIG. 2(a), Sin is deposited on the substrate 21 by, for example, the CVD method, and the film thickness is, for example, 1.5.
After forming the μm insulating film 22a and applying resist,
The resist is patterned to form a resist 23 for an etching mask.

Next, as shown in FIG. 2(b), the insulating film 22a is selectively etched by, for example, RIE using the resist 23 as a mask to form a first mask 22c for introducing impurities. At this time, the groove 24a is also formed at the same time. Next, using the first mask 22c, ions are implanted into the first substrate 21 to selectively form impurity doped regions 25.

Next, as shown in FIG. 2(C), after removing the resist 23, the grooves 24a are treated with HCI at 900° C. for 20 minutes, for example.
The inner substrate 21 is oxidized to form an insulating film 22e having a thickness of, for example, 100 layers on the surface of the substrate 21. The heat treatment at this time activates the impurity introduced region 25.

Next, as shown in FIG. 2(d), poly-Si is deposited over the entire surface by, for example, the CVD method to form a semiconductor layer 30 having a thickness of, for example, 4,000 layers.

Next, as shown in FIG. 2(e), the semiconductor layer 30 and the insulating film 22e are selectively removed by anisotropic etching to form a second etching mask 22d on the side surface of the trench 24a. At this time, the first mask 22C and the substrate 21 within the groove 24a are exposed. Semiconductor layer 3° and insulating film 22e
Specifically, first, for example, CB r
After the semiconductor layer 30 is etched to a thickness of 4,000 layers by RIE using F 3 gas, the insulating film 22e is etched to a thickness of 100 layers by RIE using, for example, CH, F, and gas.

Next, as shown in FIG. 2(f), a second mask 22d is applied.
Then, using the first mask 22c, the impurity introduced region 25 in the substrate 21 is selectively etched by, for example, RIE, to form a groove 24b. Specifically, the second mask 2
When the etching ends when the semiconductor layer 30 of 2d is etched off, a groove 24b having a depth of, for example, 1.5 μm can be formed.

That is, in this embodiment, in addition to the effects of the first embodiment, the depth of the groove 24b can be controlled almost accurately. The depth of the groove 24b can be controlled almost accurately because it can be appropriately controlled based on the relationship between the etching rate of the etched portion of the impurity introduction region 25a and the etching rate of the semiconductor layer 30 of the second mask 22d. .

In each of the above embodiments, the impurity introduction region 25 is formed by introducing impurities with the same acceleration energy (the impurity concentration tends to differ in the depth direction from the surface), but the present invention However, the invention is not limited to this (it is also possible to form an impurity-introduced region by introducing impurities by changing the accelerating voltage. In this case, in addition to the effects of each of the above embodiments, It is possible to make the impurity concentration almost uniform in the horizontal direction. Specifically, for example, if the impurity is introduced by changing the acceleration voltage as shown in FIGS. 3 and 4, the impurity concentration can be made approximately 5XIO". c.
1", it is possible to form a uniform impurity-introduced region. Note that FIGS. 3 and 4 show examples in which impurity introduction is carried out in 11 steps.

〔effect〕

According to the present invention, it is possible to improve the controllability of the thickness and the concentration of the groove side surface portion of the impurity-introduced region.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, FIGS. 2 to 4 are diagrams for explaining other embodiments of the method for manufacturing a semiconductor device according to the present invention, and FIG. 6 is a diagram explaining the manufacturing process of one example of the conventional example, and FIG. 6 is a diagram explaining the manufacturing process of another example of the conventional example. 21...Substrate, 22a, 22b, 22e-...Insulating film, 22c...
...First mask, 22d...Second mask, 23...Resist, 24a, 24b --Groove, 25.25a...Impurity Introduction area, 30...
...Semiconductor layer. , ・'' 4th grade guest 1ka J410 ~ 1st grade mt theory day 7th 2nd
Figure 5 ~ Yarisu Hachi Q-46°

Claims (1)

[Scope of Claims] A step of forming a first mask for impurity introduction on a semiconductor substrate, and selectively forming an impurity introduction region by introducing an impurity into the semiconductor substrate using the first mask. forming a second mask for etching on a side surface of the first mask; forming a concave groove in the impurity introduction region using the first mask and the second mask; A method for manufacturing a semiconductor device, comprising the steps of: