JPH01276978A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain stable reproduced pictures by providing a switching means which switches the output signal of a latch circuit which uses pulses synchronous to both edges of head switching signals as latch pulses and outputs as head amplifier switching signals. CONSTITUTION:The position of the 5th switching circuit 148 is connected to the output of the 1st latch circuit 147 and whether or not the edge arriving times HSW counting data H of detected switching signals are '2' is discriminated by controlling two input terminals 27-1 and 27-2. When the data are '2', an input terminal 28 is controlled and the 4th switching circuit 145 is connected to the forward signal side of head switching signals. When they do not coincide with each other, the circuit 145 is connected to the backward signal (the output of an inverter circuit 144) side. Therefore, the output of the 1st latch circuit 146 and the output of the 5th switch 148, namely, the head amplifier switching signals become those which have no jitter caused by a delay in processing peculiar to the software and are synchronized to the head switching signals.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a magnetic recording and reproducing device having a slow motion reproducing function, and in particular provides a device that can be easily realized at low cost using a microprocessor.

BACKGROUND OF THE INVENTION In recent years, microprocessors have become widespread and are now being used in many household electrical appliances. Home video tape recorder (hereinafter abbreviated as VTR).

) is no exception, and the core of the loading mechanism is to pull the magnetic tape out of the cassette and wrap it around a rotating head.

Microprocessors are actively being used at the center of systems such as timers and program reservation systems. However, precision rotation control devices for the cylinder motor that drives the rotating head and the capstan motor that runs the magnetic tape at a constant speed require complex judgment operations and rapid processing of detection signals, so microprocessors are not required. It has relied on specialized hardware.

In addition, recent VTRs generally allow you to select between standard recording mode and long-time recording mode by switching the tape speed, and in each recording mode, you can stop the tape during playback and still images and intermittent Some devices are constructed so that slow-motion reproduced images can be obtained by moving the tape. The conventional technology will be explained below with reference to all the drawings.

FIG. 13 is a block diagram showing the configuration of a servo system during playback of a conventional VTR, in which rotating magnetic heads 81 and 82 are close to each other, rotating magnetic heads 91 and 92 are close to each other, and each is approximately A cylinder motor that is arranged at a position 1800 and drives four rotating magnetic heads 81.82 and 91.92, in which rotating magnetic heads 81 and 91 have the same azimuth angle, and rotating magnetic heads 82 and 92 have the same azimuth angle. 2, a first frequency generator 3 that detects the rotational speed of the cylinder motor 2, a phase detector 4 that detects the entire rotational phase of the cylinder motor 2, and an output signal of the first frequency generator 3. A first frequency discriminator 4o that produces an error with respect to the reference period, a reference signal generator 42, a rotational phase signal (also a head switching signal) obtained from the phase detector 4, and a reference signal generator 42. A first phase comparator 41 detects a phase error with respect to the obtained reproduction reference signal, and mixes the phase error output of the first phase comparator 41 and the speed error output of the first frequency discriminator 4o. A first adder 43, a first amplifier 44, a first drive circuit 12 for driving the cylinder motor 2, a capstan motor 6 for running the magnetic tape at a constant speed, and a rotation speed of the capstan motor 60. A second frequency generator 7 to detect, a control head 6 to detect a control signal recorded on the lower end of the magnetic tape 1, and an error in the output signal of the second frequency generator 7 with respect to a reference period is detected. a second frequency discriminator 46 and a variable resistor 6o triggered by the output signal of the reference signal generator 42;
a tracking mono multi-circuit 46 whose delay time is variable, and a second phase comparator 4 that detects a phase error t between the control signal obtained from the control head 6 and the output signal of the tracking mono multi-circuit 46.
7, a second adder 48 for mixing the phase error output of the second phase comparator 470 and the speed error output of the second frequency discriminator 46, a second amplifier 49, and a capstan motor 6. "f: A second drive circuit 13 to drive, and a forced acceleration command signal and motor ON10 using the rotational phase signal and control signal as reference signals in order to intermittently drive the capstan motor during slow motion playback.
An intermittent running control circuit 61 that outputs an F F signal, a current direction switching signal, a head amplifier switching signal, etc.;
a third adder 63 for mixing the output of the amplifier 48 with the forced acceleration command signal of the intermittent running control circuit 61; and the four rotating magnetic heads 81, 82, 91.

It is constituted by a head amplifier circuit 11 that amplifies each reproduced video signal obtained from e2 and outputs an envelope comparison signal, which will be explained later.

Regarding the VTR configured as described above, the operation during normal playback will be briefly explained using the configuration diagram shown in FIG. 13 and the timing chart of the main parts shown in FIG. 14.

The 14th factor R is the output waveform of the reference signal generator 42 in FIG. 13, and this signal is used as the reference signal during VTR playback.
The signal is supplied to the first phase comparator 41 and the tracking monomulti circuit 46.

The trapezoidal wave signal in FIG. 14S is the internal waveform of the first phase comparator 41, and is the phase reference signal of the cylinder motor triggered by the rising edge of the
The rotary phase signal obtained from the phase detector 4 in FIG. 3, that is, the falling edge in the 14th drawing, is sampled and the hold signal (not shown) obtained from the rotational phase signal obtained from the first frequency discriminator 40 in FIG. A first adder 43 mixes the speed error signal with the speed error signal, and the mixed signal is supplied to the first drive circuit 12 via a first amplifier 44. Therefore, the cylinder motor, that is, the rotary head 8 rotates in phase synchronization with the reference signal of the fourteenth factor R. Figure 14 shows the charging/discharging waveform of the capacitor (not shown) in the tracking monomulti circuit 46 in Figure 13, which is triggered by the rising edge of the 14th factor R, and is triggered by the variable resistor 5o in Figure 13. By changing the time constant, the delay time can be varied. Fig. 14 U indicates tracking monomer f times WIr4
6, and the trapezoidal wave signal in FIG.
The internal waveform of the second phase comparator 47 shown in FIG.
The phase reference signal of the capstan motor triggered by the falling edge of the reproducing control signal obtained from the control head 5 in FIG.
The hold signal (not shown) sampled by the rising edge of W in FIG. 4 is mixed with the speed error signal obtained from the second frequency discriminator 46 in FIG. The signal is supplied to the second drive circuit 13 via an amplifier 49 . At this time, the forced acceleration command signal of the intermittent running control circuit 51 has a high impedance. Therefore, the capstan motor 6 rotates in phase synchronization with the output signal of the tracking monomulti circuit 46 shown in FIG. As described above, during normal playback of the VTR, the rotary head 8
By synchronizing the phase of the playback control signal (W in FIG. 14) with the rotational head 8, the rotary head 8 tracks the track recorded on the magnetic tape 1 at ti.

Next, the operation during slow motion reproduction will be explained with reference to the timing chart shown in FIG. In order to improve transient characteristics during slow motion playback, the second
The phase error output of the phase comparator 470 is electrically grounded,
The capstan motor 6 is rotated by being provided with only a speed control system. Figure 16! , Y is the forced acceleration command signal synchronized with the rotation phase signal of the cylinder motor in the 16th diagram and the motor 0N1.
0FF signal, and Fig. 16 2 shows the capstan motor 6.
This is the current direction switching signal of the slow tracking monomulti circuit (located inside the intermittent travel control circuit 61, and the delay time can be set by the variable resistor 52) triggered by the control signal of FIG. 16W. (Fig. 16 α), and is reset after a certain period of time. Due to the above three signals (X, Y, Z in FIG. 16), a motor current flows to the capstan motor 6 as shown in FIG. 16 Stop → Acceleration → Constant speed → Deceleration →
It transitions to a stopped state and is driven intermittently.

The four rotating magnetic heads 81, 82, 91, and 92 are constantly rotating, and when the magnetic tape 1 is stopped, still playback is performed, and when the magnetic tape is transferred, normal playback is performed.
By skillfully switching between the four rotating magnetic heads, noiseless slow-motion reproduced images can be obtained.

The 16th factor R shows a state in which the recording track pattern is repeatedly arranged, and one scale on the horizontal axis shows the time of one field, and also shows the timing of the head switching signal. The vertical axis represents the amount of movement of the magnetic tape, and each scale represents the amount of track pitch that the magnetic tape travels during one field time during recording or normal reproduction.

Note that since azimuth recording is used, each track cannot be reproduced by heads with different azimuth angles.

When a still image is reproduced, magnetic heads 81 and 91 having the same azimuth angle are used to obtain a field still image in which one field of video signal is repeatedly reproduced.

Next, after reproducing the same recording trajectory multiple times,
As described above, the magnetic tape is intermittently run one frame on two tracks until the next recording trajectory of the same azimuth is reached, and the same azimuth recording trajectory is repeatedly reproduced. 1st
The dashed-dotted lines in 6■a are the loci of the lower ends of the four rotating magnetic heads, and the solid lines are the trajectories of the two rotating magnetic heads 81.9
2, the dashed line indicates the two rotating magnetic heads 82.9
represents the locus of the upper end of 1. That is, during the three-field period when the tape is running, the rotating magnetic heads 81 and 92° 81 are sequentially used.

FIG. 17 shows the internal configuration of the head amplifier circuit 11, which includes four head amplifiers 111, 112, 113, and 114 corresponding to the four input head outputs, and the head amplifiers 111 and 112 that are input. a first switch 116 into which the head amplifiers 113 and 114 are input, and a third switch into which the output of the first switch 116 and the output of the second switch 116 are input. It is composed of a switch 117 and a level comparator 118, and the first switch 116 and the second
The switch 116 is controlled by the head switching signal input from the input terminal 121, and the third switch 117 is controlled by the head amplifier switching signal input from the input terminal 122. The outputs of two pairs of heads in contact with the magnetic tape 1 are input. The level comparator 118 then outputs the result of determining the magnitude of the two head output levels to the output terminal 119 as an envelope comparison signal. In other words, 1. When the output level of the head amplifier switching signal is high level (hereinafter referred to as H level), the rotating magnetic head 8
When the output level of the head amplifier switching signal is low level (hereinafter referred to as L level), the output of the rotating magnetic head 81 or 92 is transferred to the output terminal 12.
Output to 0.

Therefore, in order to obtain the above-mentioned slow motion playback image, the head amplifier switching signal input to the head amplifier circuit 11 becomes a signal as shown in FIG. switch 11
6 is the output signal of the second switch 116, and d in the same figure is the output signal of the third switch 117.

As described above, by effectively switching between the four rotating magnetic heads, a good slow-motion reproduced image can be obtained.

Problems to be Solved by the Invention However, in the conventional example described above, the magnetic tape is intermittently fed one frame in two tracks in the forward direction in the standard recording mode, and is not used in the case of the long-time recording mode or the slow speed in the reverse direction. In the case of motion playback or slow motion playback in which one field is advanced per track, the rotating magnetic heads used and their switching timings differ. For example, in the case of slow motion playback in the reverse direction, it is necessary to switch heads in synchronization with the envelope comparison signal during intermittent running.

In addition, in order to reduce noise generated when the rotating magnetic head crosses a recording track during double-speed playback, the head amplifier switching signal is added to the envelope comparison signal in order to embed it with the output of an adjacent rotating magnetic head having a different azimuth angle. The signals must be synchronized.

Therefore, in the case of a multi-function VTR, there is a problem in that the circuit configuration becomes extremely complicated when creating a head amplifier switching signal.

Means for Solving the Problems In order to solve the above problems, the present invention provides a magnetic recording and reproducing device that performs slow motion reproduction by repeatedly stopping and moving a magnetic tape transferred by a gear bus stun motor. , the first and third are close to each other, and the second and fourth
are adjacent to each other and also each located at approximately 1800 degrees, the first and second having the same azimuth angle, and the third and fourth having the same azimuth angle.
four rotating magnetic heads having the same azimuth angle;
A cylinder motor drives the four rotating magnetic heads, and a head switching signal indicating the rotational phase of the cylinder motor controls the playback signals from the two rotating magnetic heads that are in contact with the inner magnetic tape of each of the rotating magnetic heads. a first switch means for extracting; a second switch means for selecting two reproduction signals from the first switch means according to a head amplifier switching signal; and an envelope of the two reproduction signals from the first switch means. and an event for counting the number of times an edge of the head switching signal arrives in synchronization with the activation timing of the capstan motor during slow motion playback, and outputting a signal corresponding to a desired count value. a counting means; a third switching means for switching between the head switching signal and its inverted signal according to the first output of the event counting means; the output of the third switching means is input; a first latch circuit to which a pulse synchronized with both edges is input as a latch pulse; a second latch circuit to which a second output of the event counting means is input and relatted by the latch pulse; and a fourth switch means for switching between the output signal of the envelope comparison means and the output signal of the first latch circuit according to the output of the second latch circuit and outputting the same as the head amplifier switching signal. In the invention, the above-described configuration makes it possible to select a rotating magnetic head for use in any slow-motion playback method or double-speed playback, and to synchronize the switching timing with the head switching signal, thereby ensuring stable playback images. A magnetic recording/reproducing device can be obtained.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a VTR having a slow motion playback function according to an embodiment of the present invention, in which rotating magnetic heads 81 and 82 are close to each other, rotating magnetic heads 91 and 92 are close to each other, and Four rotating magnetic heads 81.82, 91.92, each arranged at a position of about 18 oo, with rotating magnetic heads 81 and 91 having the same azimuth angle and rotating magnetic heads 82 and 92 having the same azimuth angle.
A microprocessor 1o that controls the cylinder motor 2 that drives the magnetic tape 1t and the capstan motor 6 that causes the magnetic tape 1t to run at a constant speed and realizes a slow motion playback function, and a first analog signal output terminal from the microprocessor 10. a first drive circuit 12 that drives the cylinder motor 2 by a signal outputted via the first drive circuit 12;
A second drive circuit 13 that drives the capstan motor 6 by a signal outputted from the microprocessor 1o via a second analog signal output terminal 32, and the four rotating magnetic heads 81, 82, 91.92. A head amplifier circuit 11 that amplifies the obtained reproduced video signals and outputs an envelope comparison signal to be described later, the envelope comparison signal, the head switching signal, and the outputs of the output terminals 28, 27, and 28 of the microprocessor 1o. The entire structure includes a head amplifier switching circuit 14 which receives a signal and outputs a head amplifier switching signal, and input terminals 21 to 24 of the microprocessor 1o.
The outputs of the first frequency generator 3, the first phase detector 4, the control head 6, and the second frequency generator 7 are connected to.

The inside of the microprocessor 1o includes a register 1oo for storing data and a random access memory (indicated by the abbreviation "RAM" in the figure, hereinafter referred to as R).
It is abbreviated as AM. ) 20°, a 16-bit arithmetic unit (indicated by the abbreviation MULU in the figure, hereinafter abbreviated as MUI and U) 300 that executes arithmetic and logical operations on digital data, and An instruction to be executed is stored, and based on the instruction, the register 100 and the RAM 200 are connected to the memory I, U30 via the control bus 450.
4oO, an instruction execution circuit (indicated by the abbreviation PL in the figure) that controls the operation of 0, and a 17-pit time base counter that counts down the reference clock signal applied to the clock terminal 2o. In the figure, the count data of the time pace counter 6000 is supplied via the counter bus 550'i and the register 10o, the RAM 200. Said mu LU3
A capture register block (indicated by the abbreviation (3APR)EG in the figure) 700 and the first to sixth input terminals 21, 22, 23° are sent to the data bus 60o connected to the 24.25, and when the edges of six types of capture symbols, each having a different generation source, arrive, the count data of the time base counter 600 is transferred to the capture register block To.
capture controller (in the figure, CAP
It is designated by the abbreviation TRCTRL. ) 8oo 0 Further, the reference clock signal applied to the clock terminal 2o is provided with a timing generator (T in the figure).
It is indicated by the abbreviation G. ) 90o to the instruction execution circuit 400, and the data bus 600 includes a read-only memory (indicated by the abbreviation ROM in the figure, hereinafter abbreviated as ROM) 1000
First Dm converter 1400. Second (Z) Dmu converter 16
00, timer counter 1100. Master latch circuit 1200 for data output. Output terminal 26.27.28
There is an output latch circuit 160o connected to the output latch circuit 160o, and a slave latch circuit 1300 which takes in the output data of the master latch circuit 1200 in response to the count completion pulse of the timer counter 11oO.
i(j RAM 200 and the ROM 1000
have address decoders 250.1050i, respectively.

Note that when the edge of the capture signal arrives, the capture controller 800 and the capture register block 700 count from the time base counter 600 that the minimum decomposition accuracy is higher than the instruction execution cycle, and the instruction execution cycle is counted. 2 constitutes a capture circuit that sends the result to the input LU 300, the register 1oO, or the RAM 200 according to a specific command from the circuit 400. FIG. 2 shows the head amplifier circuit 11 and head amplifier switching circuit 14 of FIG. 1. The internal configuration of the head amplifier circuit 11 is the same as that of the head amplifier circuit shown in FIG. 17 described in connection with the prior art. Second
The head amplifier switching circuit 14 at the bottom of the figure has input terminal 1.
A flip-flop circuit 1 to which a head switching signal from 21 and a clock pulse from an input terminal 149 are input.
41.degree. 142, an exclusive logic circuit (hereinafter referred to as an EXOR gate circuit) 143 to which each bit output of the shift register is input, and an inverter circuit 144 that receives the head switching signal and its inverted signal.
a fourth switch circuit 146 which is controlled by a control signal (output signal of the output terminal 28 of the microprocessor 1o in FIG. 1) inputted from the input terminal 2; The first latch circuit 146 receives the output of the ICXOR gate circuit 143 as a latch pulse, and the data (
・Output data of the output terminal 27 of the microprocessor 10 in FIG. 1) is input, and the KXOR gate circuit 143
The second latch circuit 147 receives the output signal of the head amplifier circuit 11 as a latch pulse, the signal input from the input terminal 26 (the output signal of the output terminal 26 of the microprocessor 1o in FIG. Level comparator 11
8, the output envelope comparison signal and the output signal of the first latch circuit 146 are input, and a head amplifier switching signal is supplied to the head amplifier circuit 11 under the control of the output data of the second latch circuit 147. Regarding the VTR configured as above, the configuration diagram shown in FIG. 1 and the capture controller 8 shown in FIG.
The operation will be explained with reference to a specific configuration diagram of 00 and a timing chart of the main parts shown in FIG.

First, FIG. 3 shows the capture controller 800 of FIG.
is a logic circuit diagram showing a specific configuration example, in which control units 810 to 860 having the same configuration are connected to the first to sixth input terminals 21, 22, 23, and 24, and the control units 810 to 860 of the same configuration are connected. Units 810-850
have a common reference clock input terminal 801 and a data transfer lock input terminal 802'ii to the capture register block 700, and further have individual reset terminals 811-851 and individual flag output terminals 812-86.
2 and individual data transfer terminals 813 to 863.・Next, FIG. 4 shows a timing chart for explaining the operation of the control unit 860 comprising the capture controller 5ooNll shown in FIG. The clock signal waveform applied to FIG. 4B is a signal waveform obtained by frequency-dividing the signal waveform of FIG.
FIG. 4C shows the count clock signal waveform of the time base counter 5oO, which is composed of a synchronous counter whose unit stage is the 71J block flop of the master slave J[. At the edge), the output of the master part of the seven lip-flops of each unit stage changes, and at the trailing edge, the output of the slap section changes.

The fourth diagram shows the clock signal waveform for data transfer created from the signal waveforms in Figures 4 and B.
The data transfer lock input terminal 802 in the figure is supplied.

Now, when the signal waveform shown in FIG. 3E is applied to the sixth input terminal 26 in FIG.
”, the output level of the HAND gate 864 shifts to “1” as shown in 411F, and further, when the level of the reference clock input terminal 801 shifts to “o”, the output level of the HAND gate 866 shifts to “0”. shifts to "1" as shown in FIG. 4G, and then the reference clock input terminal 8010 level shifts to "1" again, the output level of the Tom ND gate 866 becomes "1" as shown in FIG. 4H. 1”. Each of the HAND gates 854, 855, and 856 is a pair of another HA.
Since it forms a bistable circuit with an ND gate, when the output level shifts to "1", it will maintain that state until a reset signal is applied to another NAND gate, but the output of the Tom ND gate 866 At the point when the level shifts to "1", the output level of the paired ND gate 867 shifts to rOJ, and the output level of the ND gate 868 also shifts to "1".
0'', the Nmu ND gates 864, 85
The output level of 6 returns to "0".

In this way, when the leading edge of the external signal arrives at the sixth input terminal 26, the second data transfer terminal 8
63, a signal line as shown in FIG. 3J is sent through the ND gate 869, and this signal causes the count data to be transferred from the time base counter 500 in FIG. 1 to the capture register block 700.

The output signal of the HAND gate 866 is sent to the flag output terminal 862 and is used as a capture flag signal indicating that the time pace counter 6000 count data has been transferred.
1, a reset signal is applied after software (program) confirms that this capture flag is set.

Next, FIG. 6 is a configuration diagram showing a specific example of the capture register block 700, in which each data input terminal is connected to a Do terminal to a D15 terminal, and a data output terminal is connected to a Q1 terminal to a Q1e terminal. unit registers 710 and 720 configured by 16 memory cells, and 16 memory cells whose data input terminals are connected to the D1 terminals to D16 terminals and whose data output terminals are connected to the Q1 terminals to Q16 terminals. The whole is composed of configured unit registers 730, 740, and 750. Note that each unit register 710 to 760 has 2
It has 7 control signal input terminals, and 7 read terminals.
Data transfer signals from the capture controller 800 shown in FIG. The output side of the unit register is activated, and a select signal for reading is applied to the data bus 600 in FIG. 1 via the data output terminals Q1 to Q1e.

By the way, in FIG. 5, unit registers 730 to 750
The connection position between the data input terminal and the data output terminal is shifted by one bit for the following reason.

First, regarding the unit registers 710 and 720, the LSB of the time base counter 600 and the LSB of the unit register are made to match in order to improve the resolution of the timing of capturing the edge of the external signal.
0 is shifted to the right by one bit of the data input terminal so that it can process up to twice the interval at once with the same number of pits as the unit registers 710 and 720. With such a bit shift configuration of the unit registers 730 to 760, for example, the frequency 2 of the reference clock signal
When selecting 2Mhz, 600n from unit registers 710 and 720! Count data with a resolution of i is obtained, while the unit registers 730 to 750 have a
The arrival period of an external signal having a frequency of about z can be measured in one process.

The operation of the VTR having the slow motion playback function configured as described above will be explained with reference to the configuration diagram shown in FIG. 1 and the sixth operation flowchart. FIG. 6 shows a microprocessor 1 shown in FIG.
12 is a flowchart showing an example of implementation using a program built into o. The flowchart in FIG. 6 will be explained with reference to the operational waveform diagram of a conventional VTR in FIG. 16.

Branch 401.404.408゜413.4 in Fig. 6
No. 17,421.427 executes the processes necessary for intermittently driving the capstan motor 6 in a sequence by branching according to the value of the state variable M,
First, when the sum is 0, branch 401 causes branch 401 to
2, a head switching signal (hereinafter referred to as H2N) is generated.

) is determined to be "1", and if so, the process moves to processing block 403 and the state variable M is set to "1".

When the signal level is 1, branch 404 advances to branch 406, where it is determined whether the signal level of the H8W signal is "0", and if it is, it means that a falling edge of the H8W signal has been detected, and processing block 406 , the time up to the start timing of the capstan motor 6 is subtracted from the count value of the time base counter 600 (down count) in FIG. . This corresponds to point f in FIG.

When the time is 2, branch 408 advances to branch 409, the count value of time base counter 600 (hereinafter referred to as TBO) is fetched, the count value is compared with the value written to the memory in processing block 406, and the value is determined as the first If it is within the timer 11000 count range in the figure, processing block 4
10, set the output data in the master latch circuit 120o shown in FIG.
Set to oO. Here, the data set in the master latch circuit is the signal corresponding to Fig. 16, that is, the motor O
This is to output the Hlo FF signal to the output terminal 29. The data-set timer transfers the data of the master latch circuit to the slave latch circuit 1300 after completion of counting regardless of software (program), so that a jitter-free signal can be obtained. Next, in processing block 411, the forced acceleration period (period from point g to point h in FIG. 16) is determined.
Similarly to 06, the count value is set in the memory and the number of people is set to 3 in processing block 412.

When A is 3, the 16th point corresponding to point h in FIG.
The signal in FIG. Here, the forced acceleration command signal is connected to the output of the second DMU converter 160o, which is the first factor (not shown).

When the time is 4, the process proceeds to branch 418, where it is determined by a flag whether or not a control signal input to the third input terminal of the capture controller 8oO has arrived;
If the control signal has arrived, processing block 4
19 and the TB when the control signal arrives
Capture register 70 that captures the count value of C
The data of 0 is taken into the accumulator cc (not shown) in the register 1oo in FIG. The result is stored in memory 2 and the value is set to 6 (1 point in Figure 16).

Here, the amount of slow tracking shifter stored in memory 1 is to absorb incompatibility of running conditions caused by variations in head mounting position and mechanism, etc., and it must be variable. Although not shown in the figure, when the microprocessor 1° outputs a trigger signal using a monostable monomultivibrator, the count value of the time base counter and the output signal of the monostable monomultivibrator are stored in the capture register. This can be achieved by finding the difference between the count values when input.

When the count value is 6, processing block 422 compares the data in memory 2 stored in processing block 419 with the TBO count value, and branches 423 and processing block 424.
The forced acceleration command signal and the 16th
Both current direction switching signals corresponding to Fig. 2 are set to "1",
The motor is brought into full deceleration state (point j in Figure 16). Next, in processing block 426, the braking period (16th
In order to determine the period from point C to point C in the figure), a count value is set in the memory in the same manner as in processing block 406, and in processing block 426, the count value is set to 6.

When the number of systems is 6, branch 428 and processing block 429 process the first point corresponding to the point in FIG.
Signal in Figure 5 Y, motor ON10 FF F signal 1OF
F to shift the capstan motor 6 to a stopped state.

With the above, the capstan motor 6 can be driven intermittently.

Next, the head amplifier switching operation during slow motion playback will be explained with reference to the flowcharts of FIGS. 7 and 8 and the operation waveform diagram of FIG. 9.

FIG. 7 shows an example in which means for counting the number of times the edge of the head switching signal arrives in synchronization with the intermittent operation of the capstan motor during slow motion playback is realized by a program built in the microprocessor 1o of FIG. FIG. 8 is a flowchart showing an example in which the head amplifier switching means during slow-motion playback of two forward tracks and one frame feed in the forward direction shown in FIG. 16 is realized by a program built in the microprocessor 1o shown in FIG. It is.

9 is a timing chart showing the internal operation of the head amplifier switching circuit 14 shown in FIG. 2 when the programs shown in FIGS. 7 and 8 are executed, and FIG. 9 J is a timing chart showing the internal operation of the head amplifier switching circuit 14 shown in FIG. These are the values of the state variables in the program that realizes intermittent operation. M is the seventh
This is count data as a result of executing a program that counts the number of times the edge of the head switching signal arrives (H8W count data, hereinafter abbreviated as H) in synchronization with the intermittent operation of the capstan motor shown in FIG. N is the output signal of the EXOR gate circuit 143 in FIG. 2, O in FIG. 9 is the output signal of the fourth switch circuit 146 in FIG. 2, and P in FIG. 9 is the output signal of the sixth switch in FIG. circuit 148
is the output signal of

The program for counting the number of arrivals of the edge of the head switching signal in synchronization with the intermittent operation of the capstan motor shown in FIG. If the value of variable m is less than 3 (capstan motor stopped state), HS W, count data Hk
o, and if the value of H8W is 3 or more, the branch 432 determines whether the current value of H is an odd number or an even number. If so, move to branch 433 and run H8
It is determined whether the W signal level is at H level. If both are true, the value of H is incremented by 1 in processing block 436, and if not, the value of H is held.

With the above program, the value of H changes in synchronization with the intermittent operation of the capstan motor, as shown in FIG. 9M.

The program for switching the head amplifier during slow motion playback of forward two tracks and one frame advance in Figure 8 is as follows:
First, in the processing block 437, the position of the sixth switch circuit 148 is changed to the position of the first latch circuit 147 by controlling the two input terminals 27-1 and 27-2 in FIG.
The branch 438 determines whether the H8W count data H detected by the program shown in FIG. The fourth switch circuit 146 is connected to the normal rotation signal side of the head switching signal, and if not, the process moves to processing block 439 and the fourth switch circuit 146 is connected to the inverted signal side (output of the inverter circuit 144) of the head switching signal. do.

Through the above processing, the output signal of the fourth switch circuit 146 in FIG. 2 becomes as shown in FIG. 90, and the output of the first latch circuit 146 and the output of the M5 switch circuit 148, that is, the head amplifier switching signal It is possible to obtain a signal synchronized with the head switching signal as shown in FIG. 9P, which does not have jitter due to processing delays peculiar to software. In other words, P in Fig. 9 obtained the same signal money as P in Fig. 16.

FIG. 10 shows the recording track pattern, head locus, and internal waveforms of the head amplifier circuit 11 when performing reverse slow-motion playback by intermittently driving the capstan motor in the reverse direction, all as shown in FIG. 16 above. In the case of reverse slow motion playback, when the capstan motor is driven intermittently, there is no head that can stably obtain a signal for one field period, and as shown in Figure 10e, the head output knob 9 has a high envelope signal level. It turns out that it is desirable to use heads selectively.

Therefore, as shown in FIG. 10, the envelope comparison signal is used as the head amplifier switching signal during the three field periods when the capstan motor is driven.

FIG. 11 is a flowchart showing an example in which the head amplifier switching means during slow motion playback of two backward tracks and one frame feed in FIG. 10 is realized by a program built in the microprocessor 1° of FIG. 1.

Figure 12 shows the second image when the program in Figure 11 is executed.
FIG. 12 is a timing chart showing the internal operation of the head amplifier switching circuit 14 shown in FIG. Signals with the same symbols as in FIG. 9 are the same signals as in FIG.

Processing block 441 in FIG.
46 is connected to the inverted signal of the head switching signal, that is, the output of the inverter circuit 144, and then the branch 442.
3, when the H8W count data H detected by the program in FIG. 7 is 1 and 4, respectively, processing block 4
44 and 445, a processing block 444 connects the sixth switch circuit 148 to the empe comparison circuit 118, and a processing block 446 connects the sixth switch circuit 148 to the empe comparison circuit 118.
is connected to the first latch circuit 147.

By the above processing, the head amplifier switching signal is synchronized with the head switching signal as shown in FIG. 12P, and the same signal as shown in FIG. 10 can be obtained. This is effective when fixing the head amplifier switching signal to 2 level or L level when playing back with the same head used during recording. However, head amplifier switching in the case of slow-motion playback in which one field is advanced per track can also be realized by the same method.Advantageous Effects of the InventionAs is clear from the above description, the magnetic recording and reproducing apparatus of the present invention A magnetic recording and reproducing device that performs slow-motion reproduction by repeatedly stopping and moving a magnetic tape transferred by a stun motor, in which a first and a third are close to each other, a second and a fourth are close to each other, and four rotating magnetic heads, each of which is arranged at a position of approximately 1800 degrees, the first and second having the same azimuth angle, and the third and fourth having the same azimuth angle; and the four rotating magnetic heads. a cylinder motor that drives the cylinder motor; and a first switch means for extracting reproduction signals from the two rotary magnetic heads in contact with the inner magnetic tape of each of the rotary magnetic heads based on a head switching signal indicating the rotational phase of the cylinder motor. , a second switch means for selecting all of the two reproduced signals from the first switch means, and two from the first switch means.
a comparison means for comparing two envelopes; and an event for counting the number of times the edge of the head switching signal arrives t in synchronization with the activation timing of the capstan motor during slow motion playback, and outputting a signal corresponding to a desired count value. a counting means; a third switching means for switching between the head switching signal and its inverted signal according to a first output of the event counting means;
A first latch circuit receives the output of the 0-sinch means and inputs pulses synchronized with both edges of the head switching signal as latch pulses, and a second latch circuit receives the output of the event count means and receives the latch pulses. and a second latch circuit that switches the output signal of the envelope comparison means and the output signal of the first latch circuit according to the output of the second latch circuit and outputs it as the head amplifier switching signal. This magnetic recording and reproducing apparatus is characterized in that it is equipped with the switch means of No. 4, and it is possible to obtain a magnetic recording and reproducing apparatus that is compatible with all kinds of slow-motion reproduction methods and special reproduction functions such as double-speed reproduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a magnetic recording/reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing the specific internal configuration of the head amplifier circuit 11 and head amplifier switching circuit 14 shown in FIG. 1, and FIG. Capture controller 800 in FIG.
4 is a timing chart explaining the circuit operation of FIG. 3, and FIG. 6 is a configuration diagram of a capture register block 700, and FIGS. 6, 7, and 8. 11 is a flowchart showing the operation of the main part of FIG. 1, FIGS. 9 and 12 are operation waveform diagrams for explaining the flowcharts of FIGS. Figure 16 shows the recording track pattern and head trajectory during slow motion playback of two tracks in the reverse and forward directions, respectively, and waveforms of various parts of the head amplifier switching circuit. Figure 13 shows the waveform diagram of each part of the conventional IZ) VTR. Block diagram showing the complete structure of the servo mechanism during operation, Figures 14 and 15
The figure is a timing chart for explaining the operation of the main parts in Figure 13, and Figure 17 is the head amplifier circuit 1 in Figure 13.
FIG. 1 is a block diagram showing the specific internal configuration of FIG. 1...Magnetic tape, 2...Cylinder motor, 6...Capstan motor, 11...
...Head amplifier, 14...Head amplifier switching circuit, 100...Register, 20Q...
...RAli, 300...MULU. 400... Instruction execution means, 60o...
Time pace counter, 7oO...Capture register controller, 800...Capture controller, 100o...ROM, 1100
...Timer, 1400.1500...
Dm converter. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 What is the enemy? Fig. 7 Fig. 8 ゛ Fig. 9 Fig. 11 Fig. 12 Fig. 1411 Fig. 15

Claims (1)

[Claims] A magnetic recording and reproducing device that performs slow motion playback by repeatedly stopping and moving a magnetic tape transferred by a capstan motor, wherein the first and third tapes are close to each other, and the second and fourth tapes are close to each other. and also each approximately 180°
four rotating magnetic heads arranged at positions, the first and second having the same azimuth angle, and the third and fourth having the same azimuth angle, and a cylinder motor that drives the four rotating magnetic heads; a first switch means for extracting reproduction signals from the two rotary magnetic heads in contact with the magnetic tape of each rotary magnetic head in response to a head switching signal indicating the rotational phase of the cylinder motor; a second switch means for selecting two reproduction signals from the first switch means; an envelope comparison means for comparing envelopes of the two reproduction signals from the first switch means; an event counting means for counting the number of times the edge of the head switching signal arrives in synchronization with the start-up timing of the stun motor and outputting a signal in accordance with a desired count value; and a first output of the event counting means. a third switch means for switching between the head switching signal and its inverted signal; a first switch to which the output of the third switch means is input, and a pulse synchronized with both edges of the head switch signal is input as a latch pulse; a latch circuit, and a second latch circuit into which the second output of the event counting means is inputted and latched by the latch pulse; 1
and fourth switch means for switching the output signal of the latch circuit and outputting it as the head amplifier switching signal.