JPH01276767A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable threshold to be controlled by providing a doped area doped with impurities at a part separated from the gate insulation film within non- doped a-Si-H layer laminated through a gate electrode and a gate insulation film and by placing source and drain electrodes coated by a silicate glass layer on it opposing each other. CONSTITUTION:A gate electrode G is formed on an insulation substrate 5. Then, an SiN film is formed as a gate insulation film 1 by the CVD method, an undoped a-Si:H layer 2 are formed on it, and a silicate glass BSG layer 4' including B as impurities is formed continuously, Then, the layer 4. is selectively removed and a BSG layer 4 placed opposing to an electrode G is formed. Then, as a contact layer, a source electrode S and a drain electrode D laminated with an n<+>a-Si layer 6 and a specified metal layer 7 are formed. By setting the channel forming area between a doped area 3 and the insulation film 1 to be an undoped one, reduction in mobility can be prevented. Also, since no impurities are doped at the lower layer of the electrodes S and D by forming the area 3, improper ohmic contact of electrodes S and D can be prevented and the threshold can be controlled.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, in which the dark value can be controlled without reducing mobility or causing ohmic contact failure. In a field effect thin film transistor in which a gate electrode, a gate insulating film, a non-doped amorphous silicon semiconductor active layer, and a source/drain electrode are sequentially stacked on an insulating substrate, a doped region doped with a predetermined impurity at an interface opposite to the gate electrode; a silicate glass layer covering the doped region and containing the predetermined impurity; The configuration is such that the two are sandwiched together.

[Industrial application field]

The present invention relates to a thin film transistor used as a switching element for an active matrix liquid crystal panel, and a method for manufacturing the same.

[Conventional technology]

Active matrix liquid crystal display devices using thin film transistors (TPTs) are expected to become the mainstream of full-color flat displays due to their excellent image quality. It requires a manufacturing process of
There is a problem that the yield tends to be low.

The amorphous silicon (a-3i) thin film transistor (TFT), which has been developed and is widely used as a switching element for driving the liquid crystal, is capable of controlling the dark voltage to a desired value and reducing the OFF current. is necessary.

For this purpose, M
Similar to the O3 type FET, it is necessary to dope impurities into the channel formation region of the semiconductor layer. That is, by doping the semiconductor layer with impurities, the amount of charge fixed in the space charge region is controlled, thereby setting the dark value to a desired value.

Controlling the dark value voltage of the TPT in this manner is necessary to diversify the matrix form and shorten the overall process.

A method of controlling the dark value by doping the semiconductor layer of a MOS or MIS transistor with an impurity element that serves as a donor or acceptor is to perform FET using single-crystal Si.
It is commonly used in the production of TP using a-3i.
There are also examples of doping T with boron (B) or phosphorus (P).

FIG. 3 is a diagram showing the structure of a TPT for performing conventional dark value control, in which a gate electrode G is provided on an insulating substrate 5, a gate insulating film 1. An active layer 12 consisting of an a-31=H layer doped with B is laminated, and a source electrode S and a drain electrode are disposed thereon with a protective layer JJ1)4 in between.

[Problem to be solved by the invention]

In the above structure, B was introduced during the formation of the a-3tsH layer in an attempt to move the dark value in the positive direction. is decreasing.

■ When doping impurities at a high concentration directly under the source and drain electrodes S and D, the active layer 1 of the source and drain electrodes
2, resulting in ohmic contact failure.

It turns out that there is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, in which the dark value can be controlled without reducing mobility or causing ohmic contact failure.

[Means to solve the problem]

As shown in FIG.
A doped region 3 doped with a predetermined impurity is provided in a region facing the gate electrode G and separated from the gate insulating film l, and a silicate glass layer 4 containing the doped impurity is provided on the doped region 3. A source electrode S and a drain electrode are placed facing each other with this silicate glass layer 4 in between.

In addition, in order to create a TPT with the above structure, the gate electrode G,
Gate insulating film 1. After laminating the non-doped a-3i:H layer 2, a silicate glass layer 42 containing a predetermined impurity, such as BSG (boron silicate glass), is placed on the non-doped a-3i:8 layer 2 in a region facing the gate electrode G. ) layer or PSG (W silicate glass) layer is selectively formed, and after arranging the source electrode S and the drain electrode facing each other with this silicate glass layer 4 in between, an annealing process is performed to form a PSG (W silicate glass) layer. By selectively diffusing impurities into the lower non-doped a-3T:H layer 2, the channel formation region is removed (gate insulating film 1
A doped region 3 is formed at a location separated from the doped region 3.

[For production]

As a result of various studies, the inventors of the present invention have found that, among the above problems, regarding (2), by making the non-doped 3tsH layer 2 non-doped only near the interface with the gate insulating film 1, the doped 6u region 3 can be made to have a high concentration. However, no decrease in mobility was observed, and there was also the effect of dark value control. Regarding (2), doping was selectively performed only in the region facing the gate electrode G, avoiding doping directly under the source and drain electrodes S and D. We found that it is effective to do the following.

The present invention takes advantage of this fact, and involves doping in the channel forming region, which causes a decrease in mobility.

By avoiding doping to the S/D electrodes, which causes S/D contact defects, it is possible to prevent a decrease in mobility and the occurrence of ohmic contact defects. It doesn't make it complicated.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 2(a) to 2(d).

As shown in FIG. 2(a), a gate electrode G is formed on an insulating substrate 5 such as a glass substrate, and then a gate insulating film L is formed using a plasma chemical vapor deposition (cVD) method. It has a 5iN (silicon nitride) film with a thickness of 5iN, and a non-doped A-3T:8 layer 2 with a thickness of about 100 to 3000 on it, and a thickness of about 1000 with B (boron) as an impurity. containing silicate glass (BSG)
) Layer 4'' is successively deposited.

Next, the 830 layer 4' is selectively removed according to a predetermined pattern to form the BSG layer 4 disposed opposite to the gate electrode G, as shown in FIG. 4B.

Next, as shown in the same figure (C), n as contact l
``A source electrode S and a drain electrode are formed by laminating the a-3i layer 6 and a predetermined metal layer 7.

Next, an annealing step is performed to selectively diffuse B from the 830 layer 4 into the non-doped a-3i:I (layer 2) immediately below it, forming a doped 6u region 3 as shown in the figure.

What should be noted here is that when forming the doped region 3, the interface between the non-doped a-3t:8 layer 2 and the gate insulating film 1° is left undoped, and the doped region 3 is separated from the gate insulating film 1. The goal is to form The non-doped region between the doped region 3 and the gate insulating film 1 is a region where a channel is formed during operation of the TPT according to the present invention, and by making this region non-doped, a decrease in mobility can be prevented. .

In this example, by forming the doped region 3 as described above, it only spreads slightly in the lateral direction from the bottom of the BSGSiO2, so that the lower layer of the source electrode S and the drain electrode is not doped with impurities. do not have. Therefore, it is also possible to prevent the ohmic contact between the source electrode S and the drain electrode from becoming defective.

Therefore, in this embodiment, it is possible to control the dark value of the TPT without causing a decrease in mobility or a defective ohmic contact, which were problems in the prior art.

In the above embodiment, the silicate glass layer 4 is made of B.
Although an example using a silicate glass layer containing P (phosphorus), that is, an 830 layer has been described, this does not limit the present invention; for example, a PSG layer that is a silicate glass layer containing P (phosphorus) may be used. Needless to say.

〔Effect of the invention〕

As explained above, according to the present invention, the dark value can be controlled without complicating the process or deteriorating the characteristics, so that TPT matrix type liquid crystal display devices and their manufacturing methods can be diversified. I can do it.

For example, the "gate-connected opposing matrix" method proposed earlier by the present inventors has many advantages, but it has the limitation that it does not operate unless the dark value of TPT is a positive voltage.
Although it has been difficult to form PT, by using the present invention, it becomes easy to create a liquid crystal display device of the above type.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of the present invention, FIGS. 2(a) to (d) are detailed explanatory diagrams of the present invention, and FIG. 3 is an explanatory diagram of problems with the conventional TPT. In the figure, 1 is a gate insulating film, 2 is a non-doped a-3
i: HN, 3 is the doped region, 4 is the silicate glass layer, 5 is the insulating substrate, 6 is the contact layer (n” a-3i
: 8 layers), 7 is a metal layer, G is a gate electrode, S is a source electrode, and D is a drain electrode. 4 し１堡I-7・Lasl 豐4＞Mitsucho/I lecture practice practice Seki 1st figure Shizutoka 9≦6■-pu de difference image rttvsr';b
Figure 2

Claims (2)

[Claims] (1) A gate electrode (G), a gate insulating film (1), an active layer (2) made of undoped amorphous silicon, and source/drain electrodes (S, D) are sequentially stacked on an insulating substrate (5). A field effect thin film transistor comprising: a doped region (3) doped with a predetermined impurity at an interface of the active layer (2) made of amorphous silicon on the opposite side to the gate electrode (G); and the doped region (3), and contains a silicate glass layer (4) containing the predetermined impurities.
), wherein the source/drain electrodes (S, D) are formed with the silicate glass layer (4) interposed therebetween. (2) After forming a gate electrode (G) on an insulating substrate (5), a gate insulating film (1) is formed on the insulating substrate including the top of the gate electrode, and an active layer made of non-doped amorphous silicon is formed. layer(
2), and a silicate glass layer (4) containing predetermined impurities in a portion corresponding to the gate electrode (G) on the active layer (2);
Then, the impurities contained in the silicate glass layer (4) are diffused into the active layer immediately below the silicate glass layer to such an extent that the active layer remains at a predetermined thickness to form a doped region (4).
8) A method for manufacturing a thin film transistor, comprising the step of forming.