JPH0262077A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH0262077A JPH0262077A JP63213311A JP21331188A JPH0262077A JP H0262077 A JPH0262077 A JP H0262077A JP 63213311 A JP63213311 A JP 63213311A JP 21331188 A JP21331188 A JP 21331188A JP H0262077 A JPH0262077 A JP H0262077A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- thin film
- doped
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 13
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract description 5
- 230000036211 photosensitivity Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 230000010748 Photoabsorption Effects 0.000 abstract 1
- 229910006992 Si1-xCx Inorganic materials 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
液晶駆動用の薄膜トランジスタの構造に関し、製造工程
を増加させることなく、良好なオン/オフ特性を有する
薄膜トランジスタの改良された構造を提供することを目
的とし、
動作半導体層の一主面側にゲート絶縁膜を介してゲート
電極、他の主面側にソース、ドレイン電極を配設した薄
膜トランジスタの構成において、前記動作半導体層を、
ゲート絶縁膜側に配設したノンドープのアモルファスシ
リコン層と、反対側に配設した前記ノンドープのアモル
ファスシリコン層より大きいバンドギャップを有する第
2の半導体層との2層構成とした構成とする。[Detailed Description of the Invention] [Summary] Regarding the structure of a thin film transistor for driving a liquid crystal, the present invention aims to provide an improved structure of a thin film transistor having good on/off characteristics without increasing the number of manufacturing steps. In the structure of a thin film transistor in which a gate electrode is provided on one main surface side of an active semiconductor layer via a gate insulating film, and a source and drain electrode are provided on the other main surface side, the active semiconductor layer is
The structure has a two-layer structure including a non-doped amorphous silicon layer disposed on the gate insulating film side and a second semiconductor layer having a larger band gap than the non-doped amorphous silicon layer disposed on the opposite side.
〔産業上の利用分野]
本発明は液晶駆動用の薄膜トランジスタの構造に関する
。[Industrial Application Field] The present invention relates to the structure of a thin film transistor for driving a liquid crystal.
液晶表示装置は低消費電力、軽量、カラー表示が容易な
どの特徴を有するため、ポケットTV。Liquid crystal display devices are popular among pocket TVs because they have characteristics such as low power consumption, light weight, and easy color display.
OA端末機器などの平面表示装置として広範囲な市場を
得つつある。特に薄膜トランジスタ駆動のアクティブマ
トリクス型表示装置は、鮮明な階調表示が可能なため、
将来を期待されている。It is gaining a wide market as a flat display device for OA terminal equipment and the like. In particular, active matrix display devices driven by thin film transistors are capable of displaying clear gradations.
There are high expectations for the future.
しかじのこアクティブマトリクス型表示装置では、駆動
用のTPT素子の特性を大面積にわたって均一に、且つ
、無欠陥で形成する必要があり、製造技術としては、大
きなブレークスルーが必要とされている。In active matrix display devices, it is necessary to form the drive TPT element with uniform characteristics over a large area and without defects, and a major breakthrough is needed in terms of manufacturing technology. .
従来より液晶駆動用の薄膜トランジスタは、金属膜から
なるゲート電極、5iN(窒化シリコン)膜のようなゲ
ート絶縁膜、a−3i(アモルファスシリコン)からな
る動作半導体層の積層構造を透明絶縁性基板上に形成し
ていた
上記動作半導体層であるノンドープのa−3i層は、白
色光をよく吸収し、そのため光が入射するとオフ電流が
増加し、駆動用のTPTスイッチとしてのオン/オフ特
性が低下する。Conventionally, thin film transistors for driving liquid crystals have a stacked structure of a gate electrode made of a metal film, a gate insulating film such as a 5iN (silicon nitride) film, and an active semiconductor layer made of a-3i (amorphous silicon) on a transparent insulating substrate. The non-doped a-3i layer, which is the operating semiconductor layer formed in the above, absorbs white light well, so when light is incident, the off-state current increases and the on/off characteristics as a driving TPT switch deteriorate. do.
これを解決する手段として、a−3i層の膜厚を300
人程エフ薄くし、更に遮光膜を形成するのが一般的とな
っている。As a means to solve this problem, the thickness of the a-3i layer was increased to 300 mm.
It is common practice to make the film as thin as possible and to form a light-shielding film.
ところが上述のようにa−3i層の膜厚を薄くすると、
大面積におけるa−3i層の膜厚、その他特性の均一性
、再現性が低下し、且つ、遮光膜を形成するための工程
が増加し、製造歩留の低下を招き、低コスト化が困難と
なっていた。However, when the thickness of the a-3i layer is reduced as described above,
The uniformity and reproducibility of the film thickness of the A-3I layer over a large area and other properties are reduced, and the number of steps required to form a light-shielding film is increased, leading to a decrease in manufacturing yield and making it difficult to reduce costs. It became.
本発明はこのような欠点を取り除くため、製造工程を増
加させることなく、良好なオン/オフ特性を有する薄膜
トランジスタの改良された構造を提供することを目的と
する。SUMMARY OF THE INVENTION In order to eliminate these drawbacks, it is an object of the present invention to provide an improved structure of a thin film transistor having good on/off characteristics without increasing the manufacturing process.
本発明は第1図に示す如く、動作半導体層4をゲート絶
縁膜3に接するノンドープのa−3i層4aと、a
Si層−xcx層(カーボン・ドープ・アモルファス・
シリコン)層や、a−3iNX(窒素ドープ・アモルフ
ァスシリコン)層のような、a−3iよりバンドギャッ
プが大きく、従って白色光に対する光感度がa−3iよ
り低い第2の半導体層4bとの2層構成とした。As shown in FIG.
Si layer-xcx layer (carbon doped amorphous
2 with a second semiconductor layer 4b, such as a silicon layer or an a-3i NX (nitrogen-doped amorphous silicon) layer, which has a larger band gap than a-3i and therefore has lower photosensitivity to white light than a-3i. It has a layered structure.
上記ノンドープミー3i層4aの膜厚は、光電流を小さ
くするため従来同様に300Å以下と薄くし、第2の半
導体層4bの膜厚はノンドープa−3iN4aより十分
に厚くし、両者を合わせて動作半導体層4として必要な
膜厚に形成する。The thickness of the non-doped Me3i layer 4a is made as thin as 300 Å or less in order to reduce the photocurrent, as in the conventional case, and the thickness of the second semiconductor layer 4b is made sufficiently thicker than the non-doped A-3iN4a. The active semiconductor layer 4 is formed to a required thickness.
かかる構成としたことにより、ノンドープ半導体層4a
は例えば100Å以下の厚さとすることも可能であり、
従って光吸収をきわめて少なくできる。With this configuration, the non-doped semiconductor layer 4a
For example, it is possible to have a thickness of 100 Å or less,
Therefore, light absorption can be extremely reduced.
薄膜トランジスタの主な特性を決定するゲート絶縁膜3
と動作半導体層4との界面特性は、ゲート絶縁膜3であ
るSiN膜またはSfO,膜とノンドープミー3i層4
aが接触するよう構成されているので従来と変わらず、
a−3i層4aを薄膜化することによって発生する膜質
等特性の不均一性、動作半導体層4の破断等は、第2の
半導体層4bを積層したことによって補われる。Gate insulating film 3 that determines the main characteristics of thin film transistors
The interface characteristics between the gate insulating film 3, which is a SiN film or SfO, and the non-doped Mi layer 4 are as follows.
Since it is configured so that a is in contact, it is the same as before,
Non-uniformity in properties such as film quality, breakage of the active semiconductor layer 4, etc. caused by thinning the a-3i layer 4a can be compensated for by laminating the second semiconductor layer 4b.
本発明の要部構成であるa−3i層とa−3iXCX層
またはa−Si層とa Si層−xNxの積層構造は
、同一反応室内において連続的に形成できるため、製造
工程数は増加せず、且つ、a−3i層4aを薄くしたこ
とにより、液晶表示用の照明光(自然光)の吸収量が少
なくなるので、光が入射することによるオフ電流の増加
を防ぐことができ、従って遮光膜は不必要となり、この
点からも製造工程が簡単化される。The laminated structure of the a-3i layer and the a-3i First, by making the a-3i layer 4a thinner, the amount of absorption of illumination light (natural light) for liquid crystal display is reduced, so it is possible to prevent an increase in off-state current due to incident light, and therefore, light shielding is achieved. A membrane becomes unnecessary, and the manufacturing process is simplified in this respect as well.
以下本発明の−・実施例を第2図および第3図により説
明する。Embodiments of the present invention will be described below with reference to FIGS. 2 and 3.
第2図にa 5in−xCx層4bの白色光に対する
光導電率を示す。Xの値を増加、即ちC(カーボン)の
ドープ量が増加すると、光導電率はノンドープミー3i
層即ちx=0の場合と比較して数桁低下する。従って、
ノンドープミーSi54a上に形成するa Si層−
xCx層4bの厚さが高々1000エフ度であっても、
光に対する感度を十分に抑制できる。FIG. 2 shows the photoconductivity of the a5in-xCx layer 4b for white light. When the value of X increases, that is, the amount of C (carbon) doped increases, the photoconductivity increases to
ie, several orders of magnitude lower than the case where x=0. Therefore,
A Si layer formed on non-doped Si54a
Even if the thickness of the xCx layer 4b is at most 1000 F degrees,
Sensitivity to light can be sufficiently suppressed.
これを利用した一実施例を第3図に示す。An example using this is shown in FIG. 3.
本実施例では動作半導体層4を、約100人の厚さのノ
ンドープミー3i層4aと、約500人の厚さのa
S I I−X Cx層4bとの2層構成とした例であ
る。In this embodiment, the active semiconductor layer 4 includes a non-doped 3i layer 4a with a thickness of about 100 mm and a layer 4a with a thickness of about 500 mm.
This is an example of a two-layer structure including the S I I-X Cx layer 4b.
このほか、透明絶縁性基板としてガラス基板1を用い、
ゲート電極2はTi膜よりなり、ゲート絶縁膜は5iN
(窒化シリコン)膜、コンタクト層はn’a−3i層、
電極金属膜はTi膜6.チャネル保護膜は5iOz膜7
を用いて形成した。In addition, using a glass substrate 1 as a transparent insulating substrate,
The gate electrode 2 is made of a Ti film, and the gate insulating film is made of 5iN.
(silicon nitride) film, contact layer is n'a-3i layer,
The electrode metal film is a Ti film6. Channel protective film is 5iOz film 7
It was formed using
これらについては通常の薄膜トランジスタと特に異なる
点はない。There is no particular difference between these and ordinary thin film transistors.
なお、コンタクト層5としては本実施例のn゛a−Si
層5に変えて、n’ a−31t−XCX層を用いるこ
とも可能である。Note that the contact layer 5 is made of nya-Si of this embodiment.
Instead of layer 5, it is also possible to use an n' a-31t-XCX layer.
液晶表示用白色光に対して光感度のあるa−Si層4a
のH’J厚が100人しかないため、白色光が当たって
もオフ電流は増加せず、安定した動作ができる。また第
2の半導体層4bであるa−3it−xCxCx層は、
SiとCの量を変化させることによって光感度や導電率
の制御も可能となり、薄膜トランジスタの特性を広範囲
に制御可能となる。a-Si layer 4a with photosensitivity to white light for liquid crystal display
Since the H'J thickness is only 100, the off-state current does not increase even when exposed to white light, allowing stable operation. Further, the a-3it-xCxCx layer which is the second semiconductor layer 4b is
By changing the amounts of Si and C, it is also possible to control photosensitivity and conductivity, making it possible to control the characteristics of thin film transistors over a wide range.
なお−上記−実施例の薄膜トランジスタは、逆スタガー
ド型で説明したが、本発明はスタガード型にも適用でき
る。Note that although the thin film transistor in the above-described embodiment has been described as an inverted staggered type, the present invention can also be applied to a staggered type.
以上の説明から明らかなように本発明によれば薄膜トラ
ンジスタの動作半導体層を2層とし、電気的特性を第1
層・が主に持ち、第2層はその補助の役目を果たし、特
性均一性の向丘をもたらし、且つ、光感度がないため遮
光膜が不要となり、製造工程も簡単化される。As is clear from the above description, according to the present invention, the operating semiconductor layer of the thin film transistor is made of two layers, and the electrical characteristics are
The second layer serves as an auxiliary layer, which improves the uniformity of characteristics, and since there is no photosensitivity, there is no need for a light-shielding film, which simplifies the manufacturing process.
第1図は本発明の構成説明図、
第2図はa S j I−X Cx層の光導電率の変
化を示す図、
第3図は本発明一実施例説明図である。
図において、
l :透明絶縁1生基)反(ガラス基板)2 ;ゲート
電極
3 ;ゲート絶縁膜(SiN膜)
4 :動作半導体層
4a:ノンドーブa−3i層
4b:第2の半導体層(a S i 1−x Cx層
)5 :コンタクト層(n″a−Si層)6 :電極金
属膜(Ti膜)
7 :チャネル保護膜(S i O,膜)を示す。
7 ’fff*I4 (7tXtn
不発朗端Q’tえ朗m
第1rA
O
0,5
a−Si +−XC覧トχ4−窒f/l吏Rr75iO
z#1
しl#七首1日e4−尖しざ擾(七イ列鏡EJE(コ【
1第3図FIG. 1 is a diagram illustrating the structure of the present invention, FIG. 2 is a diagram showing a change in photoconductivity of an a S j IX Cx layer, and FIG. 3 is a diagram illustrating an embodiment of the present invention. In the figure, 1: Transparent insulation 1 (Glass substrate) 2; Gate electrode 3; Gate insulating film (SiN film) 4: Operating semiconductor layer 4a: Non-doped a-3i layer 4b: Second semiconductor layer (a S i 1-x Cx layer) 5 : Contact layer (n″a-Si layer) 6 : Electrode metal film (Ti film) 7 : Channel protective film (S i O, film). 7 'fff*I4 ( 7 t
z # 1 Shil # Seven heads 1 day e4 - Pointed mirror EJE (Ko [
1Figure 3
Claims (1)
介してゲート電極(2)、他の主面側にソース、ドレイ
ン電極(S、D)を配設した薄膜トランジスタの構成に
おいて、 前記動作半導体層(4)を、ゲート絶縁膜側(3)に配
設したノンドープのアモルファスシリコン層(4a)と
、反対側に配設した前記ノンドープのアモルファスシリ
コン層(4a)より大きいバンドギャップを有する第2
の半導体層(4b)との2層構成としたことを特徴とす
る薄膜トランジスタ。[Claims] A gate electrode (2) is arranged on one main surface side of the active semiconductor layer (4) via a gate insulating film (3), and source and drain electrodes (S, D) are arranged on the other main surface side. In the structure of the thin film transistor provided, the active semiconductor layer (4) includes a non-doped amorphous silicon layer (4a) disposed on the gate insulating film side (3), and a non-doped amorphous silicon layer (4a) disposed on the opposite side. 4a) the second with larger bandgap
A thin film transistor characterized by having a two-layer structure including a semiconductor layer (4b).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63213311A JPH0262077A (en) | 1988-08-26 | 1988-08-26 | Thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63213311A JPH0262077A (en) | 1988-08-26 | 1988-08-26 | Thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0262077A true JPH0262077A (en) | 1990-03-01 |
Family
ID=16637036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63213311A Pending JPH0262077A (en) | 1988-08-26 | 1988-08-26 | Thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0262077A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
US5614732A (en) * | 1990-11-20 | 1997-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Gate insulated field effect transistors and method of manufacturing the same |
JP2009170905A (en) * | 2008-01-15 | 2009-07-30 | Samsung Electronics Co Ltd | Display substrate and display including the same |
US7858982B2 (en) | 2004-09-24 | 2010-12-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
-
1988
- 1988-08-26 JP JP63213311A patent/JPH0262077A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
US5614732A (en) * | 1990-11-20 | 1997-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Gate insulated field effect transistors and method of manufacturing the same |
US5859445A (en) * | 1990-11-20 | 1999-01-12 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device including thin film transistors having spoiling impurities added thereto |
US6011277A (en) * | 1990-11-20 | 2000-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Gate insulated field effect transistors and method of manufacturing the same |
US7858982B2 (en) | 2004-09-24 | 2010-12-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
US8252639B2 (en) | 2004-09-24 | 2012-08-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
JP2009170905A (en) * | 2008-01-15 | 2009-07-30 | Samsung Electronics Co Ltd | Display substrate and display including the same |
KR101425131B1 (en) * | 2008-01-15 | 2014-07-31 | 삼성디스플레이 주식회사 | Display substrate and display device comprising the same |
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