JPH01272332A - Different speed multiplexing/demultiplexing circuit - Google Patents

Abstract

PURPOSE:To allow the title circuit to flexibly correspond to a change in a data speed by multiplexing the output of a channel data multiplexing means for multiplexing different speed data in each channel as a format putting effective bits excluding invalid bits forward closely. CONSTITUTION:A channel data multiplexing means 3 multiplies different speed data in each channel. Since only effective bits out of the output of the channel data multiplexing means 3 are successively written in the 1st storing means 5 by using an output from the 1st channel speed setting means 4 and read out, multiplexing is executed as a format putting effective bits excluding invalid bits forward closely. On the other hand, inputted multiplexed data are written in the 2nd storing means 7, invalid bits are added in each channel by a read control signal outputted from the 2nd channel speed setting means 6 and the added data are read out as converted data. The converted data are separated into respective channel data by a channel separating means 8.

Description

[Detailed description of the invention] 〔overview〕 Different speed data is time-division multiplexed on a channel-by-channel basis.

Or, with regard to different speed multiplexing/demultiplexing circuits used when separating different speed data that has been time-division multiplexed, the purpose is to be able to flexibly respond to changes in data speeds and channels used. By using a multiplex circuit, a channel data multiplexing means that multiplexes data at different speeds for each channel, and a predetermined data speed for each channel, it is possible to write valid focus and inhibit writing of invalid bits for each channel. a first channel speed setting means for sending a write control signal to cause the writing to be performed; and an output of the channel data multiplexing means using the output of the first channel speed setting means.

a first storage means in which only valid bits are sequentially written and read, thereby multiplexing the valid bits in a front-justified form, excluding invalid bits;
Read valid bits for each channel by setting a predetermined data rate for each channel using the different speed separation circuit.

or a second channel speed setting means for transmitting a read control signal that prohibits reading of valid bits, and the input multiplexed data is written, and an invalid focus is added to each channel by the read control signal and converted. The converter is configured to have a second storage means that is read out as data, and a channel separation means that separates the converted data into each channel data and outputs the data.

[Industrial application field]

The present invention relates to a different speed multiplexing/demultiplexing circuit used when time-division multiplexing different speed data on a channel-by-channel basis or separating time-division multiplexed different speed data.

Currently, PCM is the audio encoding method used in public communication networks.
A coding scheme is used and the audio signal is transmitted as 64Kb digital information.

However, since both the signal source and receiver of voice communication are humans, the voice signal contains considerable redundancy. Therefore,
When transmitting or storing sound, it is possible to reproduce sound with sufficiently high quality without completely transmitting and receiving the information contained in the sound.

For example, the sound quality is close to that of the conventional 64-b PCM system.

Lower data rates (e.g. 32Kb8, 15K
b/s, etc.), research is underway.

Therefore, the time division multiplexing/demultiplexing circuit is designed to be able to flexibly respond to changes in data speed and channels used when time division multiplexing different speed data on a channel-by-channel basis or separating time-divided different speed data. It is necessary to do so.

[Conventional technology]

FIG. 8 is a block diagram of a conventional example of a different speed multiplexing circuit.

9 is an explanatory diagram of the operation of FIG. 8, FIG. 10 is a block diagram of a conventional example of the different speed separation circuit, and FIG. 11 is an explanatory diagram of the operation of FIG. Here, Figure 9 and Figure 1! The symbols on the left side of the figure are the waveforms of the parts with the same symbols in FIGS. 8 and 10,
Further, the numbers in the waveform indicate the number of effective bits occupying one channel, and the shaded portion indicates the invalid bit portion.

The operation shown in FIG. 8 will be explained below with reference to FIG.

First, when the number of bits per channel of the channel with the highest data rate is taken as the number of bits in one channel, as the data rate becomes slower, the number of effective bits occupying one channel decreases and the number of invalid bits increases.

For example, in the CHI shown in FIG. 9--1, each channel consists of 8 effective bits, and has the fastest data rate (this is the number of bits in one channel).

C12 shown in Figure 9-■ consists of 6 valid bits and 2 invalid bits, and CH3 shown in Figure 9-■
consists of 4 valid bits and 4 invalid bits, CH4 shown in Figure 9-■ consists of 2 valid pins and 6 invalid bits, and the data rate of CHI4 is the slowest. .

Now, in the different speed multiplex circuit, the input 0111 to C
The data of I4 is converted into 8 bits, 6 bits, and 6 bits, which are only effective bits, in the corresponding serial/parallel conversion circuits 11 to 14 using the S/P timing shown in Figure 8-○, ■, ■, ■.
After being converted to 4-bit and 2-bit parallel data, the 9th
The parallel/serial converter circuit 15 is loaded with the P/S load pulse shown in Figure 1, and its output is as shown in Figure 9 [Phase]. ).

Therefore, as shown in Figure 9-○, the old write control signal has a valid bit part of 1 (indicating writable) and an invalid bit part of 0 (indicating write prohibition), and Figure 9-○. After loading only the effective bit part into the FIFO type memory 1G using the signal line that resets the write address to address 1 as shown in Figure 9-■, reset the read address to address 1 as shown in Figure 9-■. ) using signal RR to
Read and output multiplexed data as shown in (3).

Next, in the different speed separation circuit, the multiplexed data as shown in Figure 11-■ is written at the write address shown in Figure 11-■.
Using the signal -R to reset to the address, the FIF in Figure 10
O-type memo memory 21 is loaded.

Then, as shown in FIG. 11-■, the read control signal RI in which the 20-bit valid bit part is 1 and the 12-bit invalid bit part is O, and the RR shown in FIG. 11-■ are input. By this, Figure 11-a.

Invalid bits are added to b and c, and the first stage separation is performed with Cl1l to CI4 as one block, as shown in Fig. 11-
Serial/parallel conversion circuit 22 using S/P timing of 〇
added to.

Therefore, parallel data of 8 bits, 6 bits, 4 bits, and 2 bits for each channel of CI (1 to CH4) is input to the corresponding parallel/serial conversion circuits 23 to 26.

Figure 11 - Timing T1 shown in ■, @, @, ■
Using T4, the data is converted into serial data as shown in Figure 11-■, ■, o, and ■, and data from CI to CH4 is obtained (see Figure 11-■).

[Problem to be solved by the invention]

Here, Cl1l to CI+4 input to the different speed multiplex circuit
The data is converted into parallel data by the serial/parallel conversion circuit, and further converted into multiplexed data with invalid bits removed by the parallel/serial conversion circuit, but the channel position on the frame is unique by the above conversion circuit. It will be decided.

That is, since the channel position is determined and the data rate is fixed, changing the rate requires changing the conversion circuit itself, which is not easy to handle. Incidentally, this problem also applies to different speed separation circuits.

An object of the present invention is to make it possible to flexibly respond to changes in data speed and channels used.

[Means to solve problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, 3 is a channel data multiplexing means for multiplexing data at different speeds on a channel-by-channel basis, and 4 is a means for writing valid bits for each channel by setting a predetermined data rate on a channel-by-channel basis.

A first channel speed setting means sends a write control signal to inhibit writing of invalid bits, and 5 uses the output of the first channel speed setting means to select one of the outputs of the channel data multiplexing means. , in which only valid bits are sequentially written and read, thereby multiplexing valid bits in a front-justified form excluding invalid bits.
It is a storage means for

Further, 6 is a second channel speed setting means that sends out a read control signal for reading valid bits or prohibiting reading of valid bits for each channel by setting a predetermined data rate for each channel. ,
7 is a second storage means into which the input multiplexed data is written, an invalid bit is added to each channel according to the read control signal, and is read out as converted data; 8 is a second storage means in which the input multiplexed data is read out as converted data; This is channel separation means that separates and outputs the signals.

[Effect].

Now, the operation of the different speed multiplex circuit of the present invention will be explained with reference to FIG. Note that the crossed diagonal lines in FIG. 2 indicate valid bits, and the blank areas indicate invalid bits.

CHI data to CHn data of different speeds as shown in "CHI data to CHn data" in FIG. 2 are added to the channel data multiplexing means 3 in synchronization with the frame.

As shown in "Multiplexed Data 1" in FIG. 2, the data is serially multiplexed in units of channels, but since this multiplexed data includes invalid bits, these are removed.

Therefore, by setting the speed for each channel in the first channel speed setting means 4, that is, setting the predetermined number of effective bits, the write control signal as shown in "Old" in FIG. occurs.

In this old method, the effective bit part of multiplexed data l is I+,
Since the invalid bit part is set to L and writing of the invalid bit to the first storage means 5 is prohibited, the multiplexed data 1 excluding the invalid bit is written to the first storage means 5, and the read address is set at the beginning. The "multiplexed data" shown in FIG. 2 is read out using the signal RR designated by . Note that the ridge is a signal that specifies the write address as the beginning.

Next, the operation of the different speed separation circuit of the present invention will be explained with reference to FIG.

The second channel speed setting means 6 sets the speed, that is, the effective number of bits, for each channel, and sets "R1" in FIG.
” generates a read control signal R1 as shown in “.
1 is H during valid bits and L during invalid bits, as in 1) above.

Now, the "multiplexed data" in FIG. 3 is stored in the second storage means 7 using "-R" in FIG. 3, which specifies the starting address as described above.
The data is written in the data, read out using the above Br and "RR" in FIG. 3, and separated in series in channel units to obtain the "conversion data" in FIG. 3.

Then, this converted data is transferred to CHI by channel separation means 8.
~CHn data.

Here, since the data rate can be set for each channel using the first channel rate setting 4 and the second channel rate setting, it is possible to flexibly respond to changes in data rate and channels used.

〔Example〕

FIG. 4 is a block diagram of an embodiment of the different speed multiplexing circuit, and FIG. 5 is an explanatory diagram of the operation of FIG. 4.

Here, the selector 31 is a constituent part of the channel data multiplexing means 3, and a channel speed setting part 41. Selector 42.
ROM 43. Counter 44. The inverter 45 is a component of the first channel speed setting means 4, and the memory 51
shows the constituent parts of the first storage means 5. Further, the symbols on the left side of FIG. 5 indicate the waveforms of the portions with the same symbols in FIG. 4, and the shaded portions indicate invalid bit portions.

Assuming that the input channel data is the same as the conventional example,
The operation shown in FIG. 4 will be explained with reference to FIG.

First, when the predetermined data rate of each channel, that is, the number of effective bits, is set in the channel speed setting section 41, this setting data is input to the selector 42. Then, as shown in FIG. 5--, setting data for each channel is selected by a select signal indicating the positions of C111 to C)14 and added to the ROM 43 as an address.

Since the initial value of the counter 44 for generating the old mark part as shown in Fig. 5-■ is written in this ROM, the initial value of the counter 44 corresponding to the address is output (Fig. -Refer to ■).

On the other hand, C shown in FIG.
The l1l data to CH4 data are selected by a select signal and converted into multiplexed data as shown in FIG.

Here, the counter is loaded with the above-mentioned initial value for each channel using the load signal shown in FIG.
By inputting the signal to the EP (enable P) terminal through the counter 44, even if the counter 44 overflows, it does not increment until the initial value of the next channel is loaded, and continues to output ripple carry 1.

For example, in the case of ゛, C) 12, the number of effective bits is 6, so 6 set in the channel speed setting section 41 is inputted as the address of the ROM 43 via the selector 42. Since 2 is written to this address, 2 is added to the counter as the initial value of the counter, and 9. For example, an octal counter is 6.
When counted, send out a ripple carry.

Therefore, the inverted output of the ripple carry by the inverter 45 is such that only the valid bit portion of the multiplexed data is 1, and the invalid bit portion (shaded area) is 0. That is, the fifth
-■ shown in the figure -■ writes only valid bits into the memory 51, and prohibits writing of invalid bits.

Therefore, multiplexed data 1 is written into the memory 51 by removing the invalid bit from address 1 using WR shown in FIG. 5-[phase], and from address 1 by RR shown in FIG. As shown in the figure, the multiplexed data in which the invalid bits are removed and the valid bits are front-justified is read out.

Next, FIG. 6 is a block diagram of an embodiment of the different speed separation circuit,
FIG. 7 shows an explanatory diagram of the operation of FIG. 6.

Here, the channel speed setting part 61. Selector 62°R
OM63. Counter 64. The inverter 65 is a component of the second channel speed setting means rate, the memory 71 is a component of the second memory element i, and the CI (1 output cover sofa 81 to CI4
Output buffer 84 represents a component of channel separation means 8. Further, the symbols on the left side of FIG. 7 indicate the waveforms of the portions with the same symbols in FIG. 6, and the shaded portions indicate invalid bit portions. Hereinafter, the operation of FIG. 6 will be explained with reference to FIG. 7, assuming that the input multiplexed data is the same as in the conventional example.

Similarly to the above, when the predetermined speed of each channel is set in the channel speed setting section 61, this data is input to the selector 62, and the setting value for each channel is set by C1.
The selection is made by the selector signal shown in FIG. This selected setting data is converted by the ROM 63 into the initial value of the counter 64 which generates R1, and becomes the initial value of the counter as shown in FIG.

The counter 64 loads the counter initial value shown in FIG. 5-■ for each channel at the load timing shown in FIG. 7-○,
By incrementing with the frame clock and inputting the ripple carry to the BP terminal via the inverter 65, even if this counter overflows, it will not increment until the initial value of the next channel is loaded, and this counter will Continue to output ripple carry 1. Therefore, the read control signal Rr shown in FIG. 7-- is applied to the memory 71.

On the other hand, in the memory 71, the i-th
The multiplexed data shown in Figure-■ is written.

Then, the written multiplexed data is read out by RT,
The valid bits of the 1 part are read out using RR, and the invalid bits of the 0 part are added to separate them in series in rechannel units, resulting in converted data as shown in Figure 7-0. .

This conversion data is input to C111 output buffers (for example, 3-state buffers) 81 to C) I4 output buffers 84 provided for each channel, as shown in FIGS.

The corresponding output buffer is turned on according to the timing of ■ and ■, and the CH as shown in Figure 7-0, 0, 0, [phase]
Data for 2-CH2 is obtained.

In this way, the different speed multiplexing circuit and the different speed separating circuit can arbitrarily set the speed of different speed data for each channel using the channel speed setting parts 41 and 61, respectively, so that it is possible to flexibly change the data speed or change the channel used. can be accommodated.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage of being able to flexibly respond to changes in data rate and channels used.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is an explanatory diagram of the operation of the different speed multiplex circuit in Figure 1, and Figure 3 is a block diagram of the principle of the present invention.
The figure is an explanatory diagram of the operation of the different speed separation circuit in Figure 1, Figure 4 is a block diagram of an embodiment of the present invention of the different speed multiplex circuit, Figure 5 is an explanatory diagram of the operation of Figure 4, and Figure 6 is A block diagram of an embodiment of the present invention of a different speed separation circuit - Fig. 7 is an explanation diagram of the operation of Fig. 6, Fig. 8 is a block diagram of a conventional example of a different speed multiplex circuit, and Fig. 9 is an 8th explanation of the operation. Figure 10 is a block diagram of a conventional example of a different speed separation circuit.
FIG. 1 shows an explanatory diagram of the operation of FIG. In the figure, 3 is a channel data multi-electrification means, 4 is a first channel speed setting means, 5 is a first storage means, 6 is a second channel speed setting means, 7 is a second storage means, and 8 is a channel The means of separation is shown. Honhatsurou's 厘り de σtsu 7 呵冨 1
La gloss O■■■O■O■■■■■◎■◎

Claims (1)

[Claims] Each channel is composed of a predetermined number of bits, and in the channel with the fastest data rate, all bits are valid bits, and as the data rate becomes slower, the number of valid bits in the total bits decreases. When time-division multiplexing data in which invalid bits increase, channel data multiplexing means (3) multiplexes data at different speeds in units of channels, and setting a predetermined data rate in units of channels. , a write control signal (W
A first channel speed setting means (4) that sends out I), and using the output of the first channel speed setting means, only valid bits of the output of the channel data multiplexing means are sequentially written. , and a first storage means (5) from which valid bits, excluding invalid bits, are multiplexed in a front-justified form by being read. 2. By setting a predetermined data rate for each channel when separating multiplexed data in which different speed data is multiplexed in a format in which invalid bits are removed and valid bits are left-justified in each channel, , a second channel speed setting means (6) for transmitting a read control signal (RI) for reading valid bits or prohibiting reading of valid bits for each channel;
and a second storage means (in which the input multiplexed data is written, an invalid bit is added for each channel by the read control signal (RI), and read out as converted data).
7); and channel separation means (8) for separating the converted data into each channel data and outputting the same.