JPH01268068A - Junction type field-effect transistor and video camera using same - Google Patents

Abstract

PURPOSE:To obtain a junction type field-effect transistor characterized by low noises, high resistance against electrostatic breakdown, high performance and high reliability, by forming impurity regions whose concentration is higher than that in a conductive channel region in a partial or whole region in the vicinity directly beneath a source region or a drain region. CONSTITUTION:In a junction type field effect transistor, a source region 9, a drain region 10 and a surface gate region 4 are provided at the surface of a semiconductor layer 2, and semiconductor substrates 1 and 6 are used as substrate gates. In this transistor, impurity regions 7 whose concentration is higher than that of a conductive channel region 5 are formed in the partial or entire region in the vicinity directly beneath the source region 9 or the drain region 10. For example, the N-type epitaxial layer 2 is formed on the P<+> type Si substrate 1 through the P<-> layer 6. The P<+> region 4 is formed at a part of the surface of the epitaxial layer 2 surrounded by a P<+> isolation layer 3 and made to be a surface gate. The high concentration N<+> regions 9 and 10 for a source and a drain contact are formed with said surface gate in between. The N<+> high concentration regions 4 are formed at a part of the P<->layer 6 which is to become a substrate gate region directly; beneath the N<+> regions 9 and 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides low noise and electrostatic breakdown strength suitable for amplifying signals from a signal source with a small output capacity, such as an image sensor of a video camera. The present invention relates to a junction field effect transistor with excellent properties and a video camera using the same.

[Conventional technology]

In conventional devices, as described in Japanese Patent Publication No. 62-28594, a layer of the same concentration as the conductive channel region is formed between the highly doped source region and drain region 2 and the substrate gate region for source and drain contacts.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not consider making the breakdown voltage between the substrate gate and source or drain lower than the breakdown voltage between the surface gate and source or drain. When the distance between the surface gate region and the highly doped source region or the heavily doped drain region is reduced in order to reduce the input capacitance, there is a problem in that the surface gate region is easily destroyed by discharge such as static electricity.

An object of the present invention is to provide a high-performance, highly reliable junction field effect transistor that has low noise and is resistant to electrostatic damage.

Still another object is to provide a high performance video camera device using high performance and highly reliable junction field effect transistors.

[Means to solve the problem]

The above purpose is achieved by forming a region with a higher concentration than the conductive channel region or substrate gate in a part or all of the region directly under the source or drain region, which has a higher concentration than the conductive channel region for ohmic contact. achieved.

[Effect]

A high concentration region formed in a part or all of the region immediately below the high concentration source region or drain region is
The distance between the substrate gate region and the highly doped source or drain region for ohmic contact is reduced to the distance between the surface gate region and the source or drain region. As a result, the breakdown voltage between the substrate gate and the source or drain becomes lower than the breakdown voltage between the surface gate and the source or drain, so gate breakdown due to electrostatic discharge occurs deeper than the surface and on the substrate gate side, which has a larger area. It is possible to prevent thermal damage caused by crystal defects occurring in the region and current concentration in the fine surface gate region. [Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
Figure (a) shows N using a part of the surface and the substrate as a gate.
Channel junction field effect transistor (hereinafter referred to as J-FET)
FIG. 3B is a schematic diagram of a planar pattern of FIG. This J-FET is p+
Epitaxial N layer is formed on the type Si substrate 1 through the P′″ layer 6.
A layer 2 is formed, and a P middle region 4 is formed on a part of the surface of the N-type epitaxial MI2 surrounded by the isolation P+Wj3 to serve as a surface gate. It has a structure in which high concentration N regions 9 and 10 are formed, and a medium high concentration region 7 of N is formed in a portion of the P'''' layer 6 which becomes the substrate gate region immediately below the N ten regions 9 and 10. .

The manufacturing method shown in FIG. 1 will be explained using FIGS. 2(a) to 2(d).

(a) Doped with B (boron) at a high concentration (impurity concentration N
: 1019ato+ms/cj) Llta P 10 type S
A low concentration of B (boron) doped (N: 10
"atoIls/rj) A P-type Si layer 6 is epitaxially grown to a thickness of about several μm. After this, a part of the oxide film 8 on the first surface is removed by photo-etching, and using this as a mask, Sb (antimony) is deposited on P". ``'' diffuses into layer 6, N medium high concentration region 7 (N: 10!9aton+s/-
) wo formation.

(b) Oxidation II! I8 is removed and N-type Si layer 2 (N
: 101017ato/aJ) is formed to a thickness of about 1 μm by epitaxial growth. After that, a 1M film was formed, and after photoetching, B was used as a mask.
Ions are deeply implanted to form an isolation P soil layer 3.

(C) A P region (N: 10"" atoms/cd) 4 is formed by mask diffusion (or ion implantation) on the surface of the N-type Si layer 2 surrounded by the isolation P soil layer 3, and this is formed on the surface. Gate. This surface gate is connected to the isolation P+ layer 3 as shown in FIG. N medium regions 9.degree. 10 for source and drain contacts are formed on the surface of the N layer 2.

Although not shown, a passivation film is then formed on the surface and contact photoetching is performed.

After AQ deposition, patterning is performed to form source and drain electrodes.

The concentration distribution of the source from the surface of the N medium region 9 at this time is shown in FIG. 2(d).

The N+ high concentration region 7 formed directly under the source N1 region 9 has a higher concentration than the N layer 2 of the channel portion 5.

In such a J-FET structure, the P-type Si layer 6
The avalanche breakdown voltage of the junction due to the N medium high concentration region 7 and the P medium concentration region 4 of the surface gate is
and N[2, and when a high voltage is applied between the gate and the source, breakdown occurs on the substrate gate side. This prevents current concentration on the fine surface gate (gate length is about 1 μm), and exhibits stable breakdown characteristics because it is not affected by crystal defects that occur at the interface.
The breaking strength can be increased compared to the case of breaking down with a surface gate.

Note that the P- layer 6 shown in FIG. 1(b) does not necessarily need to be clearly formed; it may be a low-Na layer formed by rising from the P+Si substrate 1 to the N layer 2. However, in this case, the thickness of the N layer 2 is determined in consideration of the amount of rise from the P+Si substrate. In addition, the N medium high concentration region is ion-implanted (impurity Nilin, dose: 3×10”Ql) using a diffusion window for forming the source N+ region and the drain N+ region.
-", implantation energy: 800 KeV).

FIG. 3 shows another embodiment of the present invention. This L element has a structure in which the source N medium region 9 or the drain N medium region 10 reaches the P- layer 6 of the substrate gate region. The same effect as the structure shown in FIG. 1 can be brought about.

The deep source N medium region 9 and drain N medium region 10 of this structure are formed, for example, as follows.

Using an oxide film (approximately 1 μm) and a photoresist film (approximately 2 μm) as masks, P (phosphorous) wo)'-X amount 3 is deposited through a window for forming a high concentration source N middle region 9 or drain N region 10.
X 1018am-”, injection Z*le #-550Ke
Ion implantation is performed with V to form a high concentration region in N at a depth of approximately 0.7 μm from one surface. After this, N medium regions 9 and 10 for source and drain contacts are formed by diffusion, and in the heat treatment process during this diffusion, N medium high concentration regions 7 and source and drain N medium regions 9 and 10 formed by ion implantation are formed. bring into contact with.

FIG. 4 shows another embodiment of the present invention, in which the N shown in FIG.
In place of the medium and high concentration region 7, a P medium and high concentration region 12 is provided.The zero-line P medium and high concentration region 12 is formed by using, for example, an oxide film (approximately 1 μm) and a photoresist film (approximately 2 μm) as a mask to form a high concentration source. N medium region 9 and drain N
B (boron) is added at a dose of 3 from the window for forming region 10.
X10"■-2. It is formed by ion implantation under the conditions of implantation energy of 300 KeV. According to the 0-wire structure, a P ÷ high concentration region can be formed at a depth of approximately 1 μm from the surface. Without changing the width of the channel region (between the front gate region 4 and the substrate gate region 2), the distance between the substrate gate region 2 and the source N middle region 9 can be made smaller than the distance between the front gate region 4 and the source N middle region 9. Since it can be made small, when a high voltage is applied to the gate, it breaks down on the substrate gate region 2 side, making it difficult to be destroyed.

FIG. 5 shows still another embodiment of the present invention, in which one end of the P middle high concentration region shown in the embodiment of FIG. 4 is in contact with the substrate gate region 2, and the other end is in contact with the source N middle region. 9 or has a structure in contact with the middle region of the drain N. According to the present invention, there is an advantage that the breakdown voltage between the substrate gate and the source can be lower than that of the structure shown in FIG.

In the above embodiment, an N-channel J-FET was explained, but it may be a P-channel J-FET, and the present invention can also be applied to a J-FET of a semiconductor integrated circuit device. The shape is not limited to a mesh shape or an overlay shape having the opposite structure, and the same effect can be obtained in either case.

Further, the junction field effect transistor of the present invention obtained as described above is suitable for amplifying a signal from a signal source with a small output capacity, such as an image sensor of a video camera, and can be used to We were able to construct a video camera device with high performance and high reliability.

〔Effect of the invention〕

According to the present invention, the surface gate length is miniaturized to 1 μm or less in order to achieve high gm and low input capacitance, and even if the distance between the surface gate region and the source contact region is shortened, the electrostatic breakdown strength of the gate is increased. High performance and high reliability J-F
Easily realizes ET, improves manufacturing yield, and eases handling during mounting.

This has the effect of improving the reliability of the device itself.

[Brief explanation of the drawing]

FIG. 1(a) is a schematic plan view of a silicon N-channel junction field effect transistor according to an embodiment of the present invention, and FIG. 1(b) is a schematic plan view of a silicon N-channel junction field effect transistor according to an embodiment of the present invention.
is a cross-sectional structural view taken along the line A-A' of the above plan view, and Fig. 2 (a) ~
(d) is a process cross-sectional view for explaining one embodiment of the present invention, and FIGS. 3 to 5 are cross-sectional structural diagrams of silicon N-channel junction field effect transistors according to other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... P+Si substrate, 2... N layer, 3... Isolation region, 4... P middle region, 5... Channel region, 6... P- layer, 7... N Medium-high concentration region, 8.
...Oxide film, 9...Source N10 region, 10...Drain N middle region, 11...(b) 4-.P? Evening @E';, ? ,, Swords Nj4tbeCb) /l・Sidust film/2- Fr Island 1 degree company-wide Pe 2nd mouth (d-) 弗 3 mouth 2/6 4th former 5th Showa

Claims (1)

[Claims] 1. In a junction field effect transistor that has a source region, a drain region, and a surface gate region on the surface of a semiconductor layer and uses a semiconductor substrate as a substrate gate, a part of the area immediately below the source region or the drain region. A junction field effect transistor characterized in that an impurity region having a higher concentration than a conductive channel region is formed in one region or the entire region. 2. A junction field effect transistor characterized in that an impurity region having a higher concentration than the substrate gate is formed in a part or all of the region immediately below the source region or the drain region. 3. A junction field effect transistor characterized in that a source region or a drain region having a higher concentration than a conductive channel region reaches a substrate gate region. 4. One end of a highly doped region of the same conductivity type as the substrate gate region formed in a part or all of the region immediately below the highly doped source or drain region reaches the substrate gate region, and the other end reaches the substrate gate region. A junction field effect transistor characterized in that an end reaches a source region or a drain region that is more highly doped than a conductive channel region of the opposite conductivity type as a substrate gate region. 5. A video camera characterized by using the junction field effect transistor according to claims 1 to 4.