JPH01266739A - Dicing line structure for separation of semiconductor chip - Google Patents

Abstract

PURPOSE:To prevent any crack produced upon dicing and die-bonding from extending to an active region by providing an uppermost stage bank on the outer circumference of the active region and providing a second stage bank on the outer circumference of the resulting uppermost stage bank. CONSTITUTION:An uppermost stage bank 9 located higher than a surface where an active region is located is provided on a device formation region, particularly at least on the outer circumference of said surface of the active region at the end of the same. Around the outer circumference of the uppermost stage bank a bank 10 lower than said bank is formed, and a dicing surface 5b to be cut actually is formed at a further lower stage. Accordingly, when a chip 13 is attracted by an attraction collet 12, the attraction collet 12 and the chip 13 make contact with the end of the uppermost stage bank 9 and with the end of an outermost bank 10 of the second stage bank, and the collet 12 does not not abut the cut end portion in which chipping 8 caused by dicing. Thus, any crack can be prevented from developing further without transmitting external influences produced upon the dicing and die-bonding to the active region.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dicing line structure for separating and cutting semiconductor chips, and more specifically, for separating a plurality of semiconductor chips formed in parallel on a semiconductor wafer into individual dicing lines. This relates to a dicing line structure for cutting and separating semiconductor chips.

[Conventional technology]

FIG. 7 is a sectional view of a conventional dicing line structure for separating semiconductor chips, FIG. 28 is an enlarged partial sectional view of the end of the dicing line in FIG. 1, and FIG. 9 is a perspective view of separated chips. FIG. 10 shows a cross-sectional view of the die-pounded material which is adsorbed by the adsorption collet. @ In Figures 7 and 8, (ll is a semiconductor substrate (semiconductor wafer), [21 is an oxide layer formed at a predetermined position on the surface of the semiconductor substrate fi+,
(3) is a diffusion region that constitutes a part of the element; constitute an element formation region including (5b
) is the dicing line surface, (5a) is an unnecessary alloy layer generated in the intermediate processing of U sea urchin fly, (6a), (6b) is located at both ends of the vl dicing line surface (5b), and is the active area arrangement surface, that is, the concrete The boundary line (8) is in contact with the laminated structure (4), and the chip (8) is a so-called chipping, which occurs at both ends of the chip when it is cut by a cutting blade or when it is cut. In this conventional example, chipping on both chip end sides caused by cutting by the cutting blade +81 +81
The dicing line boundaries (6a) and (6b) are the oxide layer (2), the diffusion region (3), and especially the laminated structure part (4).
Since it is in contact with the same surface, this chipping +81
When +81 becomes large, the chipping edge becomes an oxide layer (
2) or the laminated structure part (4), which may easily cause cracks, etc. In the subsequent assembly process, for example, the 10th
When the suction collet shown in the figure comes into contact with a chipping chip edge and suctions the chip, there is a risk that the chipping and microcracks that originally occurred during cutting may progress to the inside of the chip active area.
The width of the dicing line surface (5b) is designed to be as wide as possible with sufficient margin, and as a result, the effective area of the wafer is inevitably narrowed. Therefore, chip chips caused by suction can be completely sucked up, fall onto the chip surface, or be bitten into the suction collet, causing damage to the suctioned chip or clogging the vacuum nozzle.
have

[Problem to be solved by the invention]

In this way, in the conventional wafer dicing line structure, the dicing line surface is formed on the same plane as the active area stacked structure, so the active area stacked structure is susceptible to chipping caused by the cutting blade during dicing. The development of cracks cannot be prevented, and when chips are adsorbed in the subsequent Guipon process, chips may occur due to chipping, or new chip chips may be created to grasp small parts where racks are occurring. There have been problems such as the inability to prevent cracks from forming or propagating into the active area.

This invention was made in order to improve these conventional problems, and its purpose is to reduce the heat generated by the blade during dicing, the micro cracks that occur at the cut end, and other active factors associated with chipping during dicing. A dicing line structure for separating semiconductor chips that effectively prevents the propagation of cracks to the area stacked structure and also prevents cracks at the chip edge caused by adsorption during die pounding in the subsequent process from propagating to the active area. It provides:

[Means to solve the problem]

The dicing line structure for separating and cutting out semiconductor chips according to the present invention is provided with a top stage machine higher than the active region arrangement surface on the outer periphery of the element forming region, especially at least the end of the active region arrangement surface, and on the outer periphery of the embankment. By surrounding the chip with a lower stage embankment and by forming the dicing surface that is actually cut at an even lower stage, when the adsorption collet adsorbs the chip, the adsorption collet and the chip are connected to the end of the uppermost stage embankment and the top of the second stage. The collet is designed to prevent the collet from hitting the cut end that is in contact with the edge of the outer peripheral embankment and has chipping caused by dicing.

[Effect]

In the dicing line structure of the present invention, a top bank is provided at least on the outer periphery of the active area, and when a chip is sucked by a suction collet with a slope, the chips and the suction collet first hit the outer periphery of the top bank. Since it does not contact the active area, there is no damage to the active area, and if the chip is tilted, it will come into contact with the outer periphery of the second bank provided at the outermost periphery, so the suction collet will not damage the active area. Since the cracks do not come into contact with the areas where the chipping has occurred, the cracks can be prevented from growing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (4) is a laminated structure part that constitutes the element, (6
a) is the element active area boundary line, and (11) is the minimum width 5/! on the outer periphery of the element active area boundary line (6a). The exposed area of the upper surface of the substrate fi+ provided at least m, (9) is the top bank provided on the outer periphery of the substrate exposed area (11), and (10) is the top bank provided on the outer periphery of the top bank (9). In the second stage embankment, (5b) shows the dicing line surface, and (8) shows the chip side surface of the substrate (1) that remains after being cut away by chipping and +71H dicing. Figure 2 is an enlarged sectional view of the stepped dimension at the end of the dicing line in Figure 1, Figure 3 is a perspective view of separated chips, and Figure 4 is a state in which a suction collet (chip α3 separated by +21) is sucked. FIG.

In the figure, in order to absorb errors during photolithography, the dimension of There is a suction area (
By arranging the inner periphery of (9) in the top row, when a load is applied to the chip adsorption area from the outside, even if local crack damage occurs in the adsorption area (9), the crack propagation will be in the active area. This is to prevent it from growing inward from the boundary line (6a). In addition, by providing a second low bank (101) on the outer periphery of the top stage suction @ relative t91, when a chip is suctioned by the suction collet, the stress at the contact area with the collet increases if only the top stage edge a is used. In order to relieve stress, it is provided so that points 8 and b in Fig. 2 are in contact with each other, and to reduce the inclination of the chips to be attracted.Also, the dimensions x2 and Y3 is the dimension X3 of the uppermost plate (9) and (Y2 +
Y3) and the dimensions X2 and Y2 of the second stage embankment (lO) are determined. In addition, the purpose of digging the dicing line surface (5b), which contacts the dicing line surface (5b), the element arrangement surface (Ill, the adsorption collet surface, Irls point, and d point) is to remove chipping c and a from point d. In addition, the X2, Even considering cutting accuracy, blade thickness accuracy 2 positioning accuracy, variation in chipping dimensions, etc., ±10) tm and X2. Since the error is more than 10 times the error in the X3 dimension, the 72 dimension must be made larger, but by digging down the dicing line, the Y2
i can be lowered. In addition, the embankment provided on the outer periphery of the chip according to the present invention increases the rigidity around the chip before and after cutting, protects the active area of the chip, minimizes the propagation of defects to the internal active area, and reduces the heat generated during cutting. It has the effect of a heat sink to dissipate heat, and has the effect of reducing heat transfer to the inside during cutting.

Next, when the chip is sucked by the suction collet during the gripping, the suction collet and the chip come into contact at the predetermined atb point formed with high accuracy as shown in Figure 2, so the tilt of the chip is reduced and the stress caused by the suction collet is reduced. Moa
, it is dispersed at point b and becomes small, and even if it is attracted with a significantly excessive adsorption force, the influence of external force on the active area is separated and minimized because the outer dam is separated from the active area by a dimension of X4. .

In the above embodiment, a suction method in which points a and b touch each other is shown in FIG. It may be adsorbed at three extended points, or it can be designed to be adsorbed at two points, point b and point f, as shown in Figure J5, or at point 81 and point f, as shown in Figure 6. Therefore, the same effects as in the above embodiment can be achieved. Further, in FIG. 2, the point a may be continuous all the way around or intermittently, and similarly the heat sink effect can be obtained even if the point b is continuous all the way around or intermittently. Further, even if a+b in FIG. 2, s and f in FIG. 5, and f and a' in FIG. 6 are configured as gradients, the same effect as in the above embodiment can be obtained.

The dicing line structure according to the present invention includes: (1) making the surface (5b) of the dicing line that is actually cut by the dicing blade for separation on the dicing line the lowest groove bottom; (2) making the surface of the substrate fi+ ( 11) The dicing line surface (5b) U is lower than ■
The first chip adsorption area (10
1, ■ Providing the chip suction area (9) of gIJ2 higher than the first chip suction area (9) inside the gK1 chip suction area [(io+), ■ Providing the second chip suction area (9)
) and the production area (6a) are characterized by separating the second chip adsorption area (9) from the production area (4).

The effects are: (a) Eliminate areas with high local stress by adhering to precisely patterned areas; and (b)
The collet does not come into contact with the edge of the chip where chipping occurs during suction, so the chip does not crack.
The problem is that it eliminates problems such as nozzle clogging due to chips.
[And] By separating the element formation area from the area where external force is applied during chip adsorption and causes displacement, it is possible to reduce the force during dicing and cut heat transfer to the element formation area, and the external force during chip adsorption is extremely small. With this structure, the stress distribution in the chip element formation region can be controlled by selecting the structure and material of the suction region. In this embodiment, the adsorption region has a two-stage embankment, but it is easy to make the adsorption region more multi-stage by dividing the etching process.

Furthermore, it is also possible to easily reduce damage to the corners by forming an alloy layer or an oxide layer on the chip adsorption portion of the adsorption area.

The chip adsorption area can also be constructed by etching the substrate as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, in the conventional dicing line area outside the active area, (1) the substrate surface exposed area;
(2) The top stage machine that forms the suction area, (3) the second stage suction area embankment, (4) the substrate surface area, and (5) the dicing surface is lower than the substrate surface area, so (a) during dicing. Do not transmit the influence of external force to the active area, ←) Do not transmit the external force caused by the suction collet during die pounding to the active area, e
→The energy generated during dicing is not directly transferred to the active area, and the heat is dissipated in the adsorption area, which greatly reduces the amount of transferred heat.2) By providing a bank at the chip edge, the edge rigidity is increased and crack growth is prevented, making it reliable. We can provide high quality chips.

[Brief explanation of the drawing]

1, 5, and 6 are cross-sectional views showing the dicing structure according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view of the details of the dicing line in FIG. 1, and FIG. A perspective view of the chip diced along and separated;
Figure 4 is a cross-sectional view showing the state in which the chip is attracted by a suction collet, Figure 7 is a cross-sectional view showing the conventional dicing line structure, and Figure 8 is an enlarged view of the relationship between the dicing line and the active area of Figure 7. Cross section! FIG. 9 is a perspective view of a chip separated along a conventional dicing line, and FIG. 10 is a cross-sectional view of the chip when it is attracted by a suction collet. In the figure, 10 is the substrate, (2) is the oxide layer, (31 is the diffusion region, (4) is the stacked structure part, (5b) is the dicing line surface, (6B) is the active area boundary line, (7) is the chip side surface, (8) is chipping, (9) is the first adsorption area V,
, (the top stage machine χ(10) is the second adsorption area (second stage embankment)
, (Ill shows the exposed area of the substrate fi+, (12) shows the suction collet, and Q3 shows the separated chip. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a dicing line structure for individually cutting and separating a plurality of semiconductor chips formed on a semiconductor wafer, a chip adsorption area is arranged on the substrate surface over the entire outer periphery of the element formation area, with the substrate surface exposed area being separated. Separation of semiconductor chips, characterized in that the outer peripheral area is surrounded by a chip adsorption area with a low level difference, and the surface to be actually diced is dug down from the surface of the substrate by etching etc. so that it is at the lowest level. Dicing line structure for separation.