JP2005294842A - Semiconductor package having step type die and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package having a step type die. <P>SOLUTION: A semiconductor die has a maximum width W<SB>0</SB>, a maximum length L<SB>0</SB>, and a first recessed part R<SB>I</SB>, wherein W<SB>0</SB>is reduced by a first recessed depth D<SB>rla</SB>to form a width W<SB>la</SB>of a first minor axis and L<SB>0</SB>is reduced by a first recessed length L<SB>rla</SB>to form a length L<SB>la</SB>of the first minor axis. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit chip and a packaging assembly using the semiconductor integrated circuit chip. More specifically, the present invention relates to an integrated circuit chip or die having a deformed rectangular outer peripheral surface and a related chip embodied by using one or more thereof. Or relates to a multi-chip package.

   In general, the manufacturing process of a semiconductor package can be roughly divided into three processes such as semiconductor wafer processing, package assembly, and testing. The wafer processing process includes all processes necessary for forming a plurality of integrated circuit elements in or on a bare semiconductor wafer or substrate, such as heat treatment, ion implantation, vapor deposition, planarization, photolithography and etching.

  When the process is completed, the process proceeds to a wafer dicing process after performing parameter and / or function tests. During this process, the backside of the semiconductor wafer is polished to reduce the thickness and separated into individual integrated circuit chips along the cutting line. For this reason, the wafer dicing process is also referred to as, for example, a wafer sawing or wafer scribing process.

  Once the individual integrated circuit chips are separated from the wafer, a package assembly process is performed in which each individual integrated circuit chip is attached to a substrate such as a lead frame. The substrate is connected to the integrated circuit chip, the circuit substrate, or the socket. Including an external connection structure. By forming a sealing part that directly seals the circuit chip, part of the substrate, and the electrical connection between the chip and the substrate, and increases the resistance of the package, from external mechanical damage and contamination Protect. The package includes one or more integrated circuit chips. However, in the case of a multi-chip package, the package may include substantially the same chip or may include chips having various functions and sizes. For example, a multi-chip package is configured to include both a microprocessor integrated circuit chip and a memory chip connected thereto in one package.

  Currently, most of the semiconductor chips have a rectangular shape as shown in FIG. 1, which is derived from a conventional wafer dicing method. A conventional general wafer dicing apparatus moves along a cutting line S between a plurality of semiconductor chips 12 formed on a wafer 10 using a dicing blade 14. Since the cutting length of the dicing blade 14 is substantially the same as the surface length of the integrated circuit chip 12, the conventional dicing apparatus can cut only a simple and constant rectangle. For example, a triangular or parallelogram shape is used. There wasn't.

  In addition, in order to solve the problem of chipping that causes a decrease in yield and / or reliability due to the use of a conventional dicing blade, a dicing method using laser scribing is disclosed in US Patent Application No. 10/805, No. 212 is disclosed. Further, a Mahoh dicing machine, which is a laser scribing device of Tokyo Seimitsu Co., Ltd., dices a semiconductor wafer using a non-contact method that reduces damage to the wafer surface due to conventional sawing. Various types of integrated circuit chips are cut by irradiating the surface of a semiconductor wafer with a laser beam of a laser die. This can reduce damage such as chipping that occurs when a part of the wafer is removed by the abrasive in the conventional sawing method.

  The rectangle of the integrated circuit chip limits the form of the semiconductor package to be implemented, so that the package is also predominantly rectangular. For this reason, when a plurality of packages are mounted on the same substrate as the circuit board, the packaging density of the package is reduced and the size of the board necessary for mounting the integrated circuit chip is increased.

  Further, it is difficult to make the rectangular shape of the integrated circuit chip into a small and thin shape of the multichip package. For example, when two integrated circuit chips are stacked, if the size of the upper chip is sufficient to cover the bond pad of the lower chip, a space is interposed between the integrated circuit chips and is accessible to the bond pad of the lower chip. Must be made. However, as shown in FIG. 3A, the thickness of the multilayer chip increases to S2 due to the spacer.

  As one method for solving the interference between the upper and lower chips, as shown in FIG. 3B, the lower surface end portion of the upper chip is removed, and a five-eye type opening that can be bonded to the bond pad of the lower chip is opened. There is a method of forming a part. However, in this method, since a part of the upper chip is thinned, there is a possibility that a weakened part is broken or a crack is generated at the time of wire bonding.

  As one method of covering the bond pads of the lower chip, there is a method in which the upper chip is rotated with respect to the lower chip and mounted diagonally, and the wire bonding area is exposed on the lower chip. This method has the limitation that chips of different sizes and orientations must be used to improve accessibility to the bond pads of the lower chip, although some of the chips are not at risk of mechanical damage, There was a problem that the device and / or control device had to be used for the offset arrangement.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit chip having various forms other than a rectangular outer peripheral surface having one or more recesses, and to provide a chip and a multichip package embodied therein.

To achieve the above object, the present invention provides a semiconductor die having a modified rectangular outer periphery including the maximum width W ₀ and the maximum length L _0. Are recesses formed to the corner along one side, is reduced from the original width in the first concave portion depth D _r1a to form a first portion lateral width W _la, first the original length L ₀ 1 The first part length L _1a is formed by being reduced to the recess length L _r1a . In the integrated circuit chip according to the present invention, the partial end portion and the size are formed according to the number, size and position of the recesses. The recesses may be arranged asymmetrically with respect to the rectangular basic structure, or may be arranged symmetrically with respect to the vertical (center vertical axis), horizontal (center horizontal axis), or diagonal axis.

  The method of manufacturing an integrated circuit chip having an outer peripheral surface as described above according to the present invention includes the step of forming a plurality of dies having recesses on a semiconductor wafer and then separating the individual dies from the wafer. The step of separating into individual dies includes the step of laser scribing the outer peripheral surface of the die to form a fragile portion on the wafer and then separating the individual dies from adjacent dies along the fragile portion. In yet another embodiment, the step of separating into individual dies includes removing the upper portion of the wafer located near the recess at the end of the outer peripheral surface of the die and forming an opening in the active surface of the wafer, opposite to the active surface. And removing the remaining part of the wafer along the cutting line between the dies.

The dies having recesses according to the present invention can be arranged in various structures on a semiconductor wafer.
For example, the recesses of the at least two dies can be complementary to each other or can be arranged at a substantially constant distance along the outer peripheral surface. Alternatively, the recesses in the at least two dies may not be complementary to each other and may be spaced from different points along the adjacent portion of the outer peripheral surface of the die to substantially different distances.

  Since not only the deformed outer peripheral surface form formed on the integrated circuit chip but also the structure of the bond pad can be modified, the bond pad can be prevented from being formed on the outer peripheral surface near the recess as shown in the embodiment. The bond pads may be arranged in a substantially vertical line along the outer peripheral surface.

  The present invention provides a multi-chip package including an integrated circuit chip having the above-described recess. That is, the package includes a substrate having a contact portion and a first semiconductor die having a recess formed on the outer peripheral surface, and the first semiconductor die is mounted on the substrate so that the contact portion is exposed through the recess. . In a package according to another embodiment, the lower semiconductor die serves as a substrate and includes a contact having at least one bond pad and a plurality of bond pads formed on the active surface of the first semiconductor die. A package according to another embodiment includes a substrate having a contact surface and a first semiconductor die having a recess formed on the outer peripheral surface, and the first semiconductor die is disposed on the substrate such that the contact portion is exposed through the recess. Implemented.

  The present invention also provides a method of manufacturing the aforementioned package. A step of preparing a substrate; a step of mounting a first semiconductor die having a plurality of first bond pads on the substrate; and a step of forming a second semiconductor die having a first recess formed on an outer peripheral surface; Mounting a second semiconductor die on the first semiconductor die such that the plurality of first bond pads are exposed through the first recess. The package manufacturing method includes forming a third semiconductor element having a second recess formed on an outer peripheral surface, and exposing a plurality of second bond pads formed on an active surface of the second semiconductor element through the second recess. The method may further include mounting a third semiconductor die on the second semiconductor die. The package manufacturing method includes electrically connecting the first bond pad and the second bond pad to the substrate and / or electrically connecting the plurality of third bond pads formed on the active surface of the third semiconductor die to the substrate. The method may further include connecting to the.

  According to an embodiment of the present invention, a method of manufacturing a package includes preparing a first semiconductor die, a second semiconductor die, and a third semiconductor die with substantially the same structure, and forming the second semiconductor die with the first semiconductor die and the third semiconductor die. And a die assembly stage that is rotated about 180 ° relative to the semiconductor die. The package manufacturing method includes providing a first semiconductor die, a second semiconductor die, and a third semiconductor die having substantially the same structure, and the second semiconductor die is about 90 relative to the first semiconductor die and the third semiconductor die. ° rotating die assembly stage.

  In the package structure according to the embodiment of the present invention, the first semiconductor die having a recess on the outer peripheral surface and mounted on the substrate, and the second semiconductor die mounted horizontally with respect to the first semiconductor die, The second semiconductor die is located in the recess. In the integrated circuit chip structure according to the embodiment of the present invention, the second semiconductor die is substantially located in the recess or completely located in the recess.

  The present invention can reduce the surface area by using an integrated circuit chip having various outer peripheral surfaces and bond pad structures, and can improve the mounting density on a substrate or a circuit board.

  Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

  FIG. 4 is a diagram showing a multi-chip package 40 according to an embodiment of the present invention. A conventional rectangular first integrated circuit chip 12 and a second integrated circuit chip 50 having an outer portion modified in the present invention are formed on a substrate 41. It has the structure mounted in. The substrate 41 has an external connection structure such as a solder ball 44 for connecting the integrated circuit chip, the circuit substrate, the socket, and other fixtures.

  As shown in FIG. 5, the integrated circuit chip according to the present invention has one or more recesses R1. . . Rn is formed and is different from the conventional integrated circuit chip. The recess has end portions RD1 and RL1 formed in parallel with the outer peripheral surface. The at least one recess may be formed in at least one end, and may be implemented in an L shape by intersecting adjacent recesses. The arrangement and direction of the integrated circuit chip and the recess are based on the diagonal axes D1 and D2 and the parallel line axes V and H, and are arranged symmetrically with respect to one or more axes.

  As shown in FIGS. 6 and 7, the multi-chip stacked package 90 includes a substrate 91 on which a plurality of leads or conductive patterns are formed around the chip mounting region. The plurality of integrated circuit chips 80a, 80b, and 80c are sequentially stacked on the chip mounting region of the substrate. Each integrated circuit chip is formed with a pair of recesses 82a, 82b, 82c on both sides of one end. A plurality of bond pads 88a, 88b, 88c are formed on both sides of the other end of the integrated circuit chip while maintaining the original width, and the integrated circuit chip and the lead 92 are connected to bonding wires 93, 94, 95. . The integrated circuit chips 80a, 80b, and 80c are attached to the substrate using the adhesive layer 97. At this time, the integrated circuit chips 80b and 80c attached to the upper part are mounted by rotating 180 ° with respect to the lower chip. it can. When the concave portion of the upper chip and the peripheral region of the lower chip are continuously arranged in this manner, an opening larger than the thickness of the integrated circuit chip is formed, and the bonding wire 93 is connected to the bond pad 85a of the lower chip. Can be attached.

  As shown in FIG. 8, when one recess 32 is formed in the integrated circuit chip 30 having the side surfaces 36 and 37 orthogonal to each other, at least two outer peripheries reduced to the length of the recess ends 36 ″ and 37 ″. Surfaces 36 'and 37' are born. The shape of the integrated circuit chip 30 varies depending on the size and arrangement of the recesses. However, when the recesses surround the corners, the integrated circuit chip 30 is embodied in an L shape and is not illustrated in FIG. When formed on one surface of the circuit chip, it is embodied in a C shape.

  When one or more recesses are formed, various outer peripheral surfaces are embodied in the integrated circuit chip as shown in FIGS. As shown in FIG. 5, according to the size and arrangement of the recesses, the outer peripheral surface of the integrated circuit chip is symmetric with respect to one or more diagonal axes and / or parallel axis. For example, the outer peripheral surface of (a) is symmetrical with respect to the axis (V), and the outer peripheral surface of (b) is symmetrical with respect to the two axes (V, H). The outer peripheral surface is symmetrical with respect to four axes (D1, D2, V, H).

  As shown in FIG. 10, a plurality of integrated circuit chips 30 having steps are arranged in a repetitive pattern on a semiconductor wafer. That is, after the integrated circuit chips are arranged in the same direction, they are separated by scribing, particularly laser scribing, along the cutting lines 26a, 26b, and 26c. The cut portion 31 is removed and a recess is formed in the integrated circuit chip 30. The cut portion 31 is not included in the individual semiconductor element, and this portion is generally called scrap.

  As shown in FIG. 11, two or more integrated circuit chips having recesses are gathered to form a rectangular unit 30a. Such an arrangement can be performed repeatedly on the surface of the semiconductor wafer and can be reduced to scrap by separating into individual integrated circuit chips along the cutting lines 80a, 80b, 80c, and thus required manufacturing per device. Costs can be reduced.

  FIG. 12 is a diagram showing a multi-chip package 70 according to an embodiment of the present invention. A conventional rectangular first integrated circuit chip 12 and a second integrated circuit chip 50 having an outer peripheral surface according to the present invention are mounted horizontally on a substrate 71. Is the structure. The substrate 71 includes an external connection structure such as a solder ball 74 for connecting the integrated circuit chip, the circuit substrate, the socket, and the fixture.

  FIG. 13 is a view showing a single chip package 60 according to an embodiment of the present invention, and has a structure including one integrated circuit chip 50 having a deformed outer peripheral surface. The integrated circuit chip 50 is mounted on a substrate 61, and the substrate 61 has an external connection structure such as a solder ball 64 that connects the integrated circuit chip, the circuit substrate, the socket, and the fixture. As shown in FIGS. 12 and 13, the implemented semiconductor device package also has an outer peripheral surface corresponding to the structure of the chip, so the outer peripheral surface is not rectangular.

  As shown in FIG. 14, the present invention not only forms the recesses in the integrated circuit chip to deform the outer peripheral surface, but also changes the arrangement of the bond pads in consideration of the arrangement and connection means of adjacent integrated circuit chips. Can do. As shown in FIG. 14, the multichip package 70 has a structure in which the rectangular integrated circuit chip 12 and the modified integrated circuit chip 50 are horizontally mounted. However, the integrated circuit chips 12, 50 and the bond pads 72, 72 a, 75, 75 a of the substrate 71 are not uniformly arranged along the end portions and / or the vertical axis, but are slightly asymmetrical than the conventional case. It is arranged. In particular, the bond pad is not formed along the end 52 of the recess in the integrated circuit chip 50, and the space formed by the recess of the integrated circuit chip 50 is adjacent to the outside of the substrate 71 in the rectangular integrated circuit chip 12. An internal bond pad 75a is formed on a part of the end that is not formed. The bond pads of the integrated circuit chip and the bond pads of the substrate are connected to bonding wires 73 and 73a.

  As shown in FIGS. 15A and 15B, a multi-chip package 70b according to still another embodiment of the present invention has a structure in which the bond pad of the integrated circuit chip is not formed along the end 52 of the recess.

  FIG. 15B is a cross-sectional view taken along the line 15b′-15b ′ of FIG. 15A, in which the integrated circuit chip 12 is flip-chip bonded to the substrate and formed on the active surface of the integrated circuit chip. These bond pads are directly connected by conductive structures such as solder balls and solder bumps. Therefore, it is not necessary to use the bonding wire 73.

  FIG. 16 shows a structure in which a multi-chip package furnace and integrated circuit chips 12a, 12b, 12c, 50 are flip-chip bonded to a substrate 71 according to still another embodiment of the present invention. This eliminates the need for bonding wires, improves the mounting density of the integrated circuit chip with respect to the substrate, and facilitates attachment. Further, since the integrated circuit chips having different forms can be arranged on the substrate surface in a complete form, the mounting density can be increased.

  FIG. 17 relates to still another embodiment of the present invention, in which the integrated circuit chip 12 is disposed in an internal space formed between the multi-chip package furnace and the recesses 52a and 52b of the integrated circuit chips 12, 50a and 50b. Shows the structure. Since each integrated circuit chip is flip-chip bonded to the substrate, wire bonding is not required, which improves the mounting density of the integrated circuit chip on the substrate and allows easy mounting.

  As shown in FIG. 18, the integrated circuit chip 50 according to the embodiment of the present invention includes a structure including chip end portions 57 and 56, corner portions 51, and recessed end portions 54 a in which bond pads 54 and 54 a are regularly arranged. It is. FIG. 19 shows still another embodiment of the integrated circuit chip 50, in which the bond pad is formed only at the chip end and not at the recessed end 54a. For example, as in the multi-chip structure of FIG. 17, other integrated circuit chips can be arranged by a space formed between the recesses, which is useful for such a structure.

  20A and 20B show a structure in which a plurality of integrated circuit chips 80 having an outer peripheral surface 88 including a peripheral region 88 ′ and a recessed region 88 ″ in which bond pads are formed are arranged. As shown in FIG. 20B, the mounting density can be increased while reducing the open area and scrap by changing the direction of the integrated circuit chip on the substrate. However, it is better to leave the semiconductor wafer portion that cannot be implemented by the integrated circuit chip as it is. That is, this part is necessary to create a test plug structure for performing parameter and function tests when using a new manufacturing process, production line or new equipment. Since such a test structure can analyze capacitors, resistors, transistors, and arrangement structures, it is possible to understand the quality and effective size of important functional configurations.

  FIG. 21 is a diagram showing an individual integrated circuit chip 80 obtained through a separation step from the integrated circuit chip of FIGS. 20A and 20B. As shown in FIGS. 20A and 20B, two recessed regions 82 are formed on both sides of the first stage of the integrated circuit chip 80, and a peripheral region 88 having a surface 86 is formed on both sides of the second stage. . The peripheral area 88 and the recessed area 82 have a shape surrounding the internal functional area including the memory, logic and / or input / output circuit necessary for the device to function properly, that is, the cell area 83. The peripheral area of the chip includes left and right upper end areas 89 and 87 that become corners 84 and 81.

  As shown in FIG. 22, according to an integrated circuit chip 180a of still another embodiment of the present invention, a peripheral region 188a ′ in which a bond pad 185a is formed and a recessed region that forms one side surface 188a of the chip together with the peripheral region. It has one recess 182a including 188a ''. As shown in FIG. 23, the multi-chip package 190 according to the embodiment of the present invention has a structure in which a second integrated circuit chip 180b is stacked on the first integrated circuit chip 180a of FIG. The second integrated circuit chip 180b includes a peripheral region 188b 'opposite to the first integrated circuit chip and a recessed end 188b ". That is, when the second chip 180b is stacked on the first chip 180a, or vice versa, the concave region of the upper chip exposes the bond pad 185b of the lower chip, thereby connecting the chip and the substrate. Bond pads 185a, 185b formed in a row are provided.

  As shown in FIG. 24, an integrated circuit chip 280a according to still another embodiment of the present invention has two recesses 282a and 288a formed on both sides of the chip, and one recess 288a has a bond pad formed thereon. It includes a peripheral region 288a ′ and a recessed region 299a ″. As shown in FIG. 25, the multi-chip package 290 according to the embodiment of the present invention has a structure in which a second integrated circuit chip 280b is stacked on the first integrated circuit chip 280a of FIG. The second integrated circuit chip 280b includes a peripheral region 288b 'and a recessed region 288b' 'opposite to the first integrated circuit chip 280a. That is, when the second chip 280b is stacked on the first chip 280a, or vice versa, the recessed area of the upper chip exposes the bond pad 286b of the lower chip. Accordingly, bond pads 285a and 285b formed in both rows when the chip and the substrate are connected are provided.

  As shown in FIG. 26, an integrated circuit chip 290 according to still another embodiment of the present invention has a pair of recesses 382a and 388a formed at chip diagonal angles, and one recess 388a is formed with a bond pad. Peripheral region 388a ′ and recessed region 388a ″. As shown in FIG. 27, the multi-chip package 390 according to the embodiment of the present invention has a structure in which the second integrated circuit chip 290 is stacked on the first integrated circuit chip 290 of FIG. As shown in FIG. 27, the second chip includes a peripheral region 388 b ′ and a recessed region 388 b ″ opposite to the first chip. As a result, when the second chip is stacked on the first chip or vice versa, the recessed area of the upper chip exposes the bond pad 385b of the lower chip, thereby connecting the chip and the substrate at the end. Bond pads 385a, 385b formed along the same are provided.

  As shown in FIG. 28, an integrated circuit chip 480a according to another embodiment of the present invention has a recess 482a formed in the middle of the chip end, and one recess 488a '' is formed by a bond pad 485a. Peripheral region 488a 'and a recessed region 488a' 'formed between adjacent peripheral regions. As shown in FIG. 29, a multi-chip package 490 according to an embodiment of the present invention includes a first integrated circuit chip 480a of FIG. 28 and a second integrated circuit including a recess 488a complementary to the first integrated circuit chip 480a. The circuit chip 480b is stacked. That is, when the second chip is stacked on the first chip, the recessed area of the upper chip exposes the bond pad 485b of the lower chip. Accordingly, bond pads 485a and 485b formed along the end portion when the chip and the substrate are connected are provided.

  30 to 32, the chip stack structures 590, 690, and 790 are implemented using integrated circuit chips having various outer peripheral surfaces having different sizes and shapes, so that the bond pads of the lower chip are connected to the upper chip. Can be exposed in accordance with the size and position of the upper chip, and can be disposed corresponding to the recess of the upper chip. Therefore, the bond pad of the lower chip can be exposed without adding an additional process such as adding a spacer or etching the back surface.

  An integrated circuit chip according to an embodiment of the present invention has a structure including a cell region in which logic and / or memory circuits are formed, and one or more peripheral regions in which input / output circuits and / or input / output pads are formed. A recess is formed adjacent to the cell region and / or the peripheral region of the integrated circuit chip. Integrated circuit chips and chip stack structures according to embodiments of the present invention can be connected to one or more substrates using connection methods such as wire bonding and / or flip chip bonding. Then, it can be sealed with a resin sealing material such as an epoxy molding compound to protect the integrated circuit chip, wire bonding, and inner leads from contamination, side effects, or mechanical damage.

  In addition to wire bonding, flip chip bonding and / or TAB methods, which are the connection methods disclosed in the present specification, various methods can be used. As a substrate, a lead frame, a printed circuit board, a flexible circuit board, Various substrates other than the ceramic substrate can be used.

  As described above, the integrated circuit chip having various outer peripheral surfaces and bond pad structures according to the embodiment of the present invention can be used together with the substrate and / or the package. Further, since it can be adapted to various elements and the like, the surface area to be discarded can be reduced, and the mounting density on the substrate or the second circuit substrate can be improved. The mounting density can be improved at the element level for the multi-chip package or at a higher level such as a mother board or module board on which the package is mounted. Furthermore, the size of the substrate can be reduced by improving the packaging density of the package at the substrate level.

  It should be noted that the embodiments of the present invention disclosed in this specification and the drawings are merely provided as specific examples for helping understanding, and do not limit the scope of the present invention. It will be apparent to those skilled in the art to which the present invention pertains that other variations can be implemented based on the technical concept of the present invention in addition to the embodiments disclosed herein.

It is a perspective view which shows the wafer dicing method of a prior art. It is a figure which shows the laser wafer dicing method. It is a figure which shows embodiment of the laminated chip package of a prior art. It is a figure which shows embodiment of the laminated chip package of a prior art. It is a figure which shows embodiment of this invention. FIG. 4 shows an embodiment of the present invention having a representative size and axis. FIG. 4 shows an embodiment of the present invention having a representative size and axis. It is a figure which shows the assembly of the multichip package in embodiment of this invention. FIG. 7 is a partial cross-sectional view of the multichip package of FIG. 6. It is a top view which shows the integrated circuit chip of this invention. It is a figure which shows the various outer peripheral surface form (a)-(k) which can implement the integrated circuit chip of this invention. FIG. 9 is a diagram showing an arrangement direction in which a plurality of integrated circuit chips of FIG. 8 are arranged on a semiconductor wafer. FIG. 9 is a diagram showing an arrangement direction in which a plurality of integrated circuit chips of FIG. 8 are arranged on a semiconductor wafer. It is a perspective view which shows embodiment of this invention. It is a perspective view which shows embodiment of this invention. It is a top view which shows the multichip package in embodiment of this invention. It is a top view which shows the multichip package in embodiment of this invention. It is sectional drawing which shows the multichip package in embodiment of this invention. It is a top view which shows the multichip package in further another embodiment of this invention. It is a top view which shows the multichip package in further another embodiment of this invention. It is a top view which shows the integrated circuit chip in other embodiment of this invention. It is a top view which shows the integrated circuit chip in other embodiment of this invention. It is a top view which shows the arrangement | sequence of the integrated circuit chip formed in the semiconductor wafer of this invention. It is a top view which shows the arrangement | sequence of the integrated circuit chip formed in the semiconductor wafer of this invention. It is a top view which shows the arrangement | sequence of the integrated circuit chip formed in the semiconductor wafer of this invention. It is a top view which shows the integrated circuit chip in embodiment of this invention. It is a top view which shows the arrangement | sequence of the integrated circuit chip of the chip | tip lamination | stacking in embodiment of this invention. It is a top view which shows the integrated circuit chip in embodiment of this invention. It is a top view which shows the arrangement | sequence of the integrated circuit chip of the chip | tip lamination | stacking in embodiment of this invention. It is a top view which shows the integrated circuit chip in embodiment of this invention. 1 is a plan view showing a multi-chip stacked package implemented from an integrated circuit chip according to an embodiment of the present invention. It is a top view which shows the integrated circuit chip in embodiment of this invention. 1 is a plan view illustrating a multi-chip stacked package implemented from an integrated circuit chip according to an embodiment of the present invention. It is a top view which shows the multichip laminated package in embodiment of this invention. It is a top view which shows the multichip laminated package in embodiment of this invention. It is a top view which shows the multichip laminated package in embodiment of this invention.

Explanation of symbols

40 Multi-chip package 41 Substrate 82a, 82b, 82c Recess 182a Recess 282a, 288a Recess 382a, 388a Recess 482a, 488a Recess

Claims (34)

In a semiconductor die having a deformed rectangular perimeter,
Maximum width W ₀ ,
Maximum length L ₀ ,
A first recess,
In W ₀ , the first recess depth D _{rla is} reduced to form a first minor axis width W _la , and in L ₀ , the first recess length L _{rla is} reduced to form a first minor axis length L _la. A semiconductor die characterized by that. A second recess,
The second recess depth DR _{r2a is} reduced at W ₀ to form a second width W _2a , and the second recess length L _{r2a is} reduced at L ₀ to form a second length L _2a. A semiconductor die according to claim 1. An even number of N recesses;
In the W ₀ , the Nth width W _Na is formed by reducing the Nth recess depth D _rNa , and the L ₀ is reduced by the Nth recess length L _rNa to form the Nth length L _Na. The semiconductor die according to claim 2.   4. The semiconductor die according to claim 3, wherein the N recesses are arranged symmetrically with respect to a central longitudinal axis.   4. The semiconductor die according to claim 3, wherein the N recesses are arranged symmetrically with respect to a central horizontal axis.   6. The semiconductor die according to claim 5, wherein the N recesses are arranged symmetrically with respect to a central longitudinal axis.   4. The semiconductor die according to claim 3, wherein the N recesses are arranged symmetrically with respect to the first diagonal axis.   The semiconductor die of claim 1, wherein the recess surrounds a corner of the semiconductor die.   The semiconductor die according to claim 1, wherein the recess is formed at an intermediate point along the first surface of the semiconductor die.   3. The semiconductor die according to claim 2, wherein the first recess and the second recess engage with each other and surround one corner of the semiconductor die.   The semiconductor die of claim 2, wherein the first recess and the second recess are separated from each other by a peripheral region of the semiconductor die. The first recess surrounds a first corner of the semiconductor die;
The semiconductor die according to claim 2, wherein the second recess surrounds a second corner different from the first corner of the semiconductor die.   The semiconductor die of claim 12, wherein the first corner and the second corner face a diagonal line.   The semiconductor die according to claim 12, wherein the first corner and the second corner are located at both ends of one surface of the semiconductor die. Forming a plurality of dies having recesses on the outer periphery on a semiconductor wafer;
Separating the individual dies in the wafer. The separating step includes laser scribing the outer peripheral surface of the die to form a fragile portion on the wafer;
Separating individual dies from adjacent dies along the fragile portion;
The method of manufacturing a semiconductor device according to claim 15, comprising: The separating step includes removing an upper portion of the wafer adjacent to the recess outside the outer peripheral surface of the die to form an opening in the active surface of the wafer;
Removing the lower portion of the wafer on the opposite side of the active surface, so that the upper and lower portions are at least the same as the original thickness of the wafer;
Removing the remaining portion of the wafer along a cutting line between dies;
The method of manufacturing a semiconductor device according to claim 15, comprising:   Forming the plurality of dies on the semiconductor wafer includes arranging the dies so that the recesses of at least two adjacent dies are complementary to each other and spaced apart along the outer peripheral surface of the dies. The method of manufacturing a semiconductor device according to claim 15, wherein:   The step of forming a plurality of dies on the semiconductor wafer is such that the recesses of at least two adjacent dies are not completely complementary to each other but are spaced apart from each other at different intervals along the adjacent portion of the outer peripheral surface of the die. 16. The method of manufacturing a semiconductor device according to claim 15, further comprising the step of arranging dies on the substrate.   The step of forming a plurality of dies on the semiconductor wafer is a step of arranging a plurality of bond pads adjacent to the outer peripheral surface of the die so that a bond pad is not formed on a part of the outer peripheral surface of the die that forms a boundary with the recess. The method of manufacturing a semiconductor device according to claim 15, comprising:   21. The method of manufacturing a semiconductor device according to claim 20, wherein the plurality of bond pads are arranged along a straight line on the outer peripheral surface of the die. A substrate having a contact portion;
A first semiconductor die having a recess on an outer peripheral surface;
In a semiconductor device package comprising:
A semiconductor device package, wherein a first semiconductor die is mounted on the substrate such that the contact portion is exposed through a recess. The substrate is a lower semiconductor die, and the contact portion comprises at least one bond pad;
The semiconductor device package of claim 22, wherein a plurality of bond pads are formed on an active surface of the first semiconductor die.   24. The semiconductor device package of claim 23, wherein the bond pad formed on the active surface of the first semiconductor die is located only in the extension region. A substrate having a contact surface;
A first semiconductor die having a recess formed on the outer peripheral surface;
In a semiconductor device package comprising:
23. The semiconductor device package of claim 22, wherein a first semiconductor die is mounted on the substrate such that the contact portion is exposed through a recess. Preparing a substrate;
Mounting a first semiconductor die having a plurality of first bond pads on the substrate;
Forming a second semiconductor die having a first recess formed on an outer peripheral surface;
Mounting the second semiconductor die on the first semiconductor die such that the plurality of first bond pads are exposed through the first recess;
A method of manufacturing a semiconductor device package, comprising: Forming a third semiconductor element in which the second recess is deformed on the deformed rectangular outer peripheral surface;
Mounting the third semiconductor die on the second semiconductor die such that a plurality of second bond pads formed on the active surface of the second semiconductor element are exposed through the second recess;
A method of manufacturing a semiconductor device package, further comprising:   28. The method of claim 27, further comprising electrically connecting the first bond pad, the second bond pad, and the substrate.   30. The method of claim 28, further comprising electrically connecting a plurality of third bond pads formed on the active surface of the third semiconductor die to the substrate.   The first semiconductor die, the second semiconductor die, and the third semiconductor die have substantially the same structure, and the second semiconductor die is about 180 ° with respect to the first semiconductor die and the third semiconductor die. 30. The method of manufacturing a semiconductor device package according to claim 29, wherein the semiconductor device package is rotated.   The first semiconductor die, the second semiconductor die, and the third semiconductor die have substantially the same structure, and the second semiconductor die is about 90 ° with respect to the first semiconductor die and the third semiconductor die. 30. The method of manufacturing a semiconductor device package according to claim 29, wherein the semiconductor device package is rotated. In a semiconductor device package comprising at least two semiconductor dies,
A recess formed in the outer peripheral surface, and a first semiconductor die mounted on the substrate;
A second semiconductor die mounted horizontally with the first semiconductor die so as to be located in the recess;
A semiconductor device package comprising:   The semiconductor device of claim 32, wherein the second semiconductor die is substantially located in the recess. 33. The semiconductor device of claim 32, wherein the second semiconductor die is completely located in the recess.

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