JP3832170B2 - Multi-bare chip assembly - Google Patents

Multi-bare chip assembly Download PDF

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JP3832170B2
JP3832170B2 JP2000000934A JP2000000934A JP3832170B2 JP 3832170 B2 JP3832170 B2 JP 3832170B2 JP 2000000934 A JP2000000934 A JP 2000000934A JP 2000000934 A JP2000000934 A JP 2000000934A JP 3832170 B2 JP3832170 B2 JP 3832170B2
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chip
semiconductor
stacked
semiconductor chips
terminals
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JP2001196526A (en
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健嗣 和田
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Seiko Epson Corp
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Seiko Epson Corp
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Description

【０００１】
【発明の属する技術分野】
本発明はマルチチップパッケージ、半導体装置、ならびに電子機器に係り、半導体チップを３次元実装した構成のマルチチップパッケージ、半導体装置、ならびに電子機器に関する。
【０００２】
【従来の技術】
近年、電子機器の高性能化、小型化に伴って１つのパッケージ内に複数の半導体チップを配置してマルチベアチップ実装体を構成し、これを基板に実装しあるいは樹脂封止することによってマルチチップパッケージ(Multi Chip Package)とすることにより、半導体装置の高機能化と小型化とが図られている。そして、マルチチップパッケージには、複数の半導体チップを平面的に並べたものと、複数の半導体チップを厚み方向に積層したものとがある。半導体チップを平面的に並べたマルチチップパッケージは、広い実装面積を必要とするため、電子機器の小型化への寄与が小さい。このため、半導体チップを積層したスタックドＭＣＰの開発が盛んに行われている。
【０００３】
この種のパッケージ構造としては、実開昭６２−１５８８４０号、特開平６−３７２５０号の公報に開示されているように、複数の半導体チップを外形寸法の大きさにしたがってピラミッド状に積層し、各半導体チップの端子電極をワイヤボンディングによって接続する構成となっているのが一般的である。
【０００４】
【発明が解決しようとする課題】
ところが、上記従来構造のマルチチップパッケージでは、積層する順位がチップサイズによって規制されてしまい、積層の自由度が少なくない欠点がある。すなわち、上位に積層されるチップは下位にあるチップよりもサイズが小さくなければならず、同一サイズのチップの積層はできない。また、チップ間の端子電極の接続にワイヤボンディングを利用して行なうが、端子間距離が一定していないため、ワイヤ長さが種々にわたってしまい、ボンディング長さに起因する電気的特性の劣化が生じてしまう問題もある。更に、積層するチップの下位チップは必ず上位チップよりは端子電極の形成領域が露出している必要があり、チップサイズに限定要件があるため、設計自由度が極めて小さいという問題もある。
【０００５】
本発明は、上記従来の問題点に着目し、同一サイズであっても異種サイズであっても半導体チップの３次元実装が容易にできるマルチベアチップ実装体、マルチチップパッケージおよびこれを用いた半導体装置ならびに電子機器を提供することを目的とする。また、電気的特性の劣化を最小にすることのできるマルチベアチップ実装体、マルチチップパッケージおよびこれを用いた半導体装置ならびに電子機器を提供することを目的とする。また、チップサイズに影響を受けずに３次元実装できるようにすることを目的とする。
【０００８】
【課題を解決するための手段】
また、本発明に係るマルチベアチップ実装体は、一つの回路装置を構成する異なる種類の半導体チップ同士に共通する電極を同一の配列パターンで各チップにおける隣接する２辺の範囲内に集中配置し、前記２辺を整列させて異種半導体チップを積層した積層体の端面部分で共通電極の導通接続をなして構成するようにしてもよい。この場合には、少なくとも同一種類の半導体チップは連続積層することができる。
【００１１】
【発明の実施の形態】
以下に、本発明に係るマルチベアチップ実装体、マルチチップパッケージ、半導体装置、ならびに電子機器の具体的実施の形態を図面を参照して詳細に説明する。
【００１２】
図１（１）、（２）は第１の実施形態に係るマルチベアチップ実装体１をプリント基板２に実装した状態の概略斜視図と平面図である。この実施形態に係るマルチベアチップ実装体１は同じサイズの２枚の半導体チップ３Ａ、３Ｂを上下に積層して構成されるているが、上層のチップ３Ａを下層のチップ３Ｂに対して平面位置をずらして積層するようにしている。実施形態では、両チップ３Ａ、３Ｂを縁辺が整合するように積層させた状態から、上層チップ３Ａを下層チップ３Ｂの対角線に沿って平面移動させ、下層チップ３Ｂのチップ端子４Ｂの形成領域が露出するようにして接着積層するようにしている。この場合、チップ端子４Ｂはこの露出縁辺に集中して配置するようにする。また、上層チップ３Ａには下層チップ３Ｂとの共通投影面（図１（２）のハッチング部分）上にあるチップ縁辺にチップ端子４Ａを配列させている。
【００１３】
プリント基板２上に上記した半導体チップ３Ａ、３Ｂを積層した後、ワイヤボンディングにより端子接続をなすが、下層チップ３Ｂのチップ端子４Ｂをプリント基板２に形成されている外部端子５Ｂにワイヤボンディングをなし、しかる後、上層チップ３Ａのチップ端子４Ａをプリント基板２の外部端子５Ａにワイヤボンディングを行なって接続が行なわれる。その後は図示しないが樹脂モールドにより全体を被覆することによりマルチチップパッケージが形成される。
【００１４】
このような実施形態では、マルチベアチップ実装体１を既存のワイヤボンディング技術を用いて形成することができ、同一サイズの半導体チップ３Ａ、３Ｂのマルチチップ化が可能となる。すなわち、上層チップ３Ａをワイヤボンディングする際に、そのチップ端子４Ａが下層チップ３Ｂに対して積層した際の共通投影面上にあるチップ縁辺に集中配列されているので、ボンディングツールによる圧下力を下層チップ３Ｂが支えるので、ワイヤボンディングを利用した実装が可能となるのである。
【００１５】
なお、上層チップ３Ａの平面移動方向は下層チップ３Ｂの対角線に沿った方向としてチップ２辺に端子４Ａを集中配置するようにしているが、チップ端子数が少なければチップ縁辺に沿ったＸ方向もしくはＹ方向に平面移動させて積層し、１辺のみにチップ端子４Ａを配置するようにしてもよい。また、３層以上の多層構造とする場合は、上層チップの端子配列は下位のチップ層との共通投影面上にある縁辺に集中配置する。
【００１６】
図２は実施形態に係るマルチベアチップ実装体１をプリント回路基板１２に実装した状態のマルチチップパッケージ１０の概略斜視図であり、図３はマルチチップパッケージ１０の端子間接続状態の説明断面図である。これらに図示しているように、マルチチップパッケージ１０は、異種サイズの複数の半導体チップ１４Ａ、１４Ｂ、１４Ｃをそれらの隣接する２辺が整列するように上下に積層して構成されている。換言すれば、半導体チップ１４Ａ、１４Ｂ、１４Ｃのサイズの如何に拘わらず、それらの一つのコーナ部分が一致するように積層するのである。この実施形態では、上層には正方形をなす最小半導体チップ１４Ａが配置され、その下位の中間層には一回り大きい正方形サイズの半導体チップ１４Ｂが配置され、最下層の半導体チップ１４Ａは、上記正方形半導体チップ１４Ｂの１辺長さより長い長辺と、正方形半導体チップ１４Ｂの１辺長さよりは短い短辺を有する長方形半導体チップ１４Ｃが配置されるように積層されている。そして、同一サイズの複数の最小半導体チップ１４Ａは縁辺を揃えて連続して積層するようにしている（図示の例では３層）。
【００１７】
このように同一または異種サイズの複数の半導体チップ１４Ａ、１４Ｂ、１４Ｃをそれらの隣接する２辺１６Ｘ、１６Ｙを整列するように一つのコーナが一致するようにして積層させるため、各半導体チップ１４（１４Ａ、１４Ｂ、１４Ｃ）では、次のような構成を採用している。すなわち、各半導体チップ１４Ａ、１４Ｂ、１４Ｃに共通する端子を上記整列された縁辺１６Ｘ、１６Ｙ側に集中させているのである。例えば、半導体チップ１４をメモリ素子として構成した場合、電源ライン、データライン、アドレスラインなどの電極端子、あるいはライトイネーブルなどの制御端子を共通にすることができる。したがって、このような共通端子１８ｎ（ｎ＝１、２、………ｎ）を各半導体チップ１４における整列縁辺１６Ｘ、１６Ｙに集中配置するようにしている。このとき、各半導体チップ１４の共通端子の配列パターンを一致させる。もちろん、端子ピッチ間隔も一定にすることが望ましい。このようにすることにより、各半導体チップ１４が積層されたとき、積層体の端面に配列された端子１８ｎが鉛直方向に１直線に配列される。
【００１８】
各半導体チップ１４を積層するに際して、層間に絶縁接着樹脂２０（図３参照）を介在させることで、チップ間で端子と基板シリコンとの接触による不具合を防止できる。そして、積層チップ１４の端子１８ｎ同士は図３に示しているように、ボンディングワイヤ２２などにより接続して導通をとるようにしている。これは、例えば、各半導体チップ１４の端子１８ｎの配列縁辺１６Ｘ、１６Ｙの部分に傾斜面を形成し、端子１８ｎ上にメタライズ層２４を形成して傾斜面に延設し、このメタライズ層２４を利用してワイヤボンディングを施し、プリント回路基板１２に形成している外部電極端子２６に対してワイヤボンディングにより接続をなせばよい。
【００１９】
また、積層チップ１４間の端子１８ｎ同士を導通接続する構成としては、図４に示すような方法も採用できる。これは図４（１）に示しているように、各半導体チップ１４の共通端子１８ｎを開口するようにチップ縁辺にＶ字溝２８を形成し、積層した後にこのＶ字溝２８が一直線に配列されるため、このＶ字溝２８にハンダなどの導電金属３０を埋め込んで導通をとるようにしてもよい。
【００２０】
このようにして形成されたマルチベアチップ実装体１は、プリント回路基板１２に実装されてマルチチップパッケージ１０とされ、プリント回路基板１２の端縁に設けたコネクタ端子３２と共通電極１８ｎとが配線ライン３４によって接続される。これにより機能をもった半導体装置３６が作製される。かかるマルチチップパッケージ１０では、異種サイズの半導体チップ１４は隣接する２辺１６Ｘ、１６Ｙに共通端子１８ｎを集中配置するように設計作製し、これらの２辺１６Ｘ、１６Ｙが整列するようにコーナを一致させて積層する構成を採用しているので、ピラミッド状にチップ積層しなくてもよく、積層作業を極めて簡易に行なわせることができる。そして、積層にはチップサイズによる制限は無いので、積層順位を任意に設定でき、パッケージ設計の自由度は著しく増大する。また、積層されるチップ１４の共通端子１８ｎ同士の接続距離は上下間で共通にすることができ、ボンディングワイヤ２２の長さも最短となる。この結果、電気的な特性の劣化を最小に抑えることができるのである。マルチチップパッケージ１０の揃えた縁辺１６Ｘ、１６Ｙ以外の箇所では凹凸端面となるが、これらは樹脂モールドによって外形を整えることができるので、何ら問題はない。
【００２１】
なお、上記構成では、サイズが異なる半導体チップ１４Ａ、１４Ｂ、１４Ｃを積層するものとして述べたが、サイズの如何に拘わらず、一つの回路装置を構成する異なる種類の半導体チップを対象とし、これらに共通する電極を同一の配列パターンで各チップにおける隣接する２辺の範囲内に集中配置し、前記２辺を整列させて異種半導体チップを積層してこの積層体の端面部分で共通電極の導通接続をなすようにしてもよい。この場合においても、前述した半導体チップ１４Ａの場合と同様に、同一種類の半導体チップは連続積層させるようにすればよい。
【００２２】
図５には、本発明の実施の形態に係る半導体装置１１００を実装した回路基板１０００を示している。回路基板１０００には、例えばガラスエポキシ基板等の有機系基板を用いることが一般的である。回路基板１０００には、例えば銅からなるボンディング部が所望の回路となるように形成されている。そして、ボンディング部と半導体装置１１００の外部電極とを電気的に接続することでそれらの電気的導通が図られる。
【００２３】
なお、半導体装置１１００は、実装面積をベアチップにて実装する面積にまで小さくすることができるので、この回路基板１０００を電子機器に用いれば電気機器自体の小型化が図れる。また、同一面積内においては、より実装スペースを確保することができ、高機能化を図ることも可能である。
【００２４】
そして、この回路基板１０００を備える電子機器として、図６にノート型パーソナルコンピュータ１２００を示している。前記ノート型パーソナルコンピュータ１２００は、高機能化を図った回路基板１０００を備えているため、性能を向上させることができる。
【００２５】
【発明の効果】
以上説明したように、本発明は同一または異種サイズの複数の半導体チップを平面的にずらして積層して共通上層チップのチップ端子を共通投影面上にあるチップ縁辺に集中して配置し、あるいはそれらの隣接する２辺を整列して積層し、各半導体チップに共通する端子を上記整列された縁辺側に集中させ、集中配置された積層チップ間の端子同士を積層体の端面部分で導通接続した構成としたので、半導体チップの３次元実装が容易にできるとともに、電気的特性の劣化を最小にすることのできるマルチベアチップ実装体、マルチチップパッケージおよびこれを用いた半導体装置ならびに電子機器とすることができる。
【図面の簡単な説明】
【図１】第１実施形態に係るマルチベアチップ実装体を実装した半導体装置の斜視図およびボンディングワイヤを省略した平面図である。
【図２】第２実施形態に係るマルチベアチップ実装体を実装した半導体装置の斜視図である。
【図３】同マルチチップパッケージの端子間接続状態を示す断面図である。
【図４】同マルチチップパッケージの端子間接続の他の形態の説明図であり、（１）図は分解斜視図、（２）図は積層状態の説明斜視図である。
【図５】実施形態に係るマルチベアチップ実装体またはマルチチップパッケージの回路基板への適用例の説明図である。
【図６】実施形態に係るマルチベアチップ実装体またはマルチチップパッケージの電子機器への適用例の説明図である。
【符号の説明】
１ マルチベアチップ実装体
２ プリント回路基板
３Ａ 上層半導体チップ
３Ｂ 下層半導体チップ
４Ａ 上層チップ端子
４Ｂ 下層チップ端子
５Ａ、５Ｂ 外部電極端子
１０ マルチチップパッケージ
１２ プリント回路基板
１４（１４Ａ、１４Ｂ、１４Ｃ） 半導体チップ
１６Ｘ、１６Ｙ 整列縁辺
１８ｎ 共通端子
２０ 絶縁接着樹脂
２２ ボンディングワイヤ
２４ メタライズ層
２６ 外部電極端子
２８ Ｖ字溝
３０ 導電金属
３２ コネクタ端子
３４ 配線ライン
３６ 半導体装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multichip package, a semiconductor device, and an electronic device, and more particularly to a multichip package, a semiconductor device, and an electronic device having a configuration in which a semiconductor chip is three-dimensionally mounted.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the improvement in performance and miniaturization of electronic devices, a multi-bare chip mounting body is configured by arranging a plurality of semiconductor chips in one package, and this is mounted on a substrate or sealed with a resin. By using a package (Multi Chip Package), the semiconductor device is highly functional and downsized. The multi-chip package includes a plurality of semiconductor chips arranged in a plane and a plurality of semiconductor chips stacked in the thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, and therefore contributes little to downsizing of electronic devices. For this reason, development of stacked MCPs in which semiconductor chips are stacked has been actively conducted.
[0003]
As this type of package structure, as disclosed in Japanese Utility Model Laid-Open No. 62-158840 and Japanese Patent Laid-Open No. 6-37250, a plurality of semiconductor chips are stacked in a pyramid shape according to the size of the outer dimensions, In general, terminal electrodes of each semiconductor chip are connected by wire bonding.
[0004]
[Problems to be solved by the invention]
However, the multi-chip package having the conventional structure has a drawback that the order of stacking is restricted by the chip size, and the degree of freedom of stacking is not small. That is, the chip stacked on the upper side must be smaller in size than the chip on the lower side, and chips of the same size cannot be stacked. In addition, wire bonding is used to connect the terminal electrodes between the chips, but since the distance between the terminals is not constant, the wire length varies, and the electrical characteristics deteriorate due to the bonding length. There is also a problem. Further, the lower chip of the stacked chips must necessarily expose the terminal electrode formation region rather than the upper chip, and there is a problem that the degree of freedom in design is extremely small because there is a limited requirement for the chip size.
[0005]
The present invention pays attention to the above-mentioned conventional problems, and a multi-bare chip mounting body, a multi-chip package, and a semiconductor device using the same, which can easily perform three-dimensional mounting of semiconductor chips of the same size or different sizes An object is to provide an electronic device. It is another object of the present invention to provide a multi-bare chip mounted body, a multi-chip package, a semiconductor device using the same, and an electronic apparatus that can minimize deterioration of electrical characteristics. It is another object of the present invention to enable three-dimensional mounting without being affected by the chip size.
[0008]
[Means for Solving the Problems]
Further, the multi-bare chip mounting body according to the present invention concentrates and arranges electrodes common to different types of semiconductor chips constituting one circuit device within the range of two adjacent sides in each chip in the same arrangement pattern, The two electrodes may be arranged so that the common electrode is conductively connected at the end face portion of the stacked body in which the two sides are aligned and the different semiconductor chips are stacked. In this case, at least the same type of semiconductor chips can be continuously stacked.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments of a multi-bare chip mounted body, a multi-chip package, a semiconductor device, and an electronic device according to the present invention will be described in detail with reference to the drawings.
[0012]
FIGS. 1A and 1B are a schematic perspective view and a plan view of a state in which the multi-bare chip mounting body 1 according to the first embodiment is mounted on a printed board 2. The multi-bare chip mounting body 1 according to this embodiment is configured by stacking two semiconductor chips 3A and 3B having the same size vertically, but the upper chip 3A is placed in a planar position with respect to the lower chip 3B. They are shifted and stacked. In the embodiment, the upper layer chip 3A is planarly moved along the diagonal line of the lower layer chip 3B from the state where both the chips 3A and 3B are laminated so that the edges are aligned, and the formation region of the chip terminal 4B of the lower layer chip 3B is exposed. In this way, adhesive lamination is performed. In this case, the chip terminals 4B are arranged so as to be concentrated on the exposed edge. Further, chip terminals 4A are arranged on the chip edge on the upper projection chip 3A on the common projection plane (hatched portion in FIG. 1 (2)) with the lower chip 3B.
[0013]
After the semiconductor chips 3A and 3B described above are stacked on the printed circuit board 2, terminal connection is made by wire bonding, but the chip terminals 4B of the lower layer chip 3B are wire bonded to the external terminals 5B formed on the printed circuit board 2. Thereafter, the chip terminal 4A of the upper layer chip 3A is connected to the external terminal 5A of the printed board 2 by wire bonding. Thereafter, although not shown, a multichip package is formed by covering the whole with a resin mold.
[0014]
In such an embodiment, the multi-bare chip mounting body 1 can be formed using an existing wire bonding technique, and the semiconductor chips 3A and 3B having the same size can be made into multi-chips. That is, when wire bonding the upper layer chip 3A, the chip terminals 4A are concentrated on the chip edge on the common projection plane when stacked on the lower layer chip 3B. Since the chip 3B supports, mounting using wire bonding becomes possible.
[0015]
The plane movement direction of the upper layer chip 3A is the direction along the diagonal line of the lower layer chip 3B, and the terminals 4A are concentrated on the two sides of the chip. However, if the number of chip terminals is small, the X direction along the chip edge or It is also possible to stack by moving the plane in the Y direction, and to arrange the chip terminals 4A only on one side. In the case of a multilayer structure of three or more layers, the terminal arrangement of the upper chip is concentrated on the edge on the common projection plane with the lower chip layer.
[0016]
2 is a schematic perspective view of the multi-chip package 10 in a state where the multi-bare chip mounting body 1 according to the embodiment is mounted on the printed circuit board 12, and FIG. 3 is an explanatory sectional view of a connection state between terminals of the multi-chip package 10. is there. As shown in these drawings, the multi-chip package 10 is configured by stacking a plurality of semiconductor chips 14A, 14B, and 14C of different sizes in the vertical direction so that their two adjacent sides are aligned. In other words, regardless of the size of the semiconductor chips 14A, 14B, and 14C, they are stacked so that one corner portion thereof matches. In this embodiment, a square-shaped minimum semiconductor chip 14A is arranged in the upper layer, a square-sized semiconductor chip 14B is arranged in the lower intermediate layer, and the lowermost semiconductor chip 14A is the square semiconductor. The rectangular semiconductor chips 14C having a longer side longer than one side of the chip 14B and a shorter side shorter than one side of the square semiconductor chip 14B are stacked. A plurality of the smallest semiconductor chips 14A having the same size are continuously stacked with their edges aligned (three layers in the illustrated example).
[0017]
In this way, a plurality of semiconductor chips 14A, 14B, 14C of the same or different sizes are stacked so that one corner coincides so that their two adjacent sides 16X, 16Y are aligned. 14A, 14B, 14C) employs the following configuration. That is, the terminals common to the semiconductor chips 14A, 14B, and 14C are concentrated on the side of the aligned edges 16X and 16Y. For example, when the semiconductor chip 14 is configured as a memory element, electrode terminals such as a power supply line, a data line, and an address line, or a control terminal such as a write enable can be shared. Therefore, the common terminals 18n (n = 1, 2,... N) are concentrated on the alignment edges 16X and 16Y in each semiconductor chip 14. At this time, the arrangement pattern of the common terminals of the respective semiconductor chips 14 is matched. Of course, it is desirable to keep the terminal pitch interval constant. By doing in this way, when each semiconductor chip 14 is laminated | stacked, the terminal 18n arranged on the end surface of a laminated body is arranged in 1 straight line in the perpendicular direction.
[0018]
When the semiconductor chips 14 are stacked, the insulating adhesive resin 20 (see FIG. 3) is interposed between the layers, thereby preventing problems caused by contact between the terminals and the substrate silicon between the chips. Then, as shown in FIG. 3, the terminals 18n of the laminated chip 14 are connected by a bonding wire 22 or the like so as to be conductive. This is because, for example, an inclined surface is formed on the arrangement edge 16X, 16Y portion of the terminal 18n of each semiconductor chip 14, a metallized layer 24 is formed on the terminal 18n, and the inclined surface is extended. Wire bonding is performed using the wire electrode, and the external electrode terminal 26 formed on the printed circuit board 12 may be connected by wire bonding.
[0019]
Further, as a configuration in which the terminals 18n between the laminated chips 14 are conductively connected, a method as shown in FIG. 4 can also be adopted. As shown in FIG. 4A, a V-shaped groove 28 is formed on the chip edge so as to open the common terminal 18n of each semiconductor chip 14, and the V-shaped grooves 28 are arranged in a straight line after stacking. Therefore, a conductive metal 30 such as solder may be buried in the V-shaped groove 28 for electrical conduction.
[0020]
The multi-bare chip mounting body 1 formed in this way is mounted on the printed circuit board 12 to form the multi-chip package 10, and the connector terminal 32 and the common electrode 18n provided on the edge of the printed circuit board 12 are connected to the wiring line. 34 is connected. Thereby, a semiconductor device 36 having a function is manufactured. In such a multi-chip package 10, the semiconductor chips 14 of different sizes are designed and manufactured so that the common terminals 18n are concentrated on the two adjacent sides 16X and 16Y, and the corners are aligned so that the two sides 16X and 16Y are aligned. Since the configuration of stacking is adopted, it is not necessary to stack the chips in a pyramid shape, and the stacking operation can be performed extremely easily. Further, since there is no limitation on the chip size for stacking, the stacking order can be arbitrarily set, and the degree of freedom in package design is significantly increased. Further, the connection distance between the common terminals 18n of the stacked chips 14 can be made common between the upper and lower sides, and the length of the bonding wire 22 is also shortest. As a result, the deterioration of electrical characteristics can be minimized. The portions other than the aligned edges 16X and 16Y of the multichip package 10 become uneven end faces, but these can be trimmed by a resin mold, so there is no problem.
[0021]
In the above configuration, the semiconductor chips 14A, 14B, and 14C having different sizes are described as being stacked. However, regardless of the size, different types of semiconductor chips that constitute one circuit device are targeted. Common electrodes are concentrated and arranged in the range of two adjacent sides in each chip in the same arrangement pattern, and the two sides are aligned to stack different semiconductor chips, and the common electrode is electrically connected at the end face portion of this stacked body. You may make it make. Also in this case, the same type of semiconductor chips may be continuously stacked as in the case of the semiconductor chip 14A described above.
[0022]
FIG. 5 shows a circuit board 1000 on which the semiconductor device 1100 according to the embodiment of the present invention is mounted. As the circuit board 1000, an organic substrate such as a glass epoxy substrate is generally used. On the circuit board 1000, for example, a bonding portion made of copper is formed so as to form a desired circuit. Then, electrical connection between the bonding portion and the external electrode of the semiconductor device 1100 is achieved.
[0023]
Note that since the mounting area of the semiconductor device 1100 can be reduced to a mounting area with a bare chip, if the circuit board 1000 is used for an electronic device, the electric device itself can be downsized. In addition, in the same area, more mounting space can be secured and higher functionality can be achieved.
[0024]
FIG. 6 shows a notebook personal computer 1200 as an electronic device including the circuit board 1000. Since the notebook personal computer 1200 includes the circuit board 1000 with high functionality, the performance can be improved.
[0025]
【The invention's effect】
As described above, according to the present invention, a plurality of semiconductor chips of the same or different sizes are stacked while being shifted in a plane, and the chip terminals of the common upper layer chip are concentrated on the chip edge on the common projection plane, or Two adjacent sides are aligned and stacked, the terminals common to each semiconductor chip are concentrated on the aligned edge side, and the terminals between the stacked chips arranged in a conductive manner are connected at the end face of the stacked body. With this configuration, it is possible to easily perform three-dimensional mounting of a semiconductor chip and to minimize deterioration of electrical characteristics, and to provide a multi-bare chip mounting body, a multi-chip package, and a semiconductor device and an electronic apparatus using the same. be able to.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor device mounted with a multi-bear chip mounting body according to a first embodiment and a plan view in which bonding wires are omitted.
FIG. 2 is a perspective view of a semiconductor device mounted with a multi-bare chip mounting body according to a second embodiment.
FIG. 3 is a cross-sectional view showing a connection state between terminals of the multichip package.
FIGS. 4A and 4B are explanatory views of another form of inter-terminal connection of the multichip package, wherein FIG. 4A is an exploded perspective view, and FIG. 4B is an explanatory perspective view of a stacked state.
FIG. 5 is an explanatory diagram of an application example of the multi-bare chip mounting body or the multi-chip package according to the embodiment to a circuit board.
FIG. 6 is an explanatory diagram of an application example of the multi-bare chip mounting body or the multi-chip package according to the embodiment to an electronic device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Multi bear chip mounting body 2 Printed circuit board 3A Upper layer semiconductor chip 3B Lower layer semiconductor chip 4A Upper layer chip terminal 4B Lower layer chip terminal 5A, 5B External electrode terminal 10 Multichip package 12 Printed circuit board 14 (14A, 14B, 14C) Semiconductor chip 16X , 16Y Alignment edge 18n Common terminal 20 Insulating adhesive resin 22 Bonding wire 24 Metallized layer 26 External electrode terminal 28 V-shaped groove 30 Conductive metal 32 Connector terminal 34 Wiring line 36 Semiconductor device

Claims (1)

一つの回路装置を構成する異なる種類の半導体チップ同士に共通する電極を同一の配列パターンで各チップにおける隣接する２辺の範囲内に集中配置し、前記２辺を整列させて異種半導体チップを積層してこの積層体の端面部分で共通電極の導通接続をなして構成されたことを特徴とするマルチベアチップ実装体。  Electrodes common to different types of semiconductor chips constituting one circuit device are concentratedly arranged in the range of two adjacent sides in each chip in the same arrangement pattern, and the two sides are aligned to stack different types of semiconductor chips A multi-bare chip mounting body characterized in that the common electrode is electrically connected at an end face portion of the laminated body.
JP2000000934A 2000-01-06 2000-01-06 Multi-bare chip assembly Expired - Fee Related JP3832170B2 (en)

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JP3768761B2 (en) 2000-01-31 2006-04-19 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JP2002299595A (en) * 2001-04-03 2002-10-11 Matsushita Electric Ind Co Ltd Solid state imaging unit and its manufacturing method
DE10322719A1 (en) * 2003-05-20 2005-01-05 Infineon Technologies Ag Circuit arrangement with several chips in housing has at least one top chip mounted on base chip or chips so that base chip does or does not fully support top chip
JP2007066922A (en) * 2003-11-28 2007-03-15 Renesas Technology Corp Semiconductor integrated circuit device
KR100627006B1 (en) 2004-04-01 2006-09-25 삼성전자주식회사 Indent chip, semiconductor package and multi chip package using the same
JP4216825B2 (en) 2005-03-22 2009-01-28 株式会社日立製作所 Semiconductor package
JP2007059541A (en) * 2005-08-23 2007-03-08 Toshiba Corp Semiconductor device and method of assembling same
JP2007294488A (en) 2006-04-20 2007-11-08 Shinko Electric Ind Co Ltd Semiconductor device, process for manufacturing the same and electronic component
JP4921937B2 (en) * 2006-11-24 2012-04-25 株式会社東芝 Semiconductor integrated circuit
JP2009123923A (en) * 2007-11-15 2009-06-04 Elpida Memory Inc Semiconductor device and its production process
US8097956B2 (en) * 2009-03-12 2012-01-17 Apple Inc. Flexible packaging for chip-on-chip and package-on-package technologies

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