JP2023173553A - Wafer and processing method for wafer - Google Patents

Abstract

To suppress a semiconductor chip from chipping.SOLUTION: A wafer 20 is subjected to an expand process after having a modified region formed along lines 15 to have a plurality of semiconductor chips 120, and has a plurality of chip-formation regions 200 sectioned with chip section lines 151 as the lines 15, wherein a chip-formation region 200 has a chip part 120x which constitutes a semiconductor chip 120 and a cut-off part 122 which is cut off from the chip part 120x and also connects with the chip part 120x through an opening line 152 as the line 15 so set as to form an opening part 121 in a cut-off shape in the semiconductor chip 120, and the opening line 152 is so set that the width of the opening part 121 increases toward an opening end side, or is constant.SELECTED DRAWING: Figure 16

Description

One aspect of the present invention relates to a wafer and a wafer processing method.

A method of obtaining a plurality of semiconductor chips by dividing a wafer is known. For example, Patent Document 1 discloses a method of performing dry etching on a wafer to divide the wafer and obtain a plurality of semiconductor chips from the wafer. In addition, Patent Document 2 discloses that a modified region is formed inside the wafer by laser irradiation on the wafer, and a tape attached to the wafer on which the modified region is formed is expanded. A method for obtaining a semiconductor chip is disclosed.

Japanese Patent Application Publication No. 2011-146717 JP2012-028452A

A semiconductor chip may have a notch-shaped opening formed therein. Such an opening is formed, for example, for positioning (alignment) when installing a semiconductor chip in an optical-related product, or as a hole through which light from a light emitting element passes. For example, when dividing a wafer, a semiconductor chip and a portion in which an opening is to be formed are separated, thereby obtaining a semiconductor chip in which an opening is formed.

Here, for example, in a method of obtaining a plurality of semiconductor chips by expanding a wafer on which a modified region has been formed, the part separated from the semiconductor chip (the part forming the opening) by the expansion of the wafer becomes the semiconductor chip. Contact may cause chipping of the semiconductor chip.

One aspect of the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wafer and a wafer processing method that can suppress the occurrence of chipping in semiconductor chips.

(1) A wafer according to one aspect of the present invention is a wafer in which a plurality of semiconductor chips are obtained by performing an expanding process after a modified region is formed along a scheduled cutting line, It has a plurality of chipped regions divided by chip division lines, and the chipped regions are a chip part that constitutes a semiconductor chip and a part separated from the chip part, and a notch-shaped opening in the semiconductor chip. A separation section that is continuous to the chip part via an opening line that is a line to be cut so that It is set to be constant.

In the wafer according to one aspect of the present invention, in the chip forming region, the chip portion and the separation portion are continuously formed through an opening line that is a scheduled cutting line for forming an opening in the semiconductor chip. . In this wafer, the opening line is set so that the width of the opening increases toward the opening end or remains constant. By setting the opening line in this way, when a modified region is formed along the opening line and an expanding process is performed, the chip part (semiconductor chip) and the chip part (semiconductor chip) can be separated from each other. Contact with the cutoff portion to be cut off is suppressed. Thereby, occurrence of chipping in the semiconductor chip can be effectively suppressed.

(2) In the wafer described in (1) above, in the opening line of the chip area where the chip portion is closer to the center of the wafer than the cut-off portion, the width of the opening widens toward the outer edge of the wafer or remains constant. The opening line of the chip area where the chip part is closer to the outer edge of the wafer than the separation part is set so that the width of the opening widens toward the center of the wafer or remains constant. may have been done.

According to such a configuration, the chip part and the cut-off part to be separated from the chip part do not come into contact with each other, regardless of whether the chip part is closer to the center of the wafer than the cut-off part or if it is closer to the outer edge of the wafer. can be appropriately suppressed. In addition, in the expanding process, the displacement of the part far from the center of the wafer (that is, the outer edge of the wafer) becomes larger, so in a configuration where the chip part is closer to the center of the wafer than the cut-out part, it is difficult to separate the cut-out part. It is possible to effectively displace the semiconductor chip in the desired direction (toward the outer edge of the wafer, which is the direction away from the chip part), improve the separation property of the separation part, and more effectively suppress the occurrence of chipping in the semiconductor chip. can.

(3) In the wafer described in (1) or (2) above, the opening line of the chip area adjacent to the outer edge of the wafer may extend to the outer edge of the wafer. Since the opening line extends to the outer edge of the wafer in this manner, the dividing property of the cut-off portion can be improved, and the occurrence of chipping in the semiconductor chip can be more effectively suppressed.

(4) In the wafer described in (1) to (3) above, the chip partition line may extend to the outer edge of the wafer. In this way, by extending the chip partitioning line to the outer edge of the wafer, it is possible to improve the dividing property of the chip portion.

(5) In the wafer described in (1) to (4) above, the plurality of chipped regions are arranged radially from the center of the wafer, and the chip portion and the cut-off portion are on lines radially extending from the center of the wafer. may be provided consecutively in order. When a device that expands a wafer radially is used as an expander, a plurality of chip regions are arranged radially from the center of the wafer, and the chip portion and the cut-off portion are placed on a line that extends radially from the center of the wafer. , the chip portions and cut-off portions of a plurality of chip regions are arranged in the expansion direction. By expanding such a wafer using the above-mentioned expander, it is possible to improve the dividability and effectively suppress the occurrence of chipping in the semiconductor chips.

(6) In the wafer described in (1) to (5) above, the aperture line may be set such that the center line of the aperture angle of the aperture is located on a line that radiates from the center of the wafer. When a device that expands the wafer radially is used as an expander, the center line of the opening angle of the opening is located on a line that spreads radially from the center of the wafer, thereby preventing contact between the chip part and the cut-off part. The chip portion and the separation portion can be separated while being appropriately suppressed. That is, it is possible to more effectively suppress the occurrence of chipping in the semiconductor chip.

(7) A wafer according to one aspect of the present invention is a wafer in which a plurality of semiconductor chips are obtained by performing an expanding process after a modified region is formed along a scheduled cutting line, and It has a plurality of chipped regions divided by chip division lines, and the chipped regions are a chip part that constitutes a semiconductor chip and a part separated from the chip part, and a notch-shaped opening in the semiconductor chip. A cut-off part that is continuous to the chip part through an opening line that is a line to be cut so that the cut-off part is formed, and the opening line prevents contact between the chip part and the cut-off part during the expanding process. It is set so that

In the wafer according to one aspect of the present invention, in the chip forming region, the chip portion and the separation portion are continuously formed through an opening line that is a scheduled cutting line for forming an opening in the semiconductor chip. . In this wafer, the opening line is set so as to avoid contact between the chip part and the cut-off part in the expanding process. By setting the opening line in this way, when a modified region is formed along the opening line and an expanding process is performed, the chip part (semiconductor chip) and the chip part (semiconductor chip) can be separated from each other. Contact with the cutoff portion to be cut off is suppressed. Thereby, occurrence of chipping in the semiconductor chip can be effectively suppressed.

(8) A wafer processing method according to one aspect of the present invention has a plurality of chipping regions partitioned by chip partition lines that are scheduled cutting lines, and the chipping region is connected to a chip portion constituting a semiconductor chip. , a cut-off portion that is a portion to be separated from the chip portion and is continuous to the chip portion via an opening line that is a scheduled cutting line set so that a notch-shaped opening is formed in the semiconductor chip. A step of preparing a wafer, a step of irradiating a laser beam along the planned cutting line to form a modified region, and a step of expanding the tape attached to the wafer on which the modified region has been formed, separates the chip part from the cut-off part. and a step of separating the semiconductor chips at intervals to obtain semiconductor chips.

In the wafer processing method according to one aspect of the present invention, in the chip forming region, the chip portion and the separation portion are continuously formed via an opening line that is a scheduled cutting line for forming an opening in the semiconductor chip. A processed wafer is prepared. Then, a modified region is formed on the wafer along the planned cutting line, and the tape attached to the wafer is expanded to obtain semiconductor chips. Here, in this processing method, in the step of obtaining a semiconductor chip, the chip part and the cut-off part are separated with an interval between them. As a result, contact between the chip portion (semiconductor chip) and the cut-off portion that is separated from the chip portion (semiconductor chip) is suppressed, and occurrence of chipping in the semiconductor chip can be effectively suppressed.

(9) In the processing method described in (8) above, the plurality of chipped regions are arranged radially from the center of the wafer, and the chip portion and the cut-off portion are continuous on a line that spreads radially from the center of the wafer. In the expanding step, the tape attached to the wafer may be expanded in a direction extending radially from the center of the wafer. As a result, the direction in which the chip portion and the cut-off portion are successively provided can be aligned with the direction of expansion, which improves the divisibility and effectively suppresses the occurrence of chipping in the semiconductor chip. can.

(10) In the processing method described in (8) or (9) above, the opening line of the chipping region close to the outer edge of the wafer may extend to the outer edge of the wafer. Since the opening line extends to the outer edge of the wafer in this manner, the dividing property of the cut-off portion can be improved, and the occurrence of chipping in the semiconductor chip can be more effectively suppressed.

(11) In the processing method described in (10) above, in the step of forming the modified region, the opening line extending to the outer edge of the wafer is modified by irradiating the laser beam from the inside to the outside of the opening line. A region may also be formed. According to such a configuration, cracks caused by the formation of the modified region can be stopped inside the opening line and extended outside the opening line. Thereby, cracks can be appropriately stopped at the portion where cracks are to be stopped (inside the opening line that will become the semiconductor chip).

(12) In the processing methods described in (8) to (11) above, in the step of forming the modified region, an elliptical laser beam is irradiated in a direction opposite to the crystal direction side with respect to the advancing direction of the opening line. Good too. Regarding the laser beam, it may be bent toward the crystal direction (pulled toward the crystal direction). The laser beam can be irradiated in a desired direction of processing, taking into account the bending toward the crystal direction. That is, according to such a configuration, it is possible to realize the formation of a modified region along the planned cutting line.

(13) In the processing method described in (8) to (12) above, in the step of forming the modified region, the number of scans of the laser beam when forming the modified region along the opening line is set to the chip partition line. The number of scans of the laser beam may be set to be greater than the number of scans of the laser beam when forming the modified region along the line. According to such a configuration, the number of scans of the laser beam for separating the cut-off portion is greater than the number of scans of the laser beam for cutting the chip portion from the wafer. Can be separated. By separating the cut-off part early, the center of gravity of the wafer can be determined early, and repeated movement of the center of gravity makes it easier for the cut-off part to come into contact with the chip part, causing chipping in the semiconductor chip. The situation can be avoided.

(14) In the processing methods described in (8) to (13) above, the chip partition line may extend to the outer edge of the wafer. In this way, by extending the chip partitioning line to the outer edge of the wafer, it is possible to improve the dividing property of the chip portion.

(15) A wafer processing method according to one aspect of the present invention includes the steps of preparing the wafer described in (1) to (7) above, forming a modified region along a scheduled cutting line, and modifying the wafer. The method includes the step of obtaining a plurality of semiconductor chips by expanding a tape attached to a wafer having regions formed thereon. According to such a wafer processing method, contact between the chip part (semiconductor chip) and the separation part that is separated from the chip part (semiconductor chip) is suppressed, and chipping (chipping) of the semiconductor chip is effectively prevented. can be suppressed.

According to one aspect of the present invention, occurrence of chipping in a semiconductor chip can be suppressed.

FIG. 2 is a configuration diagram of a laser processing device that forms a modified region inside a wafer. FIG. 2 is a plan view of a wafer to be processed. 3 is a cross-sectional view of a portion of the wafer shown in FIG. 2; FIG. 3 is a flowchart showing a wafer processing method. FIG. 3 is a diagram illustrating an example of the use of a semiconductor chip in which an opening is formed. FIG. 3 is a diagram illustrating an example of the use of a semiconductor chip in which an opening is formed. FIG. 3 is a diagram illustrating the occurrence of chipping. FIG. 3 is a diagram illustrating the amount of displacement of each part of the wafer in an expanding process. FIG. 3 is a diagram illustrating the occurrence of chipping. FIG. 3 is a diagram illustrating an example of arrangement of chipped regions in which chipping is suppressed. FIG. 3 is a diagram illustrating an example of arrangement of chipped regions in which chipping is suppressed. FIG. 3 is a diagram illustrating various arrangement examples of chip regions. FIG. 3 is a diagram illustrating an example of arrangement of chipped regions in which chipping is suppressed. It is a figure explaining an example of an expansion process. It is a figure explaining other examples of an expansion process. It is a figure which shows the example of a line setting. It is a figure which shows the example of a line setting. It is a figure which shows the example of a line setting. It is a figure explaining the processing order of an opening line. FIG. 3 is a diagram illustrating laser beam irradiation at each processing location. It is a figure explaining the processing conditions of an opening line and a chip division line.

Hereinafter, embodiments according to one aspect of the present invention will be described in detail with reference to the drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and overlapping explanations will be omitted.

In this embodiment, a modified region is formed inside a wafer (target object). For example, a laser processing apparatus 100 shown in FIG. 1 can be used as an apparatus for forming a modified region inside a wafer. As shown in FIG. 1, the laser processing apparatus 100 includes a support section 102, a light source 103, an optical axis adjustment section 104, a spatial light modulator 105, a condensing section 106, an optical axis monitor section 107, It includes a visible imaging section 108A, an infrared imaging section 108B, a moving mechanism 109, and a management unit 150. The laser processing apparatus 100 is an apparatus that forms a modified region 11 on the wafer 20 by irradiating the wafer 20 with a laser beam L0. In the following description, three mutually orthogonal directions will be referred to as an X direction, a Y direction, and a Z direction, respectively. As an example, the X direction is a first horizontal direction, the Y direction is a second horizontal direction perpendicular to the first horizontal direction, and the Z direction is a vertical direction.

The support portion 102 supports the wafer 20 by, for example, adsorbing the wafer 20. The support part 102 is movable along each of the X direction and the Y direction. The support portion 102 is rotatable around a rotation axis along the Z direction. The light source 103 emits a laser beam L0 using, for example, a pulse oscillation method. The laser beam L0 is transparent to the wafer 20. The optical axis adjustment unit 104 adjusts the optical axis of the laser beam L0 emitted from the light source 103. The optical axis adjustment unit 104 is composed of, for example, a plurality of reflecting mirrors whose positions and angles can be adjusted.

Spatial light modulator 105 is arranged within laser processing head H. Spatial light modulator 105 modulates laser light L0 emitted from light source 103. The spatial light modulator 105 is a reflective liquid crystal (LCOS) spatial light modulator (SLM). In the spatial light modulator 105, the laser beam L0 can be modulated by appropriately setting a modulation pattern to be displayed on its display section (liquid crystal layer). In this embodiment, the laser beam L0 that has traveled downward along the Z direction from the optical axis adjustment unit 104 enters the laser processing head H, is reflected by the mirror MM1, and enters the spatial light modulator 105. The spatial light modulator 105 reflects and modulates the laser light L0 thus incident.

The light condensing section 106 is attached to the bottom wall of the laser processing head H. The condensing unit 106 condenses the laser beam L0 modulated by the spatial light modulator 105 onto the wafer 20 supported by the support unit 102. In this embodiment, the laser beam L0 reflected by the spatial light modulator 105 is reflected by the dichroic mirror MM2 and enters the condenser 106. The condensing unit 106 condenses the laser beam L0 thus incident on the wafer 20. The condensing unit 106 is configured by a condensing lens unit 161 attached to the bottom wall of the laser processing head H via a drive mechanism 162. The drive mechanism 162 moves the condensing lens unit 161 along the Z direction using, for example, a driving force of a piezoelectric element.

In addition, in the laser processing head H, an imaging optical system (not shown) is arranged between the spatial light modulator 105 and the condenser 106. The imaging optical system constitutes a double-sided telecentric optical system in which the reflective surface of the spatial light modulator 105 and the entrance pupil plane of the condenser 106 are in an imaging relationship. As a result, the image of the laser beam L0 on the reflective surface of the spatial light modulator 105 (the image of the laser beam L0 modulated by the spatial light modulator 105) is transferred (imaged) to the entrance pupil plane of the condenser 106. be done. A pair of distance measuring sensors S1 and S2 are attached to the bottom wall of the laser processing head H so as to be located on both sides of the condenser lens unit 161 in the X direction. Each distance measurement sensor S1, S2 emits distance measurement light (for example, laser light) to the laser light entrance surface of the wafer 20, and detects the distance measurement light reflected from the laser light entrance surface. In this way, displacement data of the laser beam incident surface is obtained.

The optical axis monitor section 107 is arranged within the laser processing head H. The optical axis monitor unit 107 detects a portion of the laser beam L0 that has passed through the dichroic mirror MM2. The detection result by the optical axis monitor unit 107 indicates, for example, the relationship between the optical axis of the laser beam L0 incident on the condensing lens unit 161 and the optical axis of the condensing lens unit 161. The visible imaging unit 108A emits visible light V0 and obtains an image of the wafer 20 using visible light V0. The visible imaging unit 108A is arranged within the laser processing head H. The infrared imaging unit 108B emits infrared light and obtains an infrared image of the wafer 20 as an infrared image. The infrared imaging unit 108B is attached to the side wall of the laser processing head H.

The moving mechanism 109 includes a mechanism that moves at least one of the laser processing head H and the support section 102 in the X direction, the Y direction, and the Z direction. The moving mechanism 109 moves at least one of the laser processing head H and the support part 102 by the driving force of a known drive device such as a motor so that the focal point C of the laser beam L0 moves in the X direction, the Y direction, and the Z direction. or to drive. The moving mechanism 109 includes a mechanism that rotates the support section 102. The moving mechanism 109 rotationally drives the support portion 102 using the driving force of a known driving device such as a motor.

Management unit 250 includes a control section 251, a user interface 252, and a storage section 253. The control section 251 controls the operation of each section of the laser processing apparatus 100. The control unit 251 is configured as a computer device including a processor, memory, storage, communication device, and the like. In the control unit 251, a processor executes software (program) read into a memory or the like, and controls reading and writing of data in the memory and storage, and communication by a communication device. The user interface 252 displays and inputs various data. The user interface 252 constitutes a GUI (Graphical User Interface) having a graphic-based operation system.

The user interface 252 includes, for example, at least one of a touch panel, a keyboard, a mouse, a microphone, a tablet terminal, a monitor, and the like. The user interface 252 can accept various inputs, such as touch input, keyboard input, mouse operation, and voice input. The user interface 252 can display various types of information on its display screen. The user interface 252 corresponds to an input reception unit that receives input, and a display unit that can display a setting screen based on the received input. The storage unit 253 is, for example, a hard disk or the like, and stores various data.

In the laser processing apparatus 100 configured as described above, when the laser beam L0 is focused inside the wafer 20, the portion corresponding to the focusing point (at least a part of the focusing area) C of the laser beam L0 is The laser beam L is absorbed, and a modified region 11 is formed inside the wafer 20. The modified region 11 is a region that differs in density, refractive index, mechanical strength, and other physical properties from the surrounding unmodified region. Examples of the modified region 11 include a melt-treated region, a crack region, a dielectric breakdown region, and a refractive index change region. The modified region 11 includes a plurality of modified spots 11s and cracks extending from the plurality of modified spots 11s.

As an example, the operation of the laser processing apparatus 100 when forming the modified region 11 inside the wafer 20 along the line 15 (planned cutting line) for cutting the wafer 20 will be described.

First, the laser processing apparatus 100 rotates the support section 102 so that the line 15 set on the wafer 20 is parallel to the X direction. The laser processing apparatus 100 determines that the convergence point C of the laser beam L0 is a line when viewed from the Z direction based on the image acquired by the infrared imaging unit 108B (for example, the image of the functional element layer included in the wafer 20). The support part 102 is moved along each of the X direction and the Y direction so as to be positioned above the support part 15. The laser processing apparatus 100 is configured to position the condensing point C of the laser beam L0 on the laser beam incident surface based on the image acquired by the visible imaging unit 108A (for example, the image of the laser beam incident surface of the wafer 20). Then, the laser processing head H (that is, the condensing section 106) is moved along the Z direction (height set). The laser processing apparatus 100 moves the laser processing head H along the Z direction so that the condensing point C of the laser beam L0 is located at a predetermined depth from the laser beam incident surface, with this position as a reference.

Next, the laser processing apparatus 100 emits the laser beam L0 from the light source 103, and moves the support section 102 along the X direction so that the condensing point C of the laser beam L0 moves relatively along the line 15. move. At this time, the laser processing apparatus 100 uses the laser beam input surface based on the displacement data of the laser beam incident surface acquired by one of the pair of distance measuring sensors S1 and S2 located on the front side in the processing progress direction of the laser beam L0. The drive mechanism 162 of the light condensing section 106 is operated so that the condensing point C of the light L0 is located at a predetermined depth from the laser light incident surface.

As a result, a row of modified regions 11 is formed along line 15 and at a constant depth from the laser beam incident surface of wafer 20. When the laser beam L0 is emitted from the light source 103 using the pulse oscillation method, a plurality of modification spots 11s are formed in a line along the X direction. One modification spot 11s is formed by irradiation with one pulse of laser light L0. One row of modified regions 11 is a collection of a plurality of modified spots 11s arranged in one row. Adjacent modification spots 11s may be connected to each other or separated from each other depending on the pulse pitch of the laser beam L0 (the value obtained by dividing the relative moving speed of the focal point C with respect to the wafer 20 by the repetition frequency of the laser beam L0). There is also.

As shown in FIGS. 2 and 3, the wafer 20 includes a semiconductor substrate (substrate) 21 and a functional element layer 22. Note that in FIGS. 2 and 3, the configuration of the wafer 20 is shown in a simplified manner. The detailed configuration of the wafer 20 will be described later. The thickness of the wafer 20 is, for example, 775 μm. The semiconductor substrate 21 has a front surface 21a and a back surface 21b. The semiconductor substrate 21 is, for example, a silicon substrate. The semiconductor substrate 21 is provided with a notch 21c indicating the crystal direction. The semiconductor substrate 21 may be provided with an orientation flat instead of the notch 21c. The functional element layer 22 is formed on the surface 21a of the semiconductor substrate 21. The functional element layer 22 includes a plurality of functional elements 22a. The plurality of functional elements 22a are two-dimensionally arranged along the surface 21a of the semiconductor substrate 21. Each functional element 22a is, for example, a light receiving element such as a photodiode, a light emitting element such as a laser diode, a circuit element such as a memory, or the like. Each functional element 22a may be configured three-dimensionally by stacking a plurality of layers.

A plurality of streets 23 are formed on the wafer 20. The plurality of streets 23 are regions exposed to the outside between adjacent functional elements 22a. That is, the plurality of functional elements 22a are arranged adjacent to each other with the streets 23 interposed therebetween. As an example, for a plurality of functional elements 22a arranged in a matrix, the plurality of streets 23 may extend in a grid pattern so as to pass between adjacent functional elements 22a.

As shown in FIGS. 2 and 3, a plurality of lines 15 are set on the wafer 20. As shown in FIGS. The wafer 20 is planned to be cut into functional elements 22a along each of the plurality of lines 15 (that is, to be made into chips for each functional element 22a). Each line 15 passes through each street 23 when viewed from the thickness direction of the wafer 20. As an example, each line 15 extends through the center of each street 23 when viewed from the thickness direction of the wafer 20. Each line 15 is a virtual line set on the wafer 20 by the laser processing apparatus 100. Each line 15 may be a line actually drawn on the wafer 20.

Note that line 15, which is the line to be cut, is used when streets 23 are configured as a pattern as in this embodiment (i.e., when an unnecessary film is removed from streets 23 in advance using a pattern mask, or when an unnecessary film is removed on streets 23 using a pattern mask). It is not limited to what can be visually recognized as in the case where TEG is placed. For example, the street 23 may not be configured as a pattern (the street 23 has the same configuration as the designed active area), and the line 15 may be estimated from the designed reference position. Furthermore, if the wafer is a bare wafer, the design line 15 may be estimated based on the notch or orientation flat.

Next, a laser processing method using the laser processing apparatus 100 will be explained with reference to FIG. 4. FIG. 4 is a flowchart showing a method for processing the wafer 20. The wafer 20 is a wafer from which a plurality of semiconductor chips are obtained by performing an expanding process after the modified region 11 is formed along the line 15.

As shown in FIG. 4, first, the wafer 20 is prepared (step S11). Details of the prepared wafer 20 will be described later. Then, a dicing tape is attached to the back surface 21b of the semiconductor substrate 21 of the wafer 20. Note that before the dicing tape is attached to the wafer 20, a grinding process for grinding the wafer 20 or a grooving process for removing the surface layer of the streets 23 may be performed.

Next, in the laser processing apparatus 100, a modified region 11 is formed inside the wafer 20 along the line 15 by irradiating the wafer 20 with the laser beam L0 along the line 15 (step S12). Here, after the wafer 20 is suctioned and supported by the supporting part 102 with the dicing tape attached to the back surface 21b of the semiconductor substrate 21, the laser beam L0 is applied to the inside of the semiconductor substrate 21 through the dicing tape. The laser beam L0 is irradiated onto the wafer 20 by aligning the focal points of the wafer 20 with the back surface 21b serving as the laser beam entrance surface.

Subsequently, in an expanding device (not shown), the attached dicing tape is expanded (expanding is performed) (step S13). As a result, cracks extend along each line 15 from the modified region 11 formed inside the semiconductor substrate 21 in the thickness direction of the wafer 20, and the wafer 20 is cut along the lines 15. As a result, the wafer 20 is made into chips for each functional element 22a, and a plurality of semiconductor chips are obtained. Specifically, by expanding the dicing tape attached to the wafer 20 on which the modified region 11 has been formed, the chip portion 120x and the separation portion 122 (see, for example, FIG. 10(b); details will be described later) are separated. Separate at intervals to obtain semiconductor chips.

Next, details of the semiconductor chip obtained by the above laser processing method will be explained. In this embodiment, a plurality of semiconductor chips obtained from the wafer 20 have cutout-shaped openings formed therein. Such an opening is formed depending on the application of the semiconductor chip. 5 and 6 are diagrams illustrating usage examples of the semiconductor chip 120 in which the opening 121 is formed. In the example shown in FIG. 5, a semiconductor chip 120 functioning as an optical semiconductor sensor has an opening 121 as a positioning (alignment) part when installed in an optical-related product 400. That is, the semiconductor chip 120 has an opening 121 as a portion fitted into the protrusion 401 of the optical-related product 400. Further, in the example shown in FIG. 6, the semiconductor chip 120 has an opening 121 as a hole through which light output from the light emitting element 500 toward the material 600 passes.

Here, in order to obtain the semiconductor chip 120 in which the opening 121 is formed, it is necessary to separate the part where the opening 121 is formed from the chip part that will become the semiconductor chip 120 (constituting the semiconductor chip 120). There is. In this case, if the portion forming the opening 121 is separated from the above-described chip portion by expanding the wafer 20 in the expansion step, the portion forming the opening 121 comes into contact with the chip portion after separation. It is conceivable that chipping may occur in the semiconductor chip 120.

FIG. 7 is a diagram illustrating the occurrence of chipping. FIG. 7A shows an example in which four chip regions 200 are formed on the wafer 20. The chipping region 200 includes a chip portion 120x that constitutes the semiconductor chip 120 after the expansion process, and a cut-off portion 122 that is a portion that is separated from the chip portion 120x and that forms an opening 121 of the semiconductor chip 120. have. That is, by separating the cutout portion 122 from the chip portion 120x, the semiconductor chip 120 in which the opening portion 121 is formed is obtained. The chip area 200 is approximately rectangular. In the long side direction of the chip area 200, the cut-off portions 122 are formed to be symmetrical (left-right symmetrical) with respect to the center.

As shown in FIG. 7(a), the four chipped regions 200 are separated by diagonal lines passing through the center of the wafer 20 (upper left region, upper right region, lower left region in FIG. 7(a)). area, lower right area). Now, suppose that the dicing tape attached to the wafer 20 is expanded radially from the center of the wafer 20 in an expander (not shown).

In this case, as shown in FIG. 7B, in the upper left chip area 200 in FIG. is possible. Furthermore, as shown in FIG. 7C, in the chip area 200 at the upper right in FIG. Conceivable. Furthermore, as shown in FIG. 7D, in the chip area 200 at the lower left in FIG. Conceivable. Furthermore, as shown in FIG. 7E, in the lower right chip area 200 in FIG. is possible. These contacts are caused, for example, by a larger displacement of a portion of the wafer 20 closer to the outer edge (details will be described later). As described above, in each chip forming region 200, when the cut-off portion 122 comes into contact with the chip portion 120x, there is a possibility that chipping may occur in the semiconductor chip 120 after the expanding process.

The principle of occurrence of chipping will be explained in detail with reference to FIGS. 8 and 9. Note that the chipping generation principle described here is just an example, and is not limited thereto. FIG. 8 is a diagram illustrating the amount of displacement of each part of the wafer 20 in the expanding process. FIGS. 8A and 8B show the state of the wafer 20 when the dicing tape attached to the wafer 20 is expanded in a direction extending radially from the center of the wafer 20. In the expanding process, the center of the wafer 20 and the center of the dicing tape for expanding are generally aligned. Now, suppose that the wafer 20 is provided with chip regions 201 and 202 that are separated from each other and adjacent to each other. The chip area 201 is located closer to the center of the wafer 20 than the chip area 202 is.

Here, the amount of displacement in the expansion process increases as the distance from the center of expansion (here, the center of the wafer 20) increases. Therefore, the amount of displacement of the chipped region 202 is larger than the amount of displacement of the chipped region 201. Although the dicing tape can be expanded and contracted by the expanding process, the chipping regions 201 and 202 of the wafer 20, which are hard enough to be considered as rigid bodies, do not expand and contract (do not deform). The dicing tape on the attachment side also does not expand or contract. Therefore, within the chip area 201, the amount of displacement is constant regardless of the distance from the center of expansion. Similarly, within the chip area 202, the amount of displacement is constant regardless of the distance from the center of expansion. That is, as expressed by the size (thickness) of the arrows of the chipped regions 201 and 202 in FIG. 8(a), a state in which uniform stress is applied is created within one chipped region. .

As a result, the displacement of the chipping region becomes approximately equal to the average value of the displacement of the dicing tape within the range of the chipping region. Therefore, the displacement of the chipped region is determined by the center of gravity model, which is represented by the distance between the center of gravity of the chipped region and the center position of the dicing tape (tape center position). That is, the displacement of the chipped region is approximately proportional to the distance between the center of gravity of the chipped region and the center of the tape. As shown in FIG. 8(b), the displacement of the chipped region 201 is determined by the distance between the gravity center position 201c of the chipped region 201 and the tape center position TC. Further, the displacement of the chipped region 202 is determined by the distance between the gravity center position 202c of the chipped region 202 and the tape center position TC. Now, since the distance between the center of gravity 202c of the chip area 202 and the tape center position TC is greater than the distance between the center of gravity 201c of the chip area 201 and the tape center position TC, A certain chipped region 202 is displaced more toward the expansion direction (towards the outer edge) than the chipped region 201 . Therefore, the chip area 202 has better divisibility (can be neatly divided) compared to the chip area 201.

Based on the above-described center of gravity model, a specific manner in which chipping occurs will be described. FIG. 9 is a diagram illustrating the occurrence of chipping. One chip area 300 is shown in FIG. 9(a). The chipping region 300 includes a chip portion 320x that constitutes a semiconductor chip after the expansion process, and a cut-off portion 322 that is a portion that is separated from the chip portion 320x and forms an opening of the semiconductor chip. There is. The chip portion 320x is arranged to surround the cut-off portion 322, and has a portion 325 closer to the outer edge than the cut-off portion 322 in the radial direction of the wafer 20, and a portion 326 closer to the center. The center of gravity position 320c of the tip portion 320x is located closer to the tape center position TC than the center of gravity position 322c of the separation portion 322. In this case, according to the center of gravity model described above, the amount of displacement of the separation portion 322 in the expansion direction (towards the outer edge) is larger than the amount of displacement of the tip portion 320x. As described above, since the tip portion 320x has a portion 325 on the outer edge side than the cut-off portion 322, the tip portion 320x contacts the cut-off portion 322 having a large displacement at the outer edge side portion 325. In this case, there is a possibility that chipping may occur in the outer edge side portion 325 of the chip portion 320x. Furthermore, the separation portion 322 may not be divided appropriately.

On the other hand, as shown in FIG. 9B, for example, in a wafer 20 in which there is no chip part 420x in the displacement direction (i.e., on the outer edge side) of the cut-off part 422, which has a large displacement amount, in one chip area 200, , the cut-off portion 422 does not come into contact with the chip portion 420x during the expanding process. In this case, chipping does not occur in the chip portion 420x, and the separation portion 422 is appropriately divided. In this way, depending on the arrangement of the chip part and the cut-off part in the chip area, it is possible to suppress the occurrence of chipping in the expanding process. Below, examples of arrangement of chipped regions that suppress chipping will be described with reference to FIGS. 10 to 13.

FIG. 10 is a diagram showing an example of the arrangement of chipped regions 200 in which chipping is suppressed. The arrangement of the chip area 200 of the wafer 20 shown in FIG. 10(a) is similar to the arrangement shown in FIG. 7(a) described above. That is, in the wafer 20 shown in FIG. 10A, one approximately rectangular chip region 200 is provided in each of four regions divided by diagonal lines passing through the center of the wafer 20. Each chip area 200 has a long side extending parallel to one diagonal line, and a short side extending parallel to the other diagonal line. Each chip region 200 is provided with a cut-off portion 122 so as to be symmetrical (left-right symmetrical) with respect to the central portion in the long side direction. The cut-off portion 122 is provided on one end side (the upper side in FIG. 10A) of the chip area 200 in the short side direction.

As shown in FIG. 10(a), such a wafer 20 is expanded in a direction extending radially from the center in an expanding process with its center aligned with the center position TC of the dicing tape. shall be. Now, as shown in the partially enlarged view of FIG. 10A, the center of gravity 120c of the tip portion 120x is located closer to the tape center position TC than the center of gravity 122c of the separation portion 122. In this case, according to the center of gravity model described above, the amount of displacement of the separation portion 122 in the expansion direction (towards the outer edge) is larger than the amount of displacement of the tip portion 120x. Since the upper right portion of the tip portion 120x exists in the displacement direction (that is, the outer edge side) of the cut-off portion 122, the cut-off portion 122 comes into contact with the upper right portion of the tip portion 120x. In this way, if a portion of the tip portion 120x with a small amount of displacement exists in the displacement direction of the separation portion 122 with a large amount of displacement, the separation portion 122 comes into contact with the tip portion 120x. In this case, chipping may occur in the chip portion 120x.

FIGS. 10(b) and 10(c) are diagrams showing the arrangement of chipped regions 200 in which chipping is suppressed. In FIGS. 10(b) and 10(c), the structure of each chipped region 200 is the same as that in FIG. 10(a) described above, but the arrangement of each chipped region 200 is different from that in FIG. 10(a). ing. In the example shown in FIG. 10(b), chip regions 200 are provided in four directions at 45 degrees with respect to a diagonal line passing through the center of the wafer 20. The distances from the center of the wafer 20 to the four chipped regions 200 are the same. The chip area 200 is arranged so that its short side is perpendicular to a radial line passing through the center of the wafer 20 and at an angle of 45 degrees to the diagonal line. Furthermore, the chip area 200 is provided such that the cut-off portion 122 is located on the outer edge side of the wafer 20. In such a configuration, as shown in the partially enlarged view of FIG. 10(b), the center of gravity position 120c of the chip portion 120x and the separation portion 122 are located on a line at 45 degrees diagonally from the tape center position TC. The center of gravity position 122c will be located. Further, the tip portion 120x does not exist in the displacement direction of the separation portion 122, which has a large amount of displacement. For this reason, the separation portion 122 does not come into contact with the chip portion 120x in the expanding process, and occurrence of chipping in the chip portion 120x is suppressed.

In the example shown in FIG. 10(c), four chipped regions 200 are provided by rotating the four chipped regions 200 shown in FIG. 10(b) by 45 degrees. That is, the four chip regions 200 are arranged diagonally. Even in such a configuration, as shown in the partially enlarged view of FIG. 10(c), the center of gravity 120c of the tip portion 120x and the center of gravity 122c of the separation portion 122 are located on the diagonal line. . Further, the tip portion 120x does not exist in the displacement direction of the separation portion 122, which has a large amount of displacement. For this reason, the separation portion 122 does not come into contact with the chip portion 120x in the expanding process, and occurrence of chipping in the chip portion 120x is suppressed.

Incidentally, the occurrence of chipping is suppressed in both the arrangements shown in FIG. 10(b) and FIG. 10(c). In the case of a <100> wafer, (100)), the configuration in FIG. 10(c) is different from 0 degrees (in the case of a crystal direction <100> wafer, (110)) (the cutting direction changes). In stealth dicing to form a modified region, the arrangement shown in FIG. 10(c) is preferable because cutting in the cutting direction (110) is good.

FIG. 11 is a diagram illustrating an example of the arrangement of chipped regions 200 in which chipping is suppressed. As described with reference to FIG. 10, for the chipped region 200 having the symmetrical cut-off portions 122, chipping can be effectively suppressed by providing four chipped regions 200 diagonally, for example. did it. Here, as shown in the partially enlarged view of FIG. 11(a), even if the chipped region 200 in which the left-right asymmetrical cut-off portions 122 are provided diagonally, chipping may occur. There are cases where the cut-off portion 122 is left undivided.

In the chip forming region 200 provided with such a left-right asymmetric cut-out portion 122, the center line of the opening angle of the portion that will become the opening after the expanding process is located on a line that radiates from the center of the wafer 20. , angle (see FIG. 11(b)) or position (see FIG. 11(c)) are set. This can suppress the occurrence of chipping and the undivided portion 122.

The center line of the opening angle of the portion that will become the opening after the expanding process will be explained in detail. As described above, the cutout portion 122 is a portion that forms the opening 121 of the semiconductor chip 120. “The center line of the opening angle of the portion that will become the opening” is the intersection of the two sides (two sides when the wafer 20 is viewed from above) connected to the opening end of the cut-off portion 122 extending toward the center of the wafer 20. , can be rephrased as a line connecting the midpoint of the opening end. In the example shown in FIG. 11(b), the center line of the opening angle of the portion that will become the opening is located on a line that radiates from the center of the wafer 20 (that is, connected to the center of the wafer 20, and 11A), each chip area 200 is arranged at an angle (specifically, at an angle of 8 degrees) from the state shown in FIG. 11A. In the example shown in FIG. 11C, the center line of the aperture angle of the portion that will become the opening is located on a line that radiates from the center of the wafer 20 (that is, connected to the center of the wafer 20, Each chip area 200 is arranged to be shifted in the circumferential direction from the state shown in FIG. 11(a) so as to match the displacement vector in the expansion process).

FIG. 12 is a diagram illustrating various arrangement examples of chip regions. In each of the chipping regions shown in FIGS. 12(a) to 12(i), the chip portion 120x is located closer to the center of the wafer than the cut-off portion 122 is.

In the example shown in FIG. 12(a), the chip area has left-right symmetrical cut-off portions 122. The separation portion 122 is provided so that the width of the opening 121 increases toward the opening end side (the outer edge side of the wafer). By providing the cut-off portion 122 such that the width of the opening 121 increases toward the open end side, it is possible to improve the divisibility of the cut-off portion 122 while appropriately suppressing the occurrence of chipping. can.

In the example shown in FIG. 12(b), the chip area has a cut-off portion 122 that is asymmetrical. Although the separation portion 122 is provided so that the width of the opening 121 increases toward the opening end side (towards the outer edge of the wafer), the opening width is narrower than in the configuration shown in FIG. 12(a). . As described above, by adjusting the angle (see FIG. 11(b)) or position (see FIG. 11(c)) of the asymmetric cut-off portion 122, it is possible to suppress the occurrence of chipping. can. Furthermore, the divisibility of the cut-off portion 122 can also be ensured, although it is inferior to the configuration of FIG. 12(a) because the opening width is narrow.

In the example shown in FIG. 12(c), the chip area has a circular cut-off portion 122. In the example shown in FIG. When forming a modified region along the line of such a circular cut-off part 122, for example, a linear processing stage is used to process a plurality of tangents, and the plurality of tangents are connected to form a substantially circular shape. do. With such a configuration as well, it is possible to improve the divisibility of the separation portion 122 while appropriately suppressing the occurrence of chipping.

In the example shown in FIG. 12(d), the chip area has a triangular cut-off portion 122 that widens toward the open end side (the outer edge side of the wafer). With such a triangular cut-off part 122, it is possible to suppress the occurrence of chipping and to divide the cut-off part 122, but since the center side of the wafer (triangular tip side) is sharp, If the direction of expansion is different from expected, there is a risk of immediate chipping.

In the example shown in FIGS. 12(e) and 12(f), the cut-off portion 122 is provided so that the width of the opening 121 becomes constant toward the opening end side (the outer edge side of the wafer). Although such a separation part 122 cannot be divided only by the expanding process, it can be appropriately divided by performing etching before the expanding process. When an etching process is performed, for example, after forming a modified region on the wafer 20 by laser beam incidence from the back surface 21b, etching is performed on the entire surface of the wafer 20 from the back surface 21b, and then a tape is applied to the back surface 21b. Paste it and perform the expansion process. Note that in the etching process, a mask may be attached for selective etching, and etching of only the dicing streets or etching of only the opening lines 152 (see FIG. 16) to be described later may be performed. Further, etching may be performed from the surface 21a with a mask attached to protect the surface.

In the example shown in FIG. 12(g), the cut-off portion 122 is provided so that the width of the opening 121 becomes narrower toward the opening end side (the outer edge side of the wafer). Regarding such a cut-off portion 122, the cut-off portion 122 cannot be divided by an expanding process.

In the example shown in FIG. 12(h), two cut-off portions 122 are provided corresponding to one chip portion 120x. In this way, a plurality of cut-off parts 122 may be provided for one chip part 120x.

In the example shown in FIG. 12(i), the shape of the chip portion 120x is not rectangular but includes an irregular shape. Even when such a chip portion 120x is used, the divisibility of the separation portion 122 can be improved while appropriately suppressing the occurrence of chipping.

FIG. 13 is a diagram showing an example of arrangement of chipped regions in which chipping is suppressed. In the example shown in FIG. 13, four chip regions 200 are provided on a diagonal line passing through the center of the wafer 20. In the example shown in FIG. In each chip region 200, the chip portion 120x is located closer to the outer edge of the wafer 20 than the cut-off portion 122 is. The width of the cut-off portion 122, which becomes the opening, is formed to increase toward the center of the wafer 20. In the example shown in FIG. 13, the tip portion 120x exists on the outer edge side, and the amount of displacement of the tip portion 120x is larger than the amount of displacement of the cut-off portion 122 in the expanding process. In this case, in the expanding step, the separation portion 122 is unlikely to come into contact with the chip portion 120x, and the occurrence of chipping in the chip portion 120x is suppressed.

Next, an example of the expanding process will be described with reference to FIGS. 14 and 15. FIG. 14 is a diagram illustrating an example of an expanding process. In the example shown in FIG. 14, in the wafer 20, a plurality of chipped regions are arranged radially from the center of the wafer 20, and the chip portion 120x and the cut-off portion 122 are arranged on a line radially extending from the center of the wafer 20. They are arranged in consecutive order. In the expanding process for such a wafer 20, as shown in FIG. be done. In this case, since the tip portion 120x does not exist in the displacement direction of the cut-off portion 122 which is arranged on the outer edge side and has a large displacement amount, it is possible to suppress the occurrence of chipping of the tip portion 120x and to reliably divide the cut-off portion 122. .

FIG. 15 is a diagram illustrating another example of the expanding process. In the example shown in FIG. 15, in the wafer 20, five chipped regions 200 are provided in the upper direction in FIG. 15, and five chipped regions 200 are provided in the lower direction. In the chip area 200 in the upward direction, a cut-off portion 122 is provided on the upper side, and a chip portion 120x is continuously provided on the lower side. Furthermore, in the downward chipping region 200, a cut-off portion 122 is provided on the lower side, and a chip portion 120x is continuously provided on the upper side. For such a wafer 20, in the expansion process, the dicing tape is expanded in one direction (CH1) in which the cut-off part 122 and the chip part 120x are continuous, as shown in FIG. 15(a), for example. be done. Thereafter, for example, as shown in FIG. 15(b), the dicing tape is expanded in the direction (CH2) intersecting CH1. In this way, the expansion process may be realized by sequentially expanding in the CH1 and CH2 directions.

Next, an example of setting the line 15 (planned cutting line) for cutting the wafer 20 will be described with reference to FIGS. 16 to 18. FIG. 16 is a diagram showing an example of setting the line 15. The wafer 20 shown in FIG. 16 is the same wafer as the left-right asymmetric wafer 20 shown in FIG. 11(c) described above.

The line 15 includes a chip partition line 151 that partitions each chip region 200, and an opening line 152 that is set so that a notch-shaped opening is formed in the semiconductor chip. The chip portion 120x and the cut-off portion 122 are provided continuously via the opening line 152. The opening line 152 is set so that contact between the chip portion 120x and the cut-off portion 122 is avoided during the expanding process.

As shown in FIG. 16, the chip partition line 151 includes a first line 151a, a second line 151b, a third line 151c, and a fourth line 151d. The first line 151a and the second line 151b are planned cutting lines that extend in parallel to each other in the vertical direction in FIG. 16. One end of each of the first line 151a and the second line 151b extends to the outer edge of the wafer 20. The third line 151c is a scheduled cutting line that is continuous with the other end of the first line 151a (the end on the center side of the wafer 20) and extends in the lateral direction in FIG. 16 to a point where it intersects with the second line 151b. It is. The fourth line 151d is a scheduled cutting line that extends in the lateral direction in FIG. 16 parallel to the third line 151c. The fourth line 151d includes a portion extending from the first line 151a to a first line 152a (described later) of the opening line 152 and a portion extending from the second line 151b to a second line 152b (described later) of the opening line 152. There is. The fourth line 151d does not cross the separation part 122, and extends only to the point where it intersects with the first line 152a and the point where it intersects with the second line 152b.

The opening line 152 is set so that the width of the opening (that is, the width of the cut-off portion 122) increases toward the opening end. As in the wafer 20 shown in FIG. 16, the opening line 152 of the chipping region 200 in which the chip portion 120x is located closer to the center of the wafer 20 than the cut-off portion 122 is such that the width of the opening increases toward the outer edge of the wafer 20. As such, it is set. Note that, as in the wafer 20 shown in FIG. 13, the opening line 152 of the chip area 200 in which the chip portion 120x is located closer to the outer edge of the wafer 20 than the separation portion 122 is such that the width of the opening portion increases toward the center of the wafer 20. It is set so that it spreads out.

As shown in FIG. 16, the opening line 152 includes a first line 152a, a second line 152b, a third line 152c, and a fourth line 152d. The first line 152a is a planned cutting line that extends in the vertical direction in FIG. 16 parallel to the first line 151a. The first line 152a has one end (corresponding to the opening end of the opening) extending to the outer edge of the wafer 20, and the other end extending to a position corresponding to the base end of the opening. The second line 152b is a scheduled cutting line that extends to the outer edge of the wafer 20 such that the closer it gets to the outer edge of the wafer 20, the further away from the first line 152a. The third line 152c is a scheduled cutting line that continues to the other end of the first line 151a and extends in the lateral direction in FIG. 16. The fourth line 152d is a scheduled cutting line that extends to connect the third line 152c and the second line 152b.

The aperture line 152 is set such that the center line CL of the aperture angle of the aperture is located on a line radially extending from the center of the wafer 20 (that is, the center position TC of the dicing tape).

FIG. 17 is a diagram showing another example of setting the line 15. The line 15 shown in FIG. 17 is generally similar to the line 15 shown in FIG. There is. In the configuration shown in FIG. 17, the fourth line 151d extends across the separation portion 122, so that the separation portion 122 is vertically separated. In this case, when comparing the configuration shown in FIG. 16 and the configuration shown in FIG. 17, in the configuration shown in FIG. Become. In this manner, from the viewpoint of the divisibility of the separation part 122, it is preferable that the chip partition line 151 is set so as not to cross the separation part 122.

FIG. 18 is a diagram showing another example of setting the line 15. The line 15 shown in FIG. 18 is generally similar to the line 15 shown in FIG. 16, but differs in that the third line 151c and the fourth line 151d extend to the outer edge of the wafer 20. The third line 151c has one end extending to a third line 1151c of another adjacent chip area 200, and the other end extending to the outer edge of the wafer 20. Furthermore, both ends of the fourth line 151d extend to the outer edge of the wafer 20. In the configuration shown in FIG. 18, the number of scheduled cutting lines increases, and the wafer 20 is divided into smaller pieces. Comparing the configuration shown in FIG. 16 and the configuration shown in FIG. 18, the configuration shown in FIG. 16 has higher divisibility from the viewpoint of the center of gravity model described above. In this way, by minimizing the number of scheduled cutting lines, the divisibility in the expanding process is improved. Further, the configuration shown in FIG. 16 has the advantage that the number of cuts is small and the chip size can be increased. On the other hand, in the configuration shown in FIG. 16, depending on the order of cracks on the planned cutting line, the center of gravity position changes moment by moment and the direction of movement changes (chip rotates), which can prevent chipping during the expanding process. This may occur. In this respect, for example, as in the configuration shown in FIG. 18, by increasing the number of scheduled cutting lines, the risk of chipping due to tip rotation can be reduced. Note that when increasing the number of scheduled cutting lines, it is preferable to increase the number of scheduled cutting lines related to locations where chipping actually occurs.

Next, details of processing the opening line 152 will be explained with reference to FIGS. 19 and 20. FIG. 19 is a diagram illustrating the processing order of the opening line 152. 19(b) to 19(i) show the processing order of the opening line 152 of one chip area 200 included in the wafer 20 shown in FIG. 19(a). In FIGS. 19(b) to 19(i), broken lines indicate lines that have not been laser processed, and solid lines indicate lines that have been laser processed.

As shown in FIG. 19(b), first, a wafer 20 on which opening lines 152 (first line 152a, second line 152b, third line 152c, fourth line 152d) to be laser processed are set is prepared. Ru.

Subsequently, as shown in FIG. 19(c), a modified region is formed along the first line 152a. The first line 152a extends to the outer edge of the wafer 20. The inside of the first line 152a (the center side of the wafer 20) is a part where it is desired to prevent the cracks related to the formation of the modified region from extending (to stop the cracks). Therefore, the first line 152a is irradiated with laser light from the inside to the outside to form a modified region. In this case, for example, the condensing point C is relative to the base end of the first line 152a, and then the tip of the first line 152a (outer edge of the wafer 20) from inside the base end (inner end) of the first line 152a. The support portion 102 (see FIG. 1) is moved so as to move the target. A section inside the base end of the first line 152a is a laser OFF section 152x in which the laser is turned off.

Subsequently, as shown in FIG. 19(d), a modified region is formed along the second line 152b. The second line 152b extends to the outer edge of the wafer 20. The inside of the second line 152b is a portion where cracks related to formation of the modified region are not desired to extend. Therefore, the second line 152b is irradiated with laser light from the inside to the outside to form a modified region. In this case, the section inside the base end (inner end) of the second line 152b is the laser OFF section 152x, and the laser OFF section 152x, the base end of the second line 152b, and the tip of the second line 152b are arranged in this order. The support part 102 (see FIG. 1) is moved so that the focal point C moves relatively. Through the processing up to this point, modified regions along the first line 152a and the second line 152b are formed (see FIG. 19(e)).

Subsequently, as shown in FIG. 19(f), a modified region is formed along the third line 152c. Regarding the third line 152c, a laser beam is irradiated toward the first line 152a, which is a processed line, to form a modified region. In this case, the section on the right side of the third line 152c (the end opposite to the first line 152a side) in FIG. The section to the left in FIG. 19(f) from the end of The support part 102 (see FIG. 1) is moved so that the focal point C moves relatively.

Subsequently, as shown in FIG. 19(g), a modified region is formed along the fourth line 152d. Regarding the fourth line 152d, a laser beam is irradiated toward the second line 152b, which is a processed line, to form a modified region. In this case, the section on the lower left side in FIG. 19(g) from the base end of the fourth line 152d (the end on the third line 152c side), and The upper right section in FIG. 19(g) is defined as the laser OFF section 152x, and the laser OFF section 152x, the base end of the fourth line 152d, the tip of the fourth line 152d, and the laser OFF section 152x are collected in this order. The support part 102 (see FIG. 1) is moved so that the light spot C moves relatively. By the processing up to this point, all the modified regions along the opening line 152 are formed (see FIG. 19(h)).

Finally, as shown in FIG. 19(i), a modified region is formed along the fourth line 151d of the chip partition line 151. Note that the formation of the modified region along the fourth line 151d may be performed before the formation of the third line 152c and the fourth line 152d, which are the opening lines 152. The modified region is formed along the fourth line 151d so as to straddle the cut-off portion 122. That is, the section that crosses the separation part 122 is defined as the laser OFF section 152x, and the section of the fourth line 151d toward the first line 152a, the section that crosses the separation part 122, and the section that extends outward from the second line 152b of the fourth line 151d. The support part 102 (see FIG. 1) is moved so that the condensing point C moves relatively in the order of the sections toward which it is directed. In this case, since the first line 152a and the second line 152b have already been formed, it is assumed that the cracks associated with the formation of the modified region along the fourth line 151d will stop at the first line 152a and the second line 152b. be done. Through the processing up to this point, a modified region along the opening line 152 and the fourth line 151d is formed (see FIG. 19(j)).

FIG. 20 is a diagram illustrating laser beam irradiation at each processing location. 20(a), 20(b), 20(c), and 20(d) show laser processing of the first line 152a, second line 152b, third line 152c, and fourth line 152d, respectively. It shows. In each case, the upper row shows laser processing along the line, and the lower row shows the laser beam irradiation state.

As shown in the lower part of FIGS. 20(a) and 20(c), when laser processing is performed in the same direction as the crystal direction (110) (i.e., 90 degrees or 0 degrees), or as shown in FIG. 20(d) As shown in the lower part of the figure, when laser processing is performed in the direction of 45 degrees to the crystal direction (110), the processing progresses by matching the processing direction and the beam shape of the elliptical laser beam. Laser processing along the direction can be realized.

On the other hand, as shown in the lower part of FIG. 20(b), when laser processing is performed in directions other than 90 degrees, 0 degrees, and 45 degrees with respect to the crystal direction (110), An elliptical laser beam is irradiated in the direction opposite to the crystal direction. Here, the direction opposite to the crystal direction side means the direction opposite to the direction in which the cleavage plane closest to the processing direction is located. Thereby, the laser beam can be irradiated in a desired processing progress direction, taking into account that the laser beam is bent (pulled) toward the crystal direction.

Note that from the viewpoint of suppressing chipping, it is preferable that the separation portion 122 is separated early in the expanding process. Therefore, in order to reliably separate the separation portion 122 at an early stage, the laser processing conditions for the aperture line 152, which is the line to be cut related to the separation portion 122, are set to be lower than the laser processing conditions for the chip partition line 151, which is the other line to be cut. Also, the laser processing conditions may be such that it is easy to divide. Specifically, the number of laser beam scans when forming the modified region along the opening line 152 is set to be greater than the number of laser beam scans when forming the modified region along the chip partition line 151. may be done.

FIG. 21 is a diagram illustrating processing conditions for the opening line 152 and the chip partition line 151. 21(a) shows the wafer 20 to be processed, FIG. 21(b) shows the opening line 152 of the chip area 200 of the wafer 20, and FIG. 21(c) shows the opening line 152 of the chip area 200 of the wafer 20. The processing conditions for the opening line 152 (and the processing results based on the processing conditions) are shown, and FIG. 21(d) shows the chip division line 151 of the chip area 200 of the wafer 20. ) shows the machining conditions of the chip division line 151 (and the machining results based on the machining conditions).

As shown in FIGS. 21(c) and 21(d), for example, in processing a 400 μm wafer 20, the conditions such as wavelength (1080 nm) are such that laser processing along the aperture line 152 and laser processing along the chip partition line 151 are performed. It is said to be common with laser processing. On the other hand, as shown in FIG. 21(c), the number of scans is 5 passes (SD1 to SD5 in FIG. 21(c)) in laser processing along the aperture line 152, whereas the number of scans is 5 passes (SD1 to SD5 in FIG. 21(c)). In the laser processing along the line 151, the number of scans is 4 passes (SD1 to SD4). In this way, the number of laser beam scans when forming the modified region along the opening line 152 is set to be greater than the number of laser beam scans when forming the modified region along the chip partition line 151. By doing so, the separation portion 122 can be separated at an early stage. Note that terms such as "Z80" and "Z75" in FIGS. 21(c) and 21(d) are information on the Z height, which is the processing depth when laser processing is performed.

Next, the effects of the wafer 20 and processing method according to this embodiment will be explained.

The wafer 20 according to the present embodiment is a wafer in which a plurality of semiconductor chips 120 are obtained by performing an expanding process after a modified region is formed along a line 15, and the chip partition line is the line 15. The chip area 200 includes a chip part 120x that constitutes the semiconductor chip 120, and a part that is separated from the chip part 120x. It has a cut-off part 122 that is continuous to the chip part 120x via an opening line 152, which is a line 15 set so that the opening part 121 is formed, and the opening line 152 is such that the width of the opening part 121 is equal to the opening end. It is set so that it spreads toward the sides or remains constant.

In the wafer 20 according to the present embodiment, in the chip forming region 200, the chip portion 120x and the cut-off portion 122 are continuously connected via the opening line 152, which is the line 15 related to the formation of the opening 121 of the semiconductor chip 120. It is formed. In the present wafer 20, the opening line 152 is set so that the width of the opening 121 increases toward the opening end or remains constant. By setting the opening line 152 in this way, when a modified region is formed along the opening line 152 and an expanding process is performed, the chip portion 120x (semiconductor chip 120) and the chip portion 120x Contact with the separation portion 122 that is separated from the semiconductor chip 120 is suppressed. Thereby, occurrence of chipping in the semiconductor chip 120 can be effectively suppressed.

In the wafer 20 described above, in the opening line 152 of the chip forming region 200 where the chip portion 120x is located closer to the center of the wafer 20 than the cut-off portion 122, the width of the opening portion 121 increases toward the outer edge of the wafer 20 or remains constant. The opening line 152 of the chip forming region 200 where the chip portion 120x is located closer to the outer edge of the wafer 20 than the cut-off portion 122 is set as shown in FIG. It may be set to be constant.

According to such a configuration, the chip portion 120x is separated from the chip portion 120x both when the chip portion 120x is located closer to the center of the wafer 20 than the separating portion 122 and when it is located closer to the outer edge of the wafer 20. Contact with the cut-off portion 122 can be appropriately suppressed. Note that in the expanding process, the displacement of the portion far from the center of the wafer 20 (that is, the outer edge side of the wafer 20) is larger; however, in a configuration in which the chip portion 120x is closer to the center of the wafer 20 than the separation portion 122, The separation portion 122 can be effectively displaced in the direction in which the separation is desired (toward the outer edge of the wafer 20, which is the direction away from the chip portion 120x), which improves the separation property of the separation portion 122 and prevents chipping in the semiconductor chip 120. The occurrence can be suppressed more effectively.

In the wafer 20 described above, the opening line 152 of the chip area 200 close to the outer edge of the wafer 20 may extend to the outer edge of the wafer 20. By extending the opening line 152 to the outer edge of the wafer 20 in this manner, the separation property of the separation portion 122 can be improved, and the occurrence of chipping in the semiconductor chip 120 can be more effectively suppressed.

In the wafer 20 described above, the chip partition line 151 may extend to the outer edge of the wafer 20. In this way, by extending the chip division line 151 to the outer edge of the wafer 20, the divisibility of the chip portion 120x can be improved.

In the wafer 20, the plurality of chip regions 200 are arranged radially from the center of the wafer 20, and the chip portions 120x and the cut-off portions 122 are sequentially provided on a line radially extending from the center of the wafer 20. It may be. When a device that expands the wafer 20 radially is used as the expander, a plurality of chip regions 200 are arranged radially from the center of the wafer 20, and the chip portion 120x and the cut-off portion 122 are separated from each other on the wafer 20. Since the chip portions 120x and cut-off portions 122 of the plurality of chip regions 200 are arranged in succession on a line radially extending from the center, the chip portions 120x and cut-off portions 122 of a plurality of chip regions 200 are arranged in the expansion direction. By expanding such a wafer 20 using the above-mentioned expander, it is possible to improve the divisibility and effectively suppress the occurrence of chipping in the semiconductor chips 120.

In the wafer 20 described above, the opening line 152 may be set such that the center line of the opening angle of the opening 121 is located on a line that radiates from the center of the wafer 20. When a device that expands the wafer 20 radially is used as the expander, the center line of the opening angle of the opening 121 is located on a line that extends radially from the center of the wafer 20, so that the chip portion 120x and the separation portion are separated. The chip portion 120x and the separation portion 122 can be separated while appropriately suppressing contact with the chip portion 120x. In other words, occurrence of chipping in the semiconductor chip 120 can be more effectively suppressed.

The opening line 152 may be set so as to avoid contact between the chip portion 120x and the cut-off portion 122 during the expanding process. By setting the opening line 152 in this way, when a modified region is formed along the opening line 152 and an expanding process is performed, contact between the chip part 120x and the cut-off part 122 is suppressed. be done. Thereby, occurrence of chipping in the semiconductor chip 120 can be effectively suppressed.

The method for processing a wafer 20 according to the present embodiment has a plurality of chip forming regions 200 divided by a chip dividing line 151 which is a line 15, and the chip forming region 200 is connected to a chip portion 120x constituting a semiconductor chip 120. , a cut-off portion 122 that is separated from the chip portion 120x and continues to the chip portion 120x via an opening line 152, which is a line 15 set so that a notch-shaped opening 121 is formed in the semiconductor chip 120. a step of preparing a wafer 20 having the following steps, a step of irradiating a laser beam along the line 15 to form a modified region, and expanding a dicing tape attached to the wafer 20 on which the modified region has been formed. The method includes a step of separating the chip portion 120x and the cut-off portion 122 at an interval to obtain the semiconductor chip 120.

In the method for processing the wafer 20 according to the present embodiment, in the chip forming region 200, the chip portion 120x and the separation portion 122 are connected to each other via the opening line 152, which is the line 15 related to the formation of the opening 121 of the semiconductor chip 120. A continuously formed wafer 20 is prepared. Then, a modified region is formed along the line 15 on the wafer 20, and the dicing tape attached to the wafer 20 is expanded, thereby obtaining the semiconductor chip 120. Here, in this processing method, in the step of obtaining the semiconductor chip 120, the chip portion 120x and the cut-off portion 122 are separated with an interval between them. This suppresses contact between the chip portion 120x (semiconductor chip 120) and the separation portion 122 that is separated from the chip portion 120x (semiconductor chip 120), and effectively prevents chipping from occurring in the semiconductor chip 120. Can be suppressed.

In the above processing method, the plurality of chip regions 200 are arranged radially from the center of the wafer 20, and the chip portions 120x and the cut-off portions 122 are sequentially provided on a line that extends radially from the center of the wafer 20. In the expanding process, the dicing tape attached to the wafer 20 may be expanded in a direction extending radially from the center of the wafer 20. As a result, the direction in which the chip portion 120x and the separation portion 122 are successively provided can be aligned with the expansion direction, improving the divisibility and effectively suppressing the occurrence of chipping in the semiconductor chip 120. can do.

In the above processing method, the opening line 152 of the chip area 200 close to the outer edge of the wafer 20 may extend to the outer edge of the wafer 20. By extending the opening line 152 to the outer edge of the wafer 20 in this manner, the separation property of the separation portion 122 can be improved, and the occurrence of chipping in the semiconductor chip 120 can be more effectively suppressed.

In the above processing method, in the step of forming the modified region, the modified region is formed by irradiating the opening line 152 extending to the outer edge of the wafer 20 with laser light from the inside to the outside of the opening line 152. Good too. According to such a configuration, cracks caused by the formation of the modified region can be stopped inside the opening line 152 and extended outside the opening line 152. Thereby, cracks can be appropriately stopped at the portion where cracks are to be stopped (inside the opening line 152 that will become the semiconductor chip 120).

In the above processing method, in the step of forming the modified region, an elliptical laser beam may be irradiated in a direction opposite to the crystal direction with respect to the processing progress direction. Regarding the laser beam, it may be bent toward the crystal direction (pulled toward the crystal direction). The laser beam can be irradiated in a desired direction of processing, taking into account the bending toward the crystal direction. That is, according to such a configuration, formation of the modified region along the line 15 can be realized.

In the above processing method, in the step of forming the modified region, the number of scans of the laser beam when forming the modified region along the opening line 152 is equal to the number of scans of the laser beam when forming the modified region along the chip partition line 151. The number may be set to be greater than the number of laser beam scans. According to such a configuration, the number of laser beam scans for cutting off the cutting portion 122 is greater than the number of laser beam scans for cutting the chip portion 120x from the wafer 20, and when the wafer 20 is expanded, the number of laser beam scans is greater than the number of laser beam scans for cutting the chip portion 120x from the wafer 20. The portion 122 can be separated at an early stage. By separating the cut-off portion 122 at an early stage, the center of gravity of the wafer 20 can be determined early, and by repeating the movement of the center of gravity, the cut-off portion 122 and the chip portion 120x easily come into contact with each other, thereby preventing chipping on the semiconductor chip 120. It is possible to avoid a situation where this occurs.

In the above processing method, the chip partition line 151 may extend to the outer edge of the wafer 20. In this way, by extending the chip division line 151 to the outer edge of the wafer 20, the divisibility of the chip portion 120x can be improved.

The above processing method includes the steps of preparing the wafer 20 described above, forming a modified region along the line 15, and expanding the dicing tape attached to the wafer 20 on which the modified region has been formed. , and obtaining a plurality of semiconductor chips 120. According to such a method of processing the wafer 20, contact between the chip portion 120x (semiconductor chip 120) and the separation portion 122 that is separated from the chip portion 120x (semiconductor chip 120) is suppressed, and chipping (chipping) of the semiconductor chip 120 is prevented. ) can be effectively suppressed from occurring.

15... Line (planned cutting line), 20... Wafer, 100... Laser processing device, 120... Semiconductor chip, 120x... Chip part, 121... Opening part, 122... Cutting part, 151... Chip division line, 152... Opening line, 200...chip area.

Claims (15)

A wafer in which a plurality of semiconductor chips are obtained by performing an expanding process after a modified region is formed along a scheduled cutting line, the wafer comprising:
It has a plurality of chipping regions partitioned by a chip partitioning line which is the planned cutting line,
The chip area is
a chip portion constituting the semiconductor chip;
a separation portion that is a portion that is separated from the chip portion and that is continuous to the chip portion via an opening line that is the scheduled cutting line that is set so that a notch-shaped opening is formed in the semiconductor chip; has
In the wafer, the opening line is set such that the width of the opening widens toward the opening end side or becomes constant. The opening line of the chipping region in which the chip portion is located closer to the center of the wafer than the separation portion is set such that the width of the opening increases toward the outer edge of the wafer or remains constant. and
The opening line of the chip forming region in which the chip portion is located closer to the outer edge of the wafer than the separation portion is set such that the width of the opening increases toward the center of the wafer or remains constant. The wafer according to claim 1, wherein the wafer comprises: 3. The wafer according to claim 1, wherein the opening line of the chipping region close to the outer edge of the wafer extends to the outer edge of the wafer. 3. The wafer according to claim 1, wherein the chip partition line extends to an outer edge of the wafer. The plurality of chipped regions are arranged radially from the center of the wafer,
3. The wafer according to claim 1, wherein the chip portion and the separation portion are successively provided in order on a line radially extending from the center of the wafer. 3. The wafer according to claim 1, wherein the opening line is set such that a center line of the opening angle of the opening is located on a line that radiates from the center of the wafer. A wafer in which a plurality of semiconductor chips are obtained by performing an expanding process after a modified region is formed along a scheduled cutting line, the wafer comprising:
It has a plurality of chipping regions partitioned by a chip partitioning line which is the planned cutting line,
The chip area is
a chip portion constituting the semiconductor chip;
a separation portion that is a portion that is separated from the chip portion and that is continuous to the chip portion via an opening line that is the scheduled cutting line that is set so that a notch-shaped opening is formed in the semiconductor chip; has
In the wafer, the opening line is set so as to avoid contact between the chip portion and the separation portion during an expanding process. It has a plurality of chip forming areas partitioned by chip dividing lines which are planned cutting lines, and the chip forming areas are a chip part constituting a semiconductor chip and a part to be separated from the chip part, and the chip forming area is a part that is separated from the chip part and is cut into a semiconductor chip. preparing a wafer having a cut-off portion that is continuous to the chip portion via the opening line that is the cut line set so that a cut-out-shaped opening is formed;
irradiating a laser beam along the planned cutting line to form a modified region;
the step of separating the chip portion and the separation portion at a distance by expanding a tape attached to the wafer on which the modified region is formed, thereby obtaining the semiconductor chip; Processing method. The plurality of chipped regions are arranged radially from the center of the wafer,
The chip portion and the separation portion are successively provided in order on a line radially extending from the center of the wafer,
9. The processing method according to claim 8, wherein in the expanding step, the tape attached to the wafer is expanded in a direction extending radially from the center of the wafer. 10. The processing method according to claim 8, wherein the opening line of the chipping region close to the outer edge of the wafer extends to the outer edge of the wafer. 11. In the step of forming the modified region, the modified region is formed by irradiating the opening line extending to the outer edge of the wafer with laser light from the inside to the outside of the opening line. processing method. 10. The processing method according to claim 8, wherein in the step of forming the modified region, an elliptical laser beam is irradiated in a direction opposite to the crystal direction with respect to the direction in which the opening line moves. In the step of forming the modified region, the number of laser beam scans when forming the modified region along the opening line is equal to the number of laser beam scans when forming the modified region along the chip partition line. The processing method according to claim 8 or 9, wherein the processing method is set to be larger than the number. 10. The processing method according to claim 8, wherein the chip partition line extends to an outer edge of the wafer. A step of preparing a wafer according to claim 1 or 2;
forming a modified region along the planned cutting line;
A method for processing a wafer, the method comprising: obtaining the plurality of semiconductor chips by expanding a tape attached to the wafer in which the modified region is formed.

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