TW202347470A - Wafer and wafer processing method in which a plurality of semiconductor chips is obtained by performing an expansion process after forming a modified region along the line - Google Patents

Wafer and wafer processing method in which a plurality of semiconductor chips is obtained by performing an expansion process after forming a modified region along the line Download PDF

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TW202347470A
TW202347470A TW112117113A TW112117113A TW202347470A TW 202347470 A TW202347470 A TW 202347470A TW 112117113 A TW112117113 A TW 112117113A TW 112117113 A TW112117113 A TW 112117113A TW 202347470 A TW202347470 A TW 202347470A
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wafer
line
opening
wafering
modified region
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坂本剛志
名倉圭介
山本和馬
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日商濱松赫德尼古斯股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)

Abstract

This invention relates to a wafer and a wafer processing method. The wafer is a wafer in which a plurality of semiconductor chips is obtained by performing an expansion process after forming a modified region along the line. The wafer has a plurality of chip-formed regions divided by chip dividing lines as lines. The chip-formed region has a chip portion, which constitutes a semiconductor chip; and a dicing portion, which is a portion cut from the chip portion and is continuous with the chip portion via an opening line. The opening line is a line set so as to form a slit-shaped opening portion on the semiconductor chip, and the opening line is set such that the width of the opening portion expands toward the opening end side or becomes constant.

Description

晶圓及晶圓的加工方法Wafers and wafer processing methods

本發明的一個方式關於一種晶圓及晶圓的加工方法。One aspect of the present invention relates to a wafer and a wafer processing method.

已知藉由分割晶圓而得到多個半導體晶片的方法。例如，在專利文獻1(日本特開2011-146717號公報)中，公開了藉由對晶圓進行乾蝕刻，分割晶圓，從晶圓得到多個半導體晶片的方法。此外，在專利文獻2(日本特開 2012-028452號公報)中，公開了藉由對晶圓進行雷射照射而在晶圓內部形成改質區域，藉由擴張貼附於形成了改質區域的晶圓的帶，從晶圓得到多個半導體晶片的方法。 A method of obtaining a plurality of semiconductor wafers by dividing a wafer is known. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2011-146717) discloses a method of dry etching a wafer to divide the wafer and obtain a plurality of semiconductor wafers from the wafer. Furthermore, in Patent Document 2 (Japanese Patent Application Laid-Open Publication No. 2012-028452) discloses that a modified region is formed inside the wafer by irradiating the wafer with laser, and a tape attached to the wafer in which the modified region is formed is expanded to obtain the modified region from the wafer. Multiple semiconductor wafer methods.

在半導體晶片，存在形成有切口形狀的開口部的情況。這樣的開口部例如在光關聯產品中以設置半導體晶片時的定位(對準)用途、或者使來自發光元件的光通過的孔的用途而形成。例如，在晶圓分割時，藉由將半導體晶片和形成開口部的部分分離，得到形成有開口部的半導體晶片。 在此，例如，在藉由擴張形成了改質區域的晶圓而得到多個半導體晶片的方法中，存在由於晶圓的擴張使從半導體晶片分離的部分(形成開口部的部分)接觸於半導體晶片，而在半導體晶片產生碎片(chipping)(破片)的情況。 本發明的一個方式鑒於上述實際情況而完成，其目的在於，提供一種晶圓及晶圓的加工方法，其能夠抑制半導體晶片中的碎片的產生。 (1)本發明的一個方式的晶圓是在沿切斷預定線形成了改質區域後藉由實施擴展工序而得到多個半導體晶片的晶圓，該晶圓具有由作為切斷預定線的晶片劃分線劃分的多個晶片化區域，晶片化區域具有：晶片部，其構成半導體晶片；以及切割部，其是從晶片部被切割的部分，並且是經由作為切斷預定線的開口線而與晶片部連續的切割部，開口線被設定為在半導體晶片形成切口形狀的開口部，開口線被設定為使得開口部的寬度朝向開口端側變寬或保持恆定。 在本發明的一個方式的晶圓中，在晶片化區域中，晶片部和切割部經由開口線連續地形成，開口線是作為與半導體晶片的開口部的形成相關的切斷預定線。於是，在本晶圓中，以開口部的寬度朝向開口端側變寬或保持恆定的方式設定上述開口線。藉由這樣設定開口線，在沿該開口線形成改質區域並實施擴展工序時，可以抑制晶片部(半導體晶片)與從晶片部(半導體晶片)被切割的切割部之間的接觸。由此，能夠有效地抑制在半導體晶片產生碎片(破片)。 (2)在上述(1)所記載的晶圓中，也可以是晶片部比切割部更靠近晶圓的中心側的晶片化區域的開口線，係以開口部的寬度朝向晶圓的外緣變寬或保持恆定的方式設定，晶片部比切割部更靠近晶圓的外緣側的晶片化區域的開口線，係以開口部的寬度朝向晶圓的中心變寬或保持恆定的方式設定。 根據這樣的構成，在晶片部比切割部更靠近晶圓的中心側的情況和比切割部更靠近晶圓的外緣側的情況的任一情況下，都能夠適當地抑制晶片部切割部之間的接觸與從晶片部切割的切割部之間的接觸。此外，在擴展工序中，由於遠離晶圓的中心的部分(即，晶圓的外緣側)的位移變得更大，所以在晶片部比切割部更靠近晶圓的中心側的構成中能夠使切割部沿想要分離的方向(作為遠離晶片部的方向的晶圓的外緣方向)有效地位移，能夠使切割部的分割性提高，並且能夠更有效地抑制半導體晶片中的碎片的產生。 (3)在上述(1)或(2)所記載的晶圓中，也可以是接近晶圓的外緣的晶片化區域的開口線，係延伸至晶圓的外緣。這樣，藉由開口線延伸至晶圓的外緣，能夠使切割部的分割性提高，並且能夠更有效地抑制半導體晶片中的碎片的產生。 (4)在上述(1)~(3)所記載的晶圓中，也可以是晶片劃分線延伸至晶圓的外緣。這樣，藉由晶片劃分線延伸至晶圓的外緣，能夠使晶片部的分割性提高。 (5)在上述(1)~(4)所記載的晶圓中，也可以是多個晶片化區域係從晶圓的中心放射狀地配置，晶片部和切割部依次連續地設置在從晶圓的中心放射狀地擴展的線上。作為擴展裝置，在使用放射狀地擴張晶圓的裝置的情況下，多個晶片化區域從晶圓的中心放射狀地配置，並且晶片部和切割部依次連續地設置在從晶圓的中心放射狀地擴展的線上，從而沿擴張方向配置有多個晶片化區域的晶片部和切割部。藉由由上述擴展裝置擴張這樣的晶圓，能夠使分割性提高，並且有效地抑制在半導體晶片產生碎片。 (6)在上述(1)~(5)所記載的晶圓中，也可以是開口線被設定為使得開口部的開口角的中心線位於從晶圓的中心放射狀地擴展的線上。作為擴展裝置，在使用放射狀地擴張晶圓的裝置的情況下，開口部的開口角的中心線位於從晶圓的中心放射狀地擴展的線上，從而能夠適當地抑制晶片部切割部之間的接觸與切割部之間的接觸並且使晶片部和切割部分離。即，能夠有效地抑制在半導體晶片產生碎片(破片)。 (7)本發明的一個方式的晶圓是在沿切斷預定線形成了改質區域後藉由實施擴展工序而得到多個半導體晶片的晶圓，該晶圓具有由作為切斷預定線的晶片劃分線劃分的多個晶片化區域，晶片化區域具有：晶片部，其構成半導體晶片；以及切割部，其是從晶片部被切割的部分，並且是經由作為切斷預定線的開口線而與晶片部連續的切割部，開口線被設定為在半導體晶片形成切口形狀的開口部，開口線被設定為在擴展工序中避免晶片部與切割部之間的接觸。 在本發明的一個方式的晶圓中，在晶片化區域中，晶片部和切割部係經由作為切斷預定線開口線連續地形成，開口線是與半導體晶片的開口部的形成相關的切斷預定線。於是，在本晶圓中，以在擴展工序中避免晶片部切割部之間的接觸與切割部之間的接觸的方式設定上述開口線。藉由這樣設定開口線，在沿該開口線形成改質區域並實施擴展工序時，抑制晶片部(半導體晶片)與從晶片部(半導體晶片)被切割的切割部之間的接觸。由此，能夠有效地抑制在半導體晶片產生碎片(破片)。 (8)本發明的一個方式的晶圓的加工方法，包括：準備晶圓的工序，晶圓具有由作為切斷預定線的晶片劃分線劃分的多個晶片化區域，晶片化區域具有：晶片部，其構成半導體晶片；以及切割部，其是從晶片部被切割的部分，並且是經由作為切斷預定線的開口線而與晶片部連續的切割部，開口線被設定為在半導體晶片形成切口形狀的開口部；沿切斷預定線照射雷射光而形成改質區域的工序；以及藉由擴張貼附於形成了改質區域的晶圓的帶，將晶片部和切割部隔開間隔而分離，得到半導體晶片的工序。 在本發明的一個方式的晶圓的加工方法中，準備的晶圓，係在晶片化區域中具有晶片部和切割部，晶片部和切割部係經由開口線連續地形成，該開口線是與半導體晶片的開口部的形成相關的切斷預定線。然後，對該晶圓沿切斷預定線形成改質區域，藉由擴張貼附於該晶圓的帶，得到半導體晶片。在此，在本加工方法中，在得到半導體晶片的工序中，晶片部和切割部是隔開間隔而分離。由此，能夠抑制晶片部(半導體晶片)和從晶片部(半導體晶片)被切割的切割部之間的接觸，並且能夠有效地抑制在半導體晶片產生碎片(破片)。 (9)在上述(8)所記載的加工方法中，也可以是多個晶片化區域從晶圓的中心放射狀地配置，晶片部和切割部依次連續地設置在從晶圓的中心放射狀地擴展的線上，在擴展工序中，沿從晶圓的中心放射狀地延伸的方向擴張貼附於晶圓的帶。由此，能夠對準晶片部和切割部連續地依次設置的方向與擴張方向，能夠使分割性提高，並且能夠有效地抑制在半導體晶片產生碎片。 (10)在上述(8)或(9)所記載的加工方法中，也可以是接近晶圓的外緣的晶片化區域的開口線係延伸至晶圓的外緣。這樣，藉由開口線延伸至晶圓的外緣，能夠使切割部的分割性提高，並且能夠更有效地抑制半導體晶片中的碎片的產生。 (11)在上述(10)所記載的加工方法中，也可以是在形成改質區域的工序中，對於延伸至晶圓的外緣的開口線，從該開口線的內側朝向外側照射雷射光而形成改質區域。根據這樣的構成，能夠使因改質區域的形成而產生的裂紋停止在開口線的內側而擴展到外側。由此，能夠在應該停止龜裂的部分(成為半導體晶片的開口線的內側)適當地停止龜裂。 (12)在上述(8)~(11)所記載的加工方法中，也可以是在形成改質區域的工序中，相對於開口線的行進方向，沿與結晶方向側相反的方向照射橢圓形的雷射光束。關於雷射光束，有時會向結晶方向側彎曲(被拉向結晶方向側)，藉由向相對於加工進行方向與結晶方向側相反的方向照射橢圓形的雷射光束，考慮到上述的向結晶方向側彎曲，能夠在期望的加工進行方向上照射雷射光束。即，根據這樣的構成，能夠實現沿切斷預定線的改質區域的形成。 (13)在上述(8)~(12)所記載的加工方法中，也可以是在形成改質區域的工序中，沿開口線形成改質區域時的雷射光的掃描數設定為比沿晶片劃分線形成改質區域時的雷射光的掃描數更多。根據這樣的構成，用於切割切割部的雷射光的掃描數比用於從晶圓切割晶片部的雷射光的掃描數更多，在晶圓擴張時，能夠使切割部儘早地分離。藉由儘早地分離切割部，能夠儘早地確定晶圓中的重心，能夠避免由於重心的反復移動而使切割部與晶片部容易相互接觸而導致在半導體晶片產生碎片的情況。 (14)在上述(8)~(13)所記載的加工方法中，也可以是晶片劃分線延伸至晶圓的外緣。這樣，藉由晶片劃分線延伸至晶圓的外緣，能夠使晶片部的分割性提高。 (15)本發明的一個方式的晶圓的加工方法包括：準備上述(1)~(7)所記載的晶圓的工序；沿切斷預定線形成改質區域的工序；以及藉由擴張貼附於形成了改質區域的晶圓的帶，得到多個半導體晶片的工序。根據這樣的晶圓的加工方法，能夠抑制晶片部(半導體晶片)與從晶片部(半導體晶片)被切割的切割部之間的接觸，並且能夠有效地抑制在半導體晶片產生碎片(破片)。 根据本發明的一個方式，能够抑制半導體晶片中的碎片的產生。 A semiconductor wafer may have a notch-shaped opening. Such openings are formed, for example, in optical-related products for positioning (alignment) when a semiconductor wafer is installed, or as a hole for passing light from a light-emitting element. For example, during wafer division, the semiconductor wafer and the portion where the opening is formed are separated to obtain a semiconductor wafer in which the opening is formed. Here, for example, in a method of obtaining a plurality of semiconductor wafers by expanding a wafer in which a modified region is formed, a portion separated from the semiconductor wafer (a portion forming an opening) may come into contact with the semiconductor due to the expansion of the wafer. wafer, and chipping (fragmentation) occurs in a semiconductor wafer. One aspect of the present invention has been accomplished in view of the above-mentioned actual situation, and an object thereof is to provide a wafer and a wafer processing method that can suppress the generation of debris in a semiconductor wafer. (1) A wafer according to one aspect of the present invention is a wafer in which a plurality of semiconductor wafers are obtained by performing an expansion process after forming a modified region along a planned cutting line, and the wafer has a plurality of semiconductor wafers formed as a planned cutting line. A plurality of wafering areas divided by wafer dividing lines, the wafering area having: a wafer portion that constitutes a semiconductor wafer; and a cutting portion that is a portion cut from the wafer portion via an opening line that is a planned cutting line In the dicing portion that is continuous with the wafer portion, the opening line is set so that the width of the opening becomes wider toward the opening end side or remains constant. In the wafer according to one aspect of the present invention, in the wafering region, the wafer portion and the dicing portion are formed continuously via an opening line serving as a planned cutting line related to the formation of the opening portion of the semiconductor wafer. Therefore, in this wafer, the opening line is set so that the width of the opening increases toward the opening end side or remains constant. By setting the opening line in this way, when the modified region is formed along the opening line and the expansion process is performed, contact between the wafer portion (semiconductor wafer) and the dicing portion cut from the wafer portion (semiconductor wafer) can be suppressed. This can effectively suppress the generation of chips (fragments) on the semiconductor wafer. (2) In the wafer described in (1) above, the opening line of the wafering area in the wafer center side of the wafer may be closer to the wafer than the dicing part, and the width of the opening may be directed toward the outer edge of the wafer. The opening line of the wafering area in the wafer area closer to the outer edge of the wafer than the dicing part is set so that the width of the opening widens or remains constant toward the center of the wafer. According to such a configuration, in either case where the wafer portion is closer to the center side of the wafer than the dicing portion or when it is closer to the outer edge side of the wafer than the dicing portion, the relationship between the wafer portion and the dicing portion can be appropriately suppressed. The contact between the cutting part and the cutting part from the wafer part. In addition, in the expansion process, since the displacement of the portion away from the center of the wafer (that is, the outer edge side of the wafer) becomes larger, it is possible to configure the wafer portion closer to the center side of the wafer than the cutting portion. By effectively displacing the dicing portion in the direction to be separated (the direction of the outer edge of the wafer as a direction away from the wafer portion), the divisionability of the dicing portion can be improved, and the generation of chips in the semiconductor wafer can be more effectively suppressed. . (3) In the wafer described in (1) or (2) above, the opening line of the wafering area close to the outer edge of the wafer may be extended to the outer edge of the wafer. In this way, by extending the opening line to the outer edge of the wafer, the divisionability of the cutting portion can be improved, and the generation of debris in the semiconductor wafer can be more effectively suppressed. (4) In the wafer described in (1) to (3) above, the wafer dividing line may extend to the outer edge of the wafer. In this way, by extending the wafer dividing line to the outer edge of the wafer, the divisionability of the wafer portion can be improved. (5) In the wafer described in (1) to (4) above, a plurality of wafering regions may be arranged radially from the center of the wafer, and the wafer part and the cutting part may be provided sequentially and continuously on the slave wafer. A line that expands radially from the center of a circle. As the expansion device, when a device that expands the wafer radially is used, a plurality of wafering regions are arranged radially from the center of the wafer, and the wafer section and the cutting section are sequentially and continuously provided radiating from the center of the wafer. The wafer portion and the cutting portion of the plurality of wafering regions are arranged along the expanding direction. By expanding such a wafer with the above-mentioned expansion device, the divisibility can be improved and the generation of chips in the semiconductor wafer can be effectively suppressed. (6) In the wafer described in (1) to (5) above, the opening line may be set so that the center line of the opening angle of the opening is located on a line extending radially from the center of the wafer. When a device that expands the wafer radially is used as the expansion device, the center line of the opening angle of the opening is located on a line that expands radially from the center of the wafer, so that the gap between the cutting portion of the wafer portion can be appropriately suppressed. The contact between the wafer part and the cutting part separates the wafer part and the cutting part. That is, the generation of chips (fragments) on the semiconductor wafer can be effectively suppressed. (7) A wafer according to one aspect of the present invention is a wafer in which a plurality of semiconductor wafers are obtained by performing an expansion process after forming a modified region along a planned cutting line, and the wafer has a plurality of semiconductor wafers formed as a planned cutting line. A plurality of wafering areas divided by wafer dividing lines, the wafering area having: a wafer portion that constitutes a semiconductor wafer; and a cutting portion that is a portion cut from the wafer portion via an opening line that is a planned cutting line The opening line of the dicing portion that is continuous with the wafer portion is set to form an opening in the shape of a notch in the semiconductor wafer, and the opening line is set to avoid contact between the wafer portion and the dicing portion during the expansion process. In the wafer according to one aspect of the present invention, in the wafering region, the wafer portion and the dicing portion are continuously formed through an opening line as a planned cutting line, which is a cutting line related to the formation of the opening portion of the semiconductor wafer. Reservation line. Therefore, in the present wafer, the opening line is set so as to avoid contact between the cut portions of the wafer portion and contact between the cut portions during the expansion process. By setting the opening line in this way, when the modified region is formed along the opening line and the expansion process is performed, contact between the wafer portion (semiconductor wafer) and the dicing portion cut from the wafer portion (semiconductor wafer) is suppressed. This can effectively suppress the generation of chips (fragments) on the semiconductor wafer. (8) A wafer processing method according to one aspect of the present invention, including the step of preparing a wafer, the wafer having a plurality of wafering areas divided by wafer dividing lines as planned cutting lines, the wafering area having: a wafer a portion that constitutes a semiconductor wafer; and a dicing portion that is a portion cut from the wafer portion and is a dicing portion that is continuous with the wafer portion via an opening line as a planned cutting line, the opening line being set to be formed on the semiconductor wafer a notch-shaped opening; a process of irradiating laser light along a planned cutting line to form a modified region; and spacing the wafer portion and the diced portion by expanding a tape attached to the wafer in which the modified region is formed. The process of separating and obtaining semiconductor wafers. In the wafer processing method according to one aspect of the present invention, the prepared wafer has a wafer part and a dicing part in the wafering region, and the wafer part and the dicing part are formed continuously through an opening line, and the opening line is connected to the wafer part. A planned cutting line related to the formation of the opening portion of the semiconductor wafer. Then, a modified region is formed on the wafer along a planned cutting line, and a tape attached to the wafer is expanded to obtain a semiconductor wafer. Here, in this processing method, in the step of obtaining a semiconductor wafer, the wafer part and the dicing part are separated with a gap. This can suppress contact between the wafer portion (semiconductor wafer) and the cutting portion cut from the wafer portion (semiconductor wafer), and can effectively suppress the generation of chips (fragments) in the semiconductor wafer. (9) In the processing method described in (8) above, the plurality of wafering regions may be arranged radially from the center of the wafer, and the wafer part and the cutting part may be successively provided radially from the center of the wafer. On the ground expansion line, in the expansion process, the tape attached to the wafer is expanded in a direction extending radially from the center of the wafer. Accordingly, the direction in which the wafer portion and the cutting portion are continuously provided in sequence can be aligned with the expansion direction, thereby improving the separability and effectively suppressing the generation of chips in the semiconductor wafer. (10) In the processing method described in (8) or (9) above, the opening line of the wafering region close to the outer edge of the wafer may be extended to the outer edge of the wafer. In this way, by extending the opening line to the outer edge of the wafer, the divisionability of the cutting portion can be improved, and the generation of debris in the semiconductor wafer can be more effectively suppressed. (11) In the processing method described in (10) above, in the step of forming the modified region, the opening line extending to the outer edge of the wafer may be irradiated with laser light from the inside toward the outside of the opening line. A modified area is formed. According to such a structure, cracks generated by the formation of the modified region can be stopped inside the opening line and spread outside. This makes it possible to appropriately stop cracking at the portion where cracking should be stopped (inside the opening line of the semiconductor wafer). (12) In the processing method described in the above (8) to (11), in the step of forming the modified region, the elliptical irradiation may be performed in the direction opposite to the crystal direction side with respect to the traveling direction of the opening line. laser beam. The laser beam may be bent toward the crystallographic direction (pulled toward the crystallographic direction). By irradiating an elliptical laser beam in the direction opposite to the crystallographic direction with respect to the processing direction, the above-mentioned direction can be considered. The crystal direction side is curved and the laser beam can be irradiated in the desired processing direction. That is, according to such a configuration, it is possible to form a modified region along the planned cutting line. (13) In the processing methods described in (8) to (12) above, in the step of forming the modified region, the scanning number of the laser light when forming the modified region along the opening line may be set to be greater than that along the wafer. When dividing lines form modified areas, the number of scans of laser light is larger. According to this configuration, the number of scans of the laser light used to cut the dicing portion is greater than the number of scans of the laser light used to cut the wafer portion from the wafer, and the dicing portion can be separated as early as possible when the wafer is expanded. By separating the cutting portion as early as possible, the center of gravity in the wafer can be determined as early as possible, and it is possible to avoid the situation where the cutting portion and the wafer portion are easily in contact with each other due to repeated movement of the center of gravity, resulting in fragments in the semiconductor wafer. (14) In the processing methods described in (8) to (13) above, the wafer dividing line may extend to the outer edge of the wafer. In this way, by extending the wafer dividing line to the outer edge of the wafer, the divisionability of the wafer portion can be improved. (15) A wafer processing method according to one aspect of the present invention includes: the steps of preparing the wafers described in (1) to (7) above; the step of forming a modified region along a planned cutting line; and by expanding the paste. A process in which a plurality of semiconductor wafers are obtained by attaching a tape to a wafer with a modified region formed thereon. According to such a wafer processing method, contact between the wafer portion (semiconductor wafer) and the dicing portion cut from the wafer portion (semiconductor wafer) can be suppressed, and the generation of chips (fragments) in the semiconductor wafer can be effectively suppressed. According to one aspect of the present invention, it is possible to suppress the occurrence of debris in a semiconductor wafer.

以下，參照附圖，對本發明的一個方式的實施方式進行詳細的說明。在各圖中，對相同或相當的部分使用相同的符號，省略重復的說明。 在本實施方式中，在晶圓(對象物)的內部形成改質區域。作為在晶圓的內部形成改質區域的裝置，能夠使用例如圖1所示的雷射加工裝置100。如圖1所示，雷射加工裝置100具備支撐部102、光源103、光軸調整部104、空間光調變器105、聚光部106、光軸監測部107、可見光攝像部108A、紅外攝像部108B、移動機構109、以及管理單元150。雷射加工裝置100是藉由對晶圓20照射雷射光L0而在晶圓20形成改質區域11的裝置。在以下的說明中，將彼此正交的3個方向分別稱為X方向、Y方向和Z方向。作為一個例子，X方向是第1水平方向，Y方向是垂直於第1水平方向的第2水平方向，Z方向是垂直方向。 支撐部102例如藉由吸附晶圓20來支撐晶圓20。支撐部102可以沿X方向和Y方向的各個方向移動。支撐部102可以以沿Z方向的旋轉軸為中心旋轉。光源103藉由例如脈衝振盪方式出射雷射光L0。雷射光L0對晶圓20具有透過性。光軸調整部104調整從光源103出射的雷射光L0的光軸。光軸調整部104例如由可以調整位置和角度的多個反射鏡構成。 空間光調變器105配置於雷射加工頭H內。空間光調變器105對從光源103出射的雷射光L0進行調變。空間光調變器105是反射型液晶(LCOS：Liquid Crystal on Silicon)的空間光調變器(SLM：Spatial Light Modulator)。在空間光調變器105中，藉由適當設定顯示於其顯示部(液晶層)的調變圖案，可以對雷射光L0進行調變。在本實施方式中，從光軸調整部104沿Z方向向下側行進的雷射光L0入射到雷射加工頭H內，被鏡MM1反射，入射到空間光調變器105。空間光調變器105反射這樣入射的雷射光L0並且進行調變。 聚光部106安裝在雷射加工頭H的底壁。聚光部106將由空間光調變器105調變的雷射光L0聚光到由支撐部102支撐的晶圓20。在本實施方式中，由空間光調變器105反射的雷射光L0被分色鏡MM2反射，入射到聚光部106。聚光部106將入射的雷射光L0聚光到晶圓20。聚光部106藉由將聚光透鏡單元161經由驅動機構162安裝於雷射加工頭H的底壁而構成。驅動機構162藉由例如壓電元件的驅動力使聚光透鏡單元161沿Z方向移動。 此外，在雷射加工頭H內，在空間光調變器105和聚光部106之間配置有成像光學系統(省略圖示)。成像光學系統構成空間光調變器105的反射面與聚光部106的入射光瞳面處於成像關係的雙側遠心光學系統。由此，空間光調變器105的反射面上的雷射光L0的像(由空間光調變器105調變後的雷射光L0的像)轉像(成像)到聚光部106的入射光瞳面。在雷射加工頭H的底壁，在X方向上以位於聚光透鏡單元161的兩側的方式安裝有一對測距感測器S1、S2。各測距感測器S1、S2對晶圓20的雷射光入射面出射測距用的光(例如雷射)，藉由檢測在雷射光入射面反射的測距用的光，取得雷射光入射面的位移資料。 光軸監測部107配置於雷射加工頭H內。光軸監測部107檢測透過分色鏡MM2的雷射光L0的一部分。光軸監測部107的檢測結果例如表示入射到聚光透鏡單元161的雷射光L0的光軸與聚光透鏡單元161的光軸之間的關係。可見光攝像部108A出射可見光V0，取得基於可見光V0的晶圓20的像作為圖像。可見光攝像部108A配置於雷射加工頭H內。紅外攝像部108B出射紅外光，取得基於紅外光的晶圓20的像作為紅外線圖像。紅外攝像部108B安裝於雷射加工頭H的側壁。 移動機構109包括使雷射加工頭H和支撐部102中的至少任一個沿X方向、Y方向和Z方向移動的機構。移動機構109藉由馬達等公知的驅動裝置的驅動力驅動雷射加工頭H和支撐部102中的至少任一個，以使雷射光L0的聚光點C沿X方向、Y方向和Z方向移動。移動機構109包括使支撐部102旋轉的機構。移動機構109藉由馬達等公知的驅動裝置的驅動力旋轉驅動支撐部102。 管理單元250具有控制部251、使用者介面252和記憶部253。控制部251控制雷射加工裝置100的各部的動作。控制部251構成為包括處理器、記憶體、儲存器和通信設備等的電腦裝置。在控制部251中，處理器執行讀入到記憶體等的軟體(程式)，控制記憶體和儲存器中的資料的讀出和寫入、以及通信設備的通信。使用者介面252進行各種資料的顯示和輸入。使用者介面252構成具有圖形庫(graphic base)的操作體系的GUI(Graphical User Interface)。 使用者介面252包括例如觸摸面板、鍵盤、滑鼠、麥克風、平板型終端、監測器等中的至少任一個。使用者介面252可以例如藉由觸摸輸入、鍵盤輸入、滑鼠操作、聲音輸入等接受各種輸入。使用者介面252可以在其顯示畫面上顯示各種資訊。使用者介面252相當於可以接受輸入的輸入接受部、以及基於接受的輸入顯示設定畫面的顯示部。記憶部253例如是硬碟等，記憶各種資料。 在如上構成的雷射加工裝置100中，當雷射光L0聚光於晶圓20的內部時，在對應於雷射光L0的聚光點(至少聚光區域的一部分)C的部分中吸收雷射L，在晶圓20的內部形成改質區域11。改質區域11是密度、折射率、機械強度、其他物理特性與周圍的非改質區域不同的區域。作為改質區域11，例如有熔融處理區域、裂紋區域、絕緣破壞區域、折射率變化區域等。改質區域11包括多個改質點11s和從多個改質點11s伸展的龜裂。 作為一個例子，說明沿用於切斷晶圓20的線15(切斷預定線)在晶圓20的內部形成改質區域11的情況下的雷射加工裝置100的動作。 首先，雷射加工裝置100使支撐部102旋轉，以使設定於晶圓20的線15平行於X方向。雷射加工裝置100基於由紅外攝像部108B取得的圖像(例如，晶圓20具有的功能元件層的像)，使支撐部102沿X方向和Y方向中的各個方向移動，以使在從Z方向觀察的情況下雷射光L0的聚光點C位於線15上。雷射加工裝置100基於由可見光攝像部108A取得的圖像(例如，晶圓20的雷射光入射面的像)，使雷射加工頭H(即，聚光部106)沿Z方向移動(高度設定)，以使雷射光L0的聚光點C位於雷射光入射面上。雷射加工裝置100以該位置為基準，使雷射加工頭H沿Z方向移動，以使雷射光L0的聚光點C位於距雷射光入射面起規定深度。 接著，雷射加工裝置100使雷射光L0從光源103出射，並且使支撐部102沿X方向移動，以使雷射光L0的聚光點C沿著線15相對地移動。此時，雷射加工裝置100基於藉由一對測距感測器S1、S2中的位於雷射光L0的加工進行方向上的前側的一方取得的雷射光入射面的位移資料，使聚光部106的驅動機構162動作，以使雷射光L0的聚光點C位於從雷射光入射面起規定深度。 由此，沿著線15並且在從晶圓20的雷射光入射面起一定深度處形成1列改質區域11。當藉由脈衝振盪方式從光源103出射雷射光L0時，多個改質點11s以沿X方向排列成一列的方式形成。1個改質點11s藉由一個脈衝的雷射光L0的照射形成。1列改質區域11是排列成1列的多個改質點11s的集合。相鄰的改質點11s根據雷射光L0的脈衝間距(聚光點C相對於晶圓20的相對移動速度除以雷射光L0的重複頻率而得的值)有彼此連接的情況，也有彼此分離的情況。 如圖2和圖3所示，晶圓20具有半導體基板(基板)21和功能元件層22。此外，在圖2和圖3中，簡化表示晶圓20的構成。晶圓20的詳細構成在後文描述。晶圓20的厚度例如為775μm。半導體基板21具有表面21a和背面21b。半導體基板21例如為矽基板。在半導體基板21設置有表示結晶方向的槽口(notch)21c。在半導體基板21，也可以設置定向平面作為槽口21c的替代。功能元件層22形成於半導體基板21的表面21a。功能元件層22包括多個功能元件22a。多個功能元件22a沿半導體基板21的表面21a二維地配置。各功能元件22a例如是光電二極體等受光元件、雷射二極體等發光元件、記憶體等電路元件等。各功能元件22a也有堆疊多個層而三維地構成的情況。 在晶圓20形成有多個街道(street)23。多個街道23是在相鄰的功能元件22a之間露出到外部的區域。即，多個功能元件22a以經由街道23彼此相鄰的方式配置。作為一個例子，多個街道23也可以相對於矩陣狀地排列的多個功能元件22a，以通過相鄰的功能元件22a之間的方式格子狀地延伸。 如圖2和圖3所示，在晶圓20設定有多條線15。晶圓20預定沿多條線15的每條線按每個功能元件22a切斷(即，按每個功能元件22a進行晶片化)。在從晶圓20的厚度方向觀察的情況下，各線15通過各街道23。作為一個例子，在從晶圓20的厚度方向觀察的情況下，各線15以通過各街道23的中心的方式延伸。各線15是由雷射加工裝置100設定於晶圓20的假想線。各線15也可以是在晶圓20實際上畫出的線。 此外，作為切斷預定線的線15不限於如本實施方式那樣如作為圖案構成街道23的情況(即，藉由圖案遮罩在街道23事先除去不需要的膜的情況或在街道23上配置TEG的情況)可以視覺辨認的線。例如，也可以不作為圖案構成街道23(街道23為與設計上的主動區域相同的構成)，而是從設計上的基準位置推定線15。此外，在晶圓為裸晶圓的情況下，也可以將槽口或定向平面作為基準而推定設計上的線15。 接著，參照圖4說明使用雷射加工裝置100的雷射加工方法。圖4是表示晶圓20的加工方法的流程圖。晶圓20是在沿線15形成了改質區域11後藉由實施擴展工序而得到多個半導體晶片的晶圓。 如圖4所示，首先，準備晶圓20(步驟S11)。準備的晶圓20的細節在後文敘述。然後，在晶圓20的半導體基板21的背面21b貼附切片(dicing)用帶。此外，在晶圓20貼附切片用帶之前，也可以實施磨削晶圓20的磨削工序、除去街道23的表層的切槽(grooving)工序。 接著，在雷射加工裝置100中，藉由沿線15向晶圓20照射雷射光L0，沿線15在晶圓20的內部形成改質區域11(步驟S12)。在此，在半導體基板21的背面21b貼附有切片用帶的狀態下，由支撐部102吸附晶圓20來進行支撐後，經由切片用帶將雷射光L0的聚光點對準半導體基板21的內部，將背面21b作為雷射光入射面，向晶圓20照射雷射光L0。 接著，在擴展裝置(未圖示)中，貼附的切片用帶被擴張(實施擴展)(步驟S13)。由此，龜裂從沿著各線15形成於半導體基板21的內部的改質區域11沿著晶圓20的厚度方向伸展，晶圓20被沿著線15切斷。由此，晶圓20按每個功能元件22a進行晶片化，得到多個半導體晶片。詳細地，藉由擴張貼附於形成了改質區域11的晶圓20的切片用帶，隔開間隔而分離晶片部120x和切割部122(例如，參照圖10(b)，詳細情況在後文描述)，得到半導體晶片。 接著，對藉由上述雷射加工方法得到的半導體晶片進行詳細說明。在本實施方式中，在從晶圓20得到的多個半導體晶片形成有切口形狀的開口部。這樣的開口部根據半導體晶片的用途而形成。圖5和圖6是說明形成有開口部121的半導體晶片120的使用例的圖。在圖5所示的例子中，作為光半導體感測器發揮功能的半導體晶片120具有作為設置於光關聯產品400時的定位(對準)部分的開口部121。即，半導體晶片120具有作為嵌合於光關聯產品400的突出部401的部分的開口部121。此外，在圖6所示的例子中，半導體晶片120具有作為將從發光元件500輸出的光朝向資料600穿過的孔的開口部121。 在此，在得到形成有開口部121的半導體晶片120的情況下，需要從成為半導體晶片120(構成半導體晶片120)的部分、即晶片部分離形成開口部121的部分。在該情況下，考慮到如果藉由在擴展工序中擴張晶圓20而從上述晶片部分離形成開口部121的部分，則在分離後，由於形成開口部121的部分與晶片部之間接觸，會在半導體晶片120產生碎片(破片)。 圖7是說明碎片的產生的圖。圖7(a)示出在晶圓20形成4個晶片化區域200的例子。晶片化區域200具有：晶片部120x，其在擴展工序後構成半導體晶片120；以及切割部122，其是從晶片部120x切割的部分，並且是形成半導體晶片120的開口部121的部分。即，藉由從晶片部120x分離切割部122，得到形成有開口部121的半導體晶片120。晶片化區域200為大致矩形。在晶片化區域200的長邊方向上，切割部122以相對於中央成為對稱(成為左右對象)的方式形成。 如圖7(a)所示，4個晶片化區域200配置在由穿過晶圓20的中心的對角線劃分的4個區域(圖7(a)中的左上區域、右上區域、左下區域、右下區域)。現在，在擴展裝置(未圖示)中，貼附於晶圓20的切片用帶從晶圓20的中心放射狀地擴張。 在該情況下，如圖7(b)所示，對於圖7(a)中的左上方的晶片化區域200，認為從晶片部120x分離的切割部122與晶片部120x的左上方部位接觸。此外，如圖7(c)所示，對於圖7(a)中的右上方的晶片化區域200，認為從晶片部120x分離的切割部122與晶片部120x的右上方部位接觸。此外，如圖7(d)所示，對於圖7(a)中的左下方的晶片化區域200，認為從晶片部120x分離的切割部122與晶片部120x的右上方部位接觸。此外，如圖7(e)所示，對於圖7(a)中的右下方的晶片化區域200，認為從晶片部120x分離的切割部122與晶片部120x的左上方部位接觸。這些接觸例如是由於越是靠近晶圓20的外緣的部分越是大幅位移而產生的(詳細情況在後文描述)。這樣，在各晶片化區域200中，由於切割部122與晶片部120x的接觸，有可能在擴展工序後的半導體晶片120產生碎片(破片)。 參照圖8和圖9對碎片的產生原理進行詳細說明。此外，在此說明的碎片的產生原理是一個例子，並不限於此。圖8是對擴展工序中的晶圓20的各部位的位移量進行說明的圖。在圖8(a)和圖8(b)中，表示貼附於晶圓20的切片用帶沿從晶圓20的中心放射狀地延伸的方向擴張時的晶圓20的狀況。在擴展工序中，晶圓20的中心與進行擴展的切片用帶的中心大致一致。現在，在晶圓20中設置彼此分離並且相鄰的晶片化區域201、202。晶片化區域201比晶片化區域202更靠近晶圓20的中心側。 在此，擴展工序中的位移量越遠離擴張的中心位置(在此為晶圓20的中心)越大。因此，晶片化區域202的位移量大於晶片化區域201的位移量。此外，藉由擴展工序，雖然切片用帶能夠伸縮，但是由於硬到可以看作剛體的程度的晶圓20的各晶片化區域201、202不伸縮(不變形)，因此與晶片化區域201、202接觸的貼附面的切片用帶也不伸縮。因此，在晶片化區域201內，無論距擴張的中心位置的距離，位移量都成為一定。同樣地，在晶片化區域202內，無論距擴張的中心位置的距離，位移量都成為一定。即，如圖8(a)中的晶片化區域201、202的箭頭的大小(粗細)所示，在1個晶片化區域內，形成施加均勻的應力的狀態。 其結果，晶片化區域的位移與晶片化區域的範圍內的切片用帶的位移的平均值近似相等。因此，晶片化區域的位移係由晶片化區域的重心位置至切片用帶的中心位置(帶中心位置)之間的距離表示的重心模型確定。即，晶片化區域的位移係與晶片化區域的重心位置至帶中心位置之間的距離近似地成比例關係。如圖8(b)所示，晶片化區域201的位移係由晶片化區域201的重心位置201c與帶中心位置TC之間的距離確定。此外，晶片化區域202的位移係由晶片化區域202的重心位置202c與帶中心位置TC之間的距離確定。現在，由於晶片化區域202的重心位置202c與帶中心位置TC之間的距離比晶片化區域201的重心位置201c與帶中心位置TC之間的距離大，因此與晶片化區域201相比，作為外緣側的晶片化區域的晶片化區域202朝向擴張方向(外緣側)位移更大。因此，晶片化區域202與晶片化區域201相比分割性更好(能夠完全地分割)。 根據上述的重心模型，對發生碎片的方式進行具體說明。圖9是說明碎片的產生的圖。圖9(a)示出了1個晶片化區域300。晶片化區域300具有：晶片部320x，其在擴展工序後構成半導體晶片；以及切割部322，其是從晶片部320x切割的部分，並且是形成半導體晶片的開口部的部分。晶片部320x以包圍切割部322的方式配置，具有在晶圓20的徑向上比切割部322更靠外緣側的部分325和更靠近中心側的部分326。再有，晶片部320x的重心位置320c位於比切割部322的重心位置322c更靠近帶中心位置TC的位置。在該情況下，根據上述重心模型，切割部322向擴張方向(外緣側)的位移量大於晶片部320x的位移量。再有，如上前述，由於晶片部320x具有比切割部322更靠近外緣側的部分325，因此在該外緣側的部分325中，與位移量大的切割部322接觸。在該情況下，在晶片部320x的外緣側的部分325中，有可能發生碎片。此外，存在不能適當地進行切割部322的分割的情況。 與此相對，例如如圖9(b)所示，在1個晶片化區域200中，在位移量大的切割部422的位移方向(即，外緣側)不存在晶片部420x的晶圓20中，在擴展工序中切割部422不與晶片部420x接觸。在該情況下，在晶片部420x中不發生碎片，此外，也可以適當地進行切割部422的分割。這樣，藉由晶片化區域中的晶片部和切割部的配置，能夠抑制擴展工序中的碎片的產生。以下，參照圖10～圖13說明抑制碎片的晶片化區域的配置例。 圖10是示出抑制碎片的晶片化區域200的配置例的圖。圖10(a)所示的晶圓20的晶片化區域200的配置與上述圖7(a)的配置相同。即，在圖10(a)所示的晶圓20中，在由通過晶片20的中心的對角線所劃分的4個區域的各區域中分別設置1個大致矩形的晶片化區域200。各晶片化區域200的長邊與一對角線平行地延伸，短邊與另一對角線平行地延伸。再有，在各晶片化區域200，以相對於長邊方向上的中央部分成為對稱(成為左右對象)的方式設置切割部122。切割部122設置於晶片化區域200的短邊方向上的一端側(圖10(a)中的上部側)。 對於這樣的晶圓20，如圖10(a)所示，在其中心與切片用帶的中心位置TC一致的狀態下，在擴展工序中，沿從中心放射狀地延伸的方向擴張。現在，如圖10(a)的局部放大圖所示，晶片部120x的重心位置120c位於比切割部122的重心位置122c更靠近帶中心位置TC的位置。在該情況下，根據上述重心模型，切割部122向擴張方向(外緣側)的位移量大於晶片部120x的位移量。再有，由於在切割部122的位移方向(即，外緣側)存在晶片部120x的右上部位，因此切割部122與晶片部120x的右上部位接觸。這樣，在位移量大的切割部122的位移方向上，存在位移量小的晶片部120x的部分的情況下，切割部122與晶片部120x接觸。在該情況下，可能在晶片部120x中發生碎片。 圖10(b)和10(c)是示出抑制碎片產生的晶片化區域200的配置的圖。在圖10(b)和圖10(c)中，晶片化區域200單體的構成與上述圖10(a)相同，但是各晶片化區域200的配置與圖10(a)不同。在圖10(b)所示的例子中，在相對於通過晶圓20的中心的對角線成45度的4個方向上，分別設置晶片化區域200。從晶圓20的中心到4個晶片化區域200的距離彼此一致。晶片化區域200以短邊相對於通過晶圓20的中心並且相對於對角線成45度的放射狀的線垂直的方式配置。此外，晶片化區域200以切割部122配置於晶圓20的外緣側的方式設置。在該構成中，如圖10(b)的局部放大圖所示，晶片部120x的重心位置120c和切割部122的重心位置122c位於從帶的中心位置TC相對於對角線為45度的線上。再有，在位移量大的切割部122的位移方向上不存在晶片部120x。因此，在擴展工序中切割部122不與晶片部120x接觸，並且可以抑制在晶片部120x中發生碎片。 在圖10(c)所示的例子中，設置使圖10(b)所示的4個晶片化區域200旋轉45度的4個晶片化區域200。即，4個晶片化區域200分別配置於對角線上。在這樣的構成中，如圖10(c)的局部放大圖所示，晶片部120x的重心位置120c和切割部122的重心位置122c位於對角線上。再有，在位移量大的切割部122的位移方向上不存在晶片部120x。因此，在擴展工序中切割部122不與晶片部120x接觸，並且可以抑制在晶片部120x中發生碎片。 此外，在圖10(b)和圖10(c)的任一配置中都抑制了碎片的產生，但是例如，晶片的切割(cut)角度，圖10(b)的構成為45度(結晶方向＜100＞晶圓的情況下，(100))，與圖10(c)的構成為0度(結晶方向＜100＞晶圓的情況下，(110))不同(切斷方位變化)。在形成改質區域的隱形切片中，切斷方位(110)的切斷變得良好，因此優選為圖10(c)的配置。 圖11是示出抑制碎片的晶片化區域200的配置例的圖。如參照圖10所說明的那樣，對於具有左右對稱的切割部122的晶片化區域200，例如藉由在對角線上設置4個晶片化區域200，能夠有效地抑制碎片。在此，如圖11(a)的局部放大圖所示，對於設置有左右不對稱的切割部122的晶片化區域200，在設置於對角線上的情況下，也存在發生碎片和切割部122未分割的情況。 對於設置有這樣的左右不對稱的切割部122的晶片化區域200，以在擴展工序後成為開口部的部分的開口角的中心線位於從晶圓20的中心放射狀地擴展的線上的方式，設定角度(參照圖11(b))或位置(參照圖11(c))。由此，能夠抑制碎片的產生和切割部122的未分割。 對在擴展工序後成為開口部的部分的開口角的中心線進行詳細說明。如上所述，切割部122是形成半導體晶片120的開口部121的部分。所謂“成為開口部的部分的開口角的中心線”，可以換言之為，將在切割部122中連接於開口端的兩邊(俯視晶圓20時的兩邊)朝向晶圓20的中心延伸的交點與開口端的中點連結的線。在圖11(b)所示例子中，以成為開口部的部分的開口角的中心線位於從晶圓20的中心放射狀地擴展的線上的方式(即，以連接於晶圓20的中心，與擴展工序中的位移向量一致的方式)，從圖11(a)的狀態，傾斜(具體地，傾斜8度)地配置各晶片化區域200。此外，在圖11(c)所示例子中，以成為開口部的部分的開口角的中心線位於從晶圓20的中心放射狀地擴展的線上的方式(即，以連接於晶圓20的中心，與擴展工序中的位移向量一致的方式)，從圖11(a)的狀態，沿周向錯開配置各晶片化區域200。 圖12是說明晶片化區域的各種配置例的圖。在圖12(a)～12(i)所示的晶片化區域中，晶片部120x都存在於比切割部122更靠近晶圓的中心側。 在圖12(a)所示的例子中，晶片化區域具有左右對稱的切割部122。切割部122以開口部121的寬度朝向開口端側(晶圓的外緣側)變寬的方式設置。這樣，藉由以開口部121的寬度朝向開口端側變寬的方式設置切割部122，能夠適當地抑制碎片的產生，並且使切割部122的分割性提高。 在圖12(b)所示的例子中，晶片化區域具有左右不對稱的切割部122。雖然切割部122以開口部121的寬度朝向開口端側(晶圓的外緣側)變寬的方式設置，但是與圖12(a)的構成相比，開口寬度變窄。對於這樣的左右不對稱的切割部122，如上所述，藉由調整角度(參照圖11(b))或位置(參照圖11(c))，也能夠抑制碎片的產生。此外，由於開口寬度窄，因此雖然比圖12(a)的構成差，但是也能夠保證切割部122的分割性。 在圖12(c)所示的例子中，晶片化區域具有圓形的切割部122。在沿這樣的圓形狀的切割部122的線形成改質區域的情況下，例如，使用直線加工台進行多個切線加工，將該多個切線連接而成為大致圓形狀。藉由這樣的構成，也可以適當地抑制碎片的產生並且使切割部122的分割性提高。 在圖12(d)所示的例子中，晶片化區域具有朝向開口端側(晶圓的外緣側)變寬的三角形的切割部122。對於這樣的三角形的切割部122，也能夠實現碎片的產生抑制和切割部122的分割，但是由於晶圓的中心側(三角形的前端側)是尖的，因此擴展工序中的擴張方向與設想不同的情況下，存在成為碎片的風險。 在圖12(e)和圖12(f)所示的例子中，以開口部121的寬度朝向開口端側(晶圓的外緣側)成為恆定的方式設置切割部122。對於這樣的切割部122，僅藉由擴展工序不能分割切割部122，但是藉由在擴展工序前進行蝕刻，能夠適當地分割。在實施蝕刻工序的情況下，例如，藉由來自背面21b的雷射光入射，在晶圓20形成改質區域後，從背面21b對晶圓20的整個面進行蝕刻，進而在背面21b貼附帶，實施擴展工序。此外，蝕刻工序也可以為了選擇性蝕刻而安裝遮罩，實施僅切片街道的蝕刻或實施僅下述的開口線152(參照圖16)的蝕刻。此外，也可以為了表面保護而安裝遮罩，從表面21a實施蝕刻。 在圖12(g)所示的例子中，以開口部121的寬度朝向開口端側(晶圓的外緣側)變窄的方式設置切割部122。對於這樣的切割部122，不能藉由擴展工序分割切割部122。 在圖12(h)所示的例子中，對應於1個晶片部120x設置2個切割部122。這樣，也可以相對於1個晶片部120x設置多個切割部122。 在圖12(i)所示的例子中，晶片部120x的形狀不是矩形而是包含異形形狀。即使在使用這樣的晶片部120x的情況下，也能夠適當地抑制碎片的產生並且使切割部122的分割性提高。 圖13是示出抑制碎片的晶片化區域的配置例的圖。在圖13所示的例子中，在通過晶圓20的中心的對角線上設置4個晶片化區域200。在各晶片化區域200中，晶片部120x存在於比切割部122更靠近晶圓20的外緣側的位置。成為開口部的切割部122的寬度以朝向晶片20的中心變寬的方式形成。在圖13所示的例子中，晶片部120x存在於外緣側，在擴展工序中，晶片部120x的位移量比切割部122的位移量大。在該情況下，在擴展工序中，切割部122難以與晶片部120x接觸，可以抑制在晶片部120x中發生碎片。 接著，參照圖14和圖15對擴展工序的例子進行說明。圖14是說明擴展工序的一例的圖。在圖14所示的例子中，在晶圓20中，多個晶片化區域從晶圓20的中心放射狀地配置，晶片部120x和切割部122在從晶圓20的中心放射狀地擴展的線上連續地依次設置。相對於這樣的晶圓20，在擴展工序中，如圖14所示，利用圓形擴張型擴展器，貼附於晶圓20的切片用帶沿從晶圓20的中心放射狀地延伸的方向擴張。在該情況下，由於在配置於外緣側並且位移量大的切割部122的位移方向上不存在晶片部120x，因此能夠抑制晶片部120x的碎片的產生，並且能夠可靠地分割切割部122。 圖15是說明擴展工序的其他例子的圖。在圖15所示的例子中，在晶圓20中，在圖15中的上方向設置5個晶片化區域200，在下方向設置5個晶片化區域200。在上方向的晶片化區域200中，連續地依次在上部側設置切割部122，在下部側設置晶片部120x。此外，在下方向的晶片化區域200中，連續地依次在下部側設置切割部122，在上部側設置晶片部120x。相對於這樣的晶圓20，在擴展工序中，例如如圖15(a)所示，作為一個方向(CH1)，沿切割部122和晶片部120x連續的方向，實施切片用帶的擴張。之後，例如如圖15(b)所示，沿與CH1交叉的方向(CH2)實施切片用帶的擴張。這樣，也可以藉由對CH1和CH2方向依次擴張來實現擴展工序。 接著，參照圖16～圖18對用於切斷晶圓20的線15(切斷預定線)的設定例進行說明。圖16是示出線15的設定例的圖。圖16所示的晶圓20是與上述圖11(c)所示的左右非對稱的晶圓20相同的晶圓。 線15被構成為包括劃分各晶片化區域200的晶片劃分線151以及以在半導體晶片形成切口形狀的開口部的方式設定的開口線152。晶片部120x和切割部122經由開口線152連續地設置。開口線152被設定為在擴展工序中避免晶片部120x與切割部122之接觸。 如圖16所示，晶片劃分線151具有第1線151a、第2線151b、第3線151c和第4線151d。第1線151a和第2線151b是彼此平行地沿圖16中的縱向延伸的切斷預定線。第1線151a和第2線151b的一端部都延伸至晶圓20的外緣。第3線151c是與第1線151a的另一端部(晶圓20的中心側的端部)連續，並且沿圖16中的橫向延伸至與第2線151b交叉的部位的切斷預定線。第4線151d是與第3線151c平行地沿圖16中的橫向延伸的切斷預定線。第4線151d具有從第1線151a延伸至開口線152的第1線152a(下述)的部分和從第2線151b延伸至開口線152的第2線152b(下述)的部分。第4線151d沒有橫穿切割部122，僅延伸至與第1線152a交叉的部位和與第2線152b交叉的部位。 開口線152以開口部的寬度(即，切割部122的寬度)朝向開口端側變寬的方式設定。如圖16所示的晶圓20那樣，晶片部120x位於比切割部122更靠近晶圓20的中心側的晶片化區域200的開口線152，係以開口部的寬度朝向晶圓20的外緣變寬的方式設定。此外，如圖13所示的晶圓20那樣，晶片部120x位於比切割部122更靠近晶圓20的外緣側的晶片化區域200的開口線152，係以開口部的寬度朝向晶圓20的中心變寬的方式設定。 如圖16所示，開口線152具有第1線152a、第2線152b、第3線152c和第4線152d。第1線152a是與第1線151a平行地沿圖16中的縱向延伸的切斷預定線。第1線152a的一端部(相當於開口部的開口端的部分)延伸至晶圓20的外緣，另一端部延伸至相當於開口部的基端的位置。第2線152b是以越接近晶圓20的外緣越遠離第1線152a的方式延伸至晶圓20的外緣的切斷預定線。第3線152c是與第1線151a的另一端部連續並且沿圖16中的橫向延伸的切斷預定線。第4線152d是以連接第3線152c和第2線152b的方式延伸的切斷預定線。 這樣的開口線152以開口部的開口角的中心線CL位於從晶圓20的中心(即，切片用帶的中心位置TC)放射狀地擴展的線上的方式設定。 圖17是示出線15的另一設定例的圖。圖17所示的線15大體上與圖16所示的線15相同，但是不同之處在於，晶片劃分線151的第4線151d以橫穿切割部122的方式延伸。在圖17所示的構成中，由於第4線151d以橫穿切割部122的方式延伸，因此切割部122上下分離。在該情況下，如果比較圖16所示的構成和圖17所示的構成，則圖16所示的構成的切割部122的重心遠離晶圓20的中心，分割性變高。這樣，從切割部122的分割性的觀點出發，優選晶片劃分線151以不橫穿切割部122的方式設定。 圖18是示出線15的另一設定例的圖。圖18所示的線15大體上與圖16所示的線15相同，但是不同之處在於，第3線151c和第4線151d延伸至晶圓20的外緣。第3線151c，一端部延伸至相鄰的另一晶片化區域200的第3線1151c，並且另一端部延伸至晶圓20的外緣。此外，第4線151d的兩個端部延伸至晶圓20的外緣。在圖18所示的構成中，切斷預定線變多，晶圓20被更細地分割。如果比較圖16所示的構成和圖18所示的構成，則從上述重心模型的觀點出發，圖16所示的構成的分割性變高。這樣，藉由將切斷預定線的數量設為所需最小限度，擴展工序中的分割性提高。此外，在圖16所示的構成中，也具有切斷個數少，能夠增大晶片尺寸等的優點。另一方面，在圖16所示的構成中，根據切斷預定線的割裂的順序，重心位置時時刻刻變化，移動方向變化(晶片旋轉)，由此存在在擴展工序中發生碎片的情況。在這一點上，例如如圖18所示的構成那樣，藉由增加切斷預定線的個數，能夠減小由於晶片旋轉引起的碎片的風險。此外，在增加切斷預定線的情況下，優選增加與實際發生了碎片的部位有關的切斷預定線。 接著，參照圖19和圖20對開口線152的加工進行詳細說明。圖19是說明開口線152的加工順序的圖。圖19(b)～圖19(i)示出圖19(a)所示的包含於晶圓20的1個晶片化區域200的開口線152的加工順序。在圖19(b)～圖19(i)中，虛線表示未被雷射加工的線，實線表示雷射加工後的線。 如圖19(b)所示，首先，準備設定了雷射加工預定的開口線152(第1線152a、第2線152b、第3線152c、第4線152d)的晶圓20。 接著，如圖19(c)所示，沿第1線152a形成改質區域。第1線152a延伸至晶圓20的外緣。關於第1線152a的內側(晶圓20的中心側)，是不想將與改質區域的形成有關的龜裂延長(想停止龜裂)的部分。因此，對於第1線152a，從內側朝向外側照射雷射光，形成改質區域。在該情況下，以聚光點C從例如比第1線152a的基端(內側的端部)更靠近內側的位置，按照第1線152a的基端、第1線152a的前端(晶圓20的外緣)的順序相對地移動的方式，使支撐部102(參照圖1)移動。比第1線152a的基端更靠近內側的區間設為雷射被關斷(OFF)的雷射關斷區間152x。 接著，如圖19(d)所示，沿第2線152b形成改質區域。第2線152b延伸至晶圓20的外緣。關於第2線152b的內側，是不想將與改質區域的形成有關的龜裂延長的部分。因此，對於第2線152b，從內側朝向外側照射雷射光，形成改質區域。在該情況下，以將比第2線152b的基端(內側的端部)更靠近內側的區間設為雷射關斷區間152x，聚光點C按照雷射關斷區間152x、第2線152b的基端、第2線152b的前端的順序相對地移動的方式，使支撐部102(參照圖1)移動。藉由至此的加工，形成沿第1線152a和第2線152b的改質區域(參照圖19(e))。 接著，如圖19(f)所示，沿第3線152c形成改質區域。對於第3線152c，朝向作為已加工的線的第1線152a照射雷射光，形成改質區域。在該情況下，以比第3線152c的基端(第1線152a側的相反側的端部)更靠近圖19(f)中的右側的區間和比第3線152c的前端(第1線152a側的端部)更靠近圖19(f)中的左側的區間設為雷射關斷區間152x，聚光點C按照雷射關斷區間152x、第3線152c的基端、第3線152c的前端、雷射關斷區間152x的順序相對地移動的方式，使支撐部102(參照圖1)移動。 接著，如圖19(g)所示，沿第4線152d形成改質區域。對於第4線152d，朝向作為已加工的線的第2線152b照射雷射光，形成改質區域。在該情況下，以比第4線152d的基端(第3線152c側的端部)更靠近圖19(g)中的左下側的區間和比第4線152d的前端(第2線152b側的端部)更靠近圖19(g)中的右上側的區間設為雷射關斷區間152x，聚光點C按照雷射關斷區間152x、第4線152d的基端、第4線152d的前端、雷射關斷區間152x的順序相對地移動的方式，使支撐部102(參照圖1)移動。藉由至此的加工，沿開口線152的改質區域全部被形成(參照圖19(h))。 最後，如圖19(i)所示，沿晶片劃分線151的第4線151d形成改質區域。此外，沿第4線151d的改質區域的形成也可以在作為開口線152的第3線152c和第4線152d形成之前實施。沿第4線151d的改質區域的形成以跨越切割部122的方式實施。即，以橫穿切割部122的區間設為雷射關斷區間152x，並且聚光點C按照第4線151d的朝向第1線152a的區間、橫穿切割部122的區間、第4線151d的從第2線152b朝向外側的區間的順序相對地移動的方式，使支撐部102(參照圖1)移動。在該情況下，由於已經形成了第1線152a和第2線152b，因此假定與沿第4線151d的改質區域的形成有關的龜裂在第1線152a和第2線152b處停止。藉由至此的加工，形成沿開口線152和第4線151d的改質區域(參照圖19(j))。 圖20是說明各加工部位中的雷射光束照射的圖。圖20(a)、圖20(b)、圖20(c)和圖20(d)分別示出第1線152a、第2線152b、第3線152c和第4線152d的雷射加工。上段表示沿線的雷射加工，下段表示雷射光束的照射狀態。 如圖20(a)和圖20(c)的下段所示，在與結晶方向(110)相同的方向(即，90度或0度)進行雷射加工的情況下，或者如圖20(d)的下段所示，在相對於結晶方向(110)為45度的方向進行雷射加工的情況下，藉由使加工進行方向和橢圓形的雷射光束的光束形狀一致，能夠實現沿加工進行方向的雷射加工。 另一方面，如圖20(b)的下段所示，在沿相對於結晶方向(110)為上述的90度、0度、45度以外的方向進行雷射加工的情況下，沿相對於加工進行方向與結晶方向側相反方向照射橢圓形的雷射光束。此處的與結晶方向側相反方向是指相對於加工進行方向具有最接近的裂開面的方向的相反方向。由此，能夠在考慮到雷射光束向結晶方向側彎曲(被拉伸)之後，向所期望的加工進行方向照射雷射光束。 此外，從抑制碎片的觀點出發，優選在擴展工序中，儘早地分離切割部122。因此，為了可靠且儘早地分離切割部122，也可以將作為與切割部122有關的切斷預定線的開口線152的雷射加工條件設為比作為另一條切斷預定線的晶片劃分線151的雷射加工條件更容易分割的雷射加工條件。具體地，也可以將沿開口線152形成改質區域時的雷射的掃描數設定得比沿晶片劃分線151形成改質區域時的雷射的掃描數多。 圖21是說明開口線152和晶片劃分線151的加工條件的圖。圖21(a)表示加工對象的晶圓20，圖21(b)表示該晶圓20的晶片化區域200的開口線152，圖21(c)表示開口線152的加工條件(和基於該加工條件的加工結果)，圖21(d)表示晶圓20的晶片化區域200的晶片劃分線151，圖21(e)表示晶片劃分線151的加工條件(和基於該加工條件的加工結果)。 如圖21(c)和圖21(d)所示，例如在400μm的晶圓20的加工中，波長(1080nm)等的條件在沿開口線152的雷射加工和沿晶片劃分線151的雷射加工中是共同的。另一方面，如圖21(c)所示，在沿開口線152的雷射加工中，掃描數為5次(Pass)(圖21(c)中的SD1～SD5)，相對於此，在沿晶片劃分線151的雷射加工中，掃描數為4次(Pass)(SD1～SD4)。這樣，藉由將沿開口線152形成改質區域時的雷射的掃描數設定為比沿晶片劃分線151形成改質區域時的雷射的掃描數多，能夠儘早地對切割部122進行分離。此外，圖21(c)和圖21(d)中的“Z80”“Z75”等的用語是作為進行雷射加工時的加工深度的Z高度的資訊。 接著，對本實施方式的晶圓20和加工方法的作用效果進行說明。 本實施方式的晶圓20是在沿線15形成了改質區域後藉由實施擴展工序而得到多個半導體晶片120的晶圓，具有由作為線15的晶片劃分線151所劃分的多個晶片化區域200，晶片化區域200具有構成半導體晶片120的晶片部120x、以及從晶片部120x切割的部分並且是經由開口線152與晶片部120x連續的切割部122，其中，開口線152是以在半導體晶片120形成有切口形狀的開口部121的方式設定的線15 ，開口線152以開口部121的寬度朝向開口端側變寬或保持恆定的方式設定。 在本實施方式的晶圓20中，在晶片化區域200中，晶片部120x和切割部122經由作為與半導體晶片120的開口部121的形成有關的作為線15的開口線152連續地形成。再有，在本晶圓20中，以開口部121的寬度朝向開口端側變寬或保持恆定的方式設定上述開口線152。藉由這樣設定開口線152，在沿該開口線152形成改質區域並實施擴展工序時，可以抑制晶片部120x(半導體晶片120)和從晶片部120x(半導體晶片120)切割的切割部122之間的接觸。由此，能夠有效地抑制在半導體晶片120產生碎片(破片)。 在上述晶圓20中，也可以是晶片部120x位於比切割部122更靠近晶圓20的中心側的晶片化區域200的開口線152，係以開口部121的寬度朝向晶圓20的外緣變寬或保持恆定的方式設定，晶片部120x位於比切割部122更靠近晶圓20的外緣側的晶片化區域200的開口線152，係以開口部121的寬度朝向晶圓20的中心變寬或保持恆定的方式設定。 根據這樣的構成，在晶片部120x位於比切割部122更靠近晶圓20的中心側的情況、以及位於比切割部122更靠近晶圓20的外緣側的情況下，都能夠適當地抑制晶片部120x和從晶片部120x切割的切割部122之間的接觸。此外，在擴展工序中，當遠離晶圓20的中心的部分(即，晶圓20的外緣側)的位移變得更大時，在晶片部120x位於比切割部122更靠近晶圓20的中心側的構成中，能夠使切割部122沿想要分離的方向(作為遠離晶片部120x的方向的晶圓20的外緣方向)有效地位移，能夠使切割部122的分割性提高，並且能夠更有效地抑制半導體晶片120中的碎片的產生。 在上述晶圓20中，接近晶圓20的外緣的晶片化區域200的開口線152也可以延伸至晶圓20的外緣。這樣，藉由使開口線152延伸至晶圓20的外緣，能夠使切割部122的分割性提高，並且能夠更有效地抑制半導體晶片120中的碎片的產生。 在上述晶圓20中，晶片劃分線151也可以延伸至晶圓20的外緣。這樣，藉由晶片劃分線151延伸至晶圓20的外緣，能夠使晶片部120x的分割性提高。 在上述晶圓20中，也可以是多個晶片化區域200從晶圓20的中心放射狀地配置，晶片部120x和切割部122在從晶圓20的中心放射狀地擴展的線上連續地依次設置。作為擴展裝置，在使用將晶圓20放射狀地擴張的裝置的情況下，多個晶片化區域200從晶圓20的中心放射狀地配置，藉由將晶片部120x和切割部122在從晶圓20的中心放射狀地擴展的線上連續地依次設置，沿擴張方向配置多個晶片化區域200的晶片部120x和切割部122。藉由利用上述擴展裝置擴張這樣的晶圓20，能夠使分割性提高，並且能夠有效地抑制在半導體晶片120產生碎片。 在上述晶圓20中，開口線152也可以以開口部121的開口角的中心線位於從晶圓20的中心放射狀地擴展的線上的方式設定。作為擴展裝置，在使用將晶圓20放射狀地擴張的裝置的情況下，藉由使開口部121的開口角的中心線位於從晶圓20的中心放射狀地擴展的線上，能夠適當地抑制晶片部120x和切割部122的接觸，並且可以使晶片部120x和切割部122分離。即，能夠更有效地抑制在半導體晶片120產生碎片(破片)。 開口線152也可以以在擴展工序中避免晶片部120x和切割部122的接觸的方式設定。藉由這樣設定開口線152，在沿該開口線152形成改質區域並且實施擴展工序時，可以抑制晶片部120x和切割部122的接觸。由此，能夠有效地抑制在半導體晶片120產生碎片(破片)。 本實施方式的晶圓20的加工方法包括：準備晶圓20的工序，其中，晶圓20具有由作為線15的晶片劃分線151劃分的多個晶片化區域200，晶片化區域200具有構成半導體晶片120的晶片部120x、以及從晶片部120x切割的部分並且是經由開口線152與晶片部120x連續的切割部122，其中，開口線152是以在半導體晶片部120x形成有切口形狀的開口部121的方式設定的線15；沿線15照射雷射光而形成改質區域的工序；以及藉由擴張貼附於形成了改質區域的晶圓20的切片用帶，將晶片部120x和切割部122隔開間隔而分離，得到半導體晶片120的工序。 在本實施方式的晶圓20的加工方法中，在晶片化區域200中，準備晶片部120x和切割部122經由作為與半導體晶片120的開口部121的形成有關的線15的開口線152連續地形成的晶圓20。然後，對該晶圓20沿線15形成改質區域，藉由對貼附於該晶圓20的切片用帶進行擴張，得到半導體晶片120。在此，在本加工方法中，在得到半導體晶片120的工序中，晶片部120x和切割部122隔開間隔而分離。由此，能夠抑制晶片部120x(半導體晶片120)和從晶片部120x(半導體晶片120)切割的切割部122的接觸，並且能夠有效地抑制在半導體晶片120產生碎片(破片)。 在上述加工方法中，也可以是多個晶片化區域200從晶圓20的中心放射狀地配置，晶片部120x和切割部122在從晶圓20的中心放射狀地擴展的線上連續地依次設置，在擴展工序中將貼附於晶圓20的切片用帶沿從晶圓20的中心放射狀地延伸的方向擴張。由此，能夠使晶片部120x和切割部122連續地依次設置的方向和擴張方向對準，能夠使分割性提高，並且能夠有效地抑制在半導體晶片120產生碎片。 在上述加工方法中，接近晶圓20的外緣的晶片化區域200的開口線152也可以延伸至晶圓20的外緣。這樣，藉由開口線152延伸至晶圓20的外緣，能夠使切割部122的分割性提高，並且能夠更有效地抑制半導體晶片120中的碎片的產生。 在上述加工方法中，在形成改質區域的工序中，對於延伸至晶圓20的外緣的開口線152，也可以從該開口線152的內側朝向外側照射雷射光而形成改質區域。根據這樣的構成，能夠在開口線152的內側停止由於改質區域的形成而引起的龜裂，在外側延長由於改質區域的形成而引起的龜裂。由此，能夠在想要停止龜裂的部分(成為半導體晶片120的開口線152的內側)適當地停止龜裂。 在上述加工方法中，在形成改質區域的工序中，也可以相對於加工進行方向沿與結晶方向側相反方向照射橢圓形的雷射光束。關於雷射光束，當存在向結晶方向側彎曲(向結晶方向側拉伸)的情況時，考慮到藉由將橢圓形的雷射光束相對於加工進行方向向與結晶方向側相反方向照射而向上述的結晶方向側彎曲，能夠將雷射光束沿期望的加工進行方向照射。即，根據這樣的構成，能夠實現沿線15的改質區域的形成。 在上述加工方法中，在形成改質區域的工序中，沿開口線152形成改質區域時的雷射光的掃描數也可以設定為比沿晶片劃分線151形成改質區域時的雷射光的掃描數多。根據這樣的構成，用於將切割部122切割的雷射光的掃描數比用於將晶片部120x從晶圓20切割的雷射光的掃描數多，在晶圓20擴張時，能夠使切割部122儘早地分離。藉由儘早地將切割部122分離，能夠儘早地確定晶圓20的重心，能夠避免因重複重心移動而使切割部122和晶片部120x容易接觸，從而在半導體晶片120產生碎片的情況。 在上述加工方法中，晶片劃分線151也可以延伸至晶圓20的外緣。這樣，藉由晶片劃分線151延伸至晶圓20的外緣，能夠使晶片部120x的分割性提高。 上述加工方法包括：準備上述晶圓20的工序；沿線15形成改質區域的工序；以及藉由擴張貼附於形成了改質區域的晶圓20的切片用帶，得到多個半導體晶片120的工序。根據這樣的晶圓20的加工方法，能夠抑制晶片部120x(半導體晶片120)和從晶片部120x(半導體晶片120)切割的切割部122的接觸，並且能夠有效地抑制在半導體晶片120產生碎片(破片)。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In each drawing, the same symbols are used for the same or corresponding parts, and repeated descriptions are omitted. In this embodiment, a modified region is formed inside the wafer (object). As an apparatus for forming a modified region inside a wafer, for example, the laser processing apparatus 100 shown in FIG. 1 can be used. As shown in FIG. 1 , the laser processing apparatus 100 includes a support part 102, a light source 103, an optical axis adjustment part 104, a spatial light modulator 105, a light condensing part 106, an optical axis monitoring part 107, a visible light imaging part 108A, and an infrared imaging part. 108B, moving mechanism 109, and management unit 150. The laser processing device 100 is a device that forms the modified region 11 on the wafer 20 by irradiating the wafer 20 with laser light L0. In the following description, three directions that are orthogonal to each other are referred to as the X direction, the Y direction, and the Z direction respectively. As an example, the X direction is a first horizontal direction, the Y direction is a second horizontal direction perpendicular to the first horizontal direction, and the Z direction is a vertical direction. The support part 102 supports the wafer 20 by, for example, adsorbing the wafer 20 . The support part 102 can move in each direction of the X direction and the Y direction. The support part 102 can rotate about the rotation axis along the Z direction. The light source 103 emits laser light L0 by, for example, pulse oscillation. The laser light L0 is transparent to the wafer 20 . The optical axis adjustment unit 104 adjusts the optical axis of the laser light L0 emitted from the light source 103 . The optical axis adjustment unit 104 is composed of, for example, a plurality of mirrors whose positions and angles can be adjusted. The spatial light modulator 105 is arranged in the laser processing head H. The spatial light modulator 105 modulates the laser light L0 emitted from the light source 103. The spatial light modulator 105 is a spatial light modulator (SLM) of a reflective liquid crystal (LCOS: Liquid Crystal on Silicon). In the spatial light modulator 105, the laser light L0 can be modulated by appropriately setting the modulation pattern displayed on its display portion (liquid crystal layer). In the present embodiment, the laser light L0 traveling downward in the Z direction from the optical axis adjustment unit 104 enters the laser processing head H, is reflected by the mirror MM1, and enters the spatial light modulator 105. The spatial light modulator 105 reflects and modulates the incident laser light L0. The light condensing part 106 is installed on the bottom wall of the laser processing head H. The light condensing part 106 focuses the laser light L0 modulated by the spatial light modulator 105 onto the wafer 20 supported by the supporting part 102 . In this embodiment, the laser light L0 reflected by the spatial light modulator 105 is reflected by the dichroic mirror MM2 and enters the light condensing part 106 . The light condensing unit 106 condenses the incident laser light L0 onto the wafer 20 . The condensing unit 106 is configured by mounting the condensing lens unit 161 on the bottom wall of the laser processing head H via the driving mechanism 162 . The driving mechanism 162 moves the condenser lens unit 161 in the Z direction using, for example, the driving force of a piezoelectric element. Furthermore, in the laser processing head H, an imaging optical system (not shown) is arranged between the spatial light modulator 105 and the light condensing unit 106 . The imaging optical system constitutes a bilateral telecentric optical system in which the reflective surface of the spatial light modulator 105 and the entrance pupil surface of the light condensing part 106 are in an imaging relationship. Thereby, the image of the laser light L0 on the reflective surface of the spatial light modulator 105 (the image of the laser light L0 modulated by the spatial light modulator 105) is transferred (imaged) to the incident light of the light condensing unit 106 Pupil face. A pair of distance sensors S1 and S2 is mounted on the bottom wall of the laser processing head H so as to be located on both sides of the condenser lens unit 161 in the X direction. Each ranging sensor S1 and S2 emits ranging light (for example, laser) to the laser light incident surface of the wafer 20, and detects the laser light incidence by detecting the ranging light reflected on the laser light incident surface. Surface displacement data. The optical axis monitoring unit 107 is arranged in the laser processing head H. The optical axis monitoring unit 107 detects a part of the laser light L0 that has passed through the dichroic mirror MM2. The detection result of the optical axis monitoring unit 107 represents, for example, the relationship between the optical axis of the laser light L0 incident on the condenser lens unit 161 and the optical axis of the condenser lens unit 161 . The visible light imaging unit 108A emits visible light V0 and acquires an image of the wafer 20 based on the visible light V0 as an image. The visible light imaging unit 108A is arranged in the laser processing head H. The infrared imaging unit 108B emits infrared light and acquires an image of the wafer 20 based on the infrared light as an infrared image. The infrared imaging unit 108B is installed on the side wall of the laser processing head H. The moving mechanism 109 includes a mechanism that moves at least one of the laser processing head H and the support part 102 in the X direction, the Y direction, and the Z direction. The moving mechanism 109 drives at least one of the laser processing head H and the support part 102 by the driving force of a known driving device such as a motor to move the focusing point C of the laser light L0 in the X direction, the Y direction, and the Z direction. . The moving mechanism 109 includes a mechanism for rotating the support portion 102 . The moving mechanism 109 rotates and drives the support portion 102 by the driving force of a known driving device such as a motor. The management unit 250 has a control part 251, a user interface 252 and a memory part 253. The control unit 251 controls the operations of each unit of the laser processing apparatus 100 . The control unit 251 is configured as a computer device including a processor, a memory, a storage, a communication device, and the like. In the control unit 251, the processor executes software (program) read into the memory or the like, and controls reading and writing of data in the memory and storage, as well as communication with the communication device. The user interface 252 displays and inputs various data. The user interface 252 constitutes a GUI (Graphical User Interface) of an operating system having a graphics base. The user interface 252 includes, for example, at least any one of a touch panel, a keyboard, a mouse, a microphone, a tablet terminal, a monitor, and the like. The user interface 252 may accept various inputs, for example, through touch input, keyboard input, mouse operation, voice input, etc. The user interface 252 can display various information on its display screen. The user interface 252 corresponds to an input accepting unit that can accept input and a display unit that displays a setting screen based on the accepted input. The storage unit 253 is, for example, a hard disk, and stores various data. In the laser processing apparatus 100 configured as above, when the laser light L0 is condensed inside the wafer 20 , the laser light is absorbed in a portion corresponding to the focusing point (at least a part of the focusing area) C of the laser light L0 L, the modified region 11 is formed inside the wafer 20 . The modified region 11 is a region whose density, refractive index, mechanical strength, and other physical properties are different from those of the surrounding non-modified region. Examples of the modified region 11 include a melt-processed region, a crack region, a dielectric breakdown region, a refractive index change region, and the like. The modified region 11 includes a plurality of modified points 11s and cracks extending from the plurality of modified points 11s. As an example, the operation of the laser processing apparatus 100 in the case of forming the modified region 11 inside the wafer 20 along the line 15 for cutting the wafer 20 (the planned cutting line) will be described. First, the laser processing apparatus 100 rotates the support part 102 so that the line 15 set on the wafer 20 is parallel to the X direction. The laser processing apparatus 100 moves the support part 102 in each direction of the X direction and the Y direction based on the image acquired by the infrared imaging part 108B (for example, an image of the functional element layer included in the wafer 20), so that the support part 102 moves from the X direction to the Y direction. When viewed in the Z direction, the focusing point C of the laser light L0 is located on the line 15 . The laser processing apparatus 100 moves the laser processing head H (that is, the light condensing unit 106 ) in the Z direction based on the image (for example, the image of the laser light incident surface of the wafer 20 ) acquired by the visible light imaging unit 108A. Set) so that the focusing point C of the laser light L0 is located on the laser light incident surface. The laser processing apparatus 100 moves the laser processing head H in the Z direction based on this position so that the focusing point C of the laser light L0 is located at a predetermined depth from the laser light incident surface. Next, the laser processing apparatus 100 emits the laser light L0 from the light source 103 and moves the support portion 102 in the X direction so that the focusing point C of the laser light L0 moves relatively along the line 15 . At this time, the laser processing device 100 uses the displacement data of the laser light incident surface obtained by the one of the pair of distance sensors S1 and S2 located on the front side in the processing direction of the laser light L0 to cause the light condensing unit to The driving mechanism 162 of 106 operates so that the focusing point C of the laser light L0 is located at a predetermined depth from the laser light incident surface. Thereby, one row of modified regions 11 is formed along the line 15 at a certain depth from the laser light incident surface of the wafer 20 . When the laser light L0 is emitted from the light source 103 in the pulse oscillation mode, a plurality of modified points 11s are formed in a row along the X direction. One modified point 11s is formed by the irradiation of one pulse of laser light L0. One row of modified regions 11 is a set of a plurality of modified points 11s arranged in one row. The adjacent modified points 11s may be connected to each other or separated from each other depending on the pulse pitch of the laser light L0 (the value obtained by dividing the relative movement speed of the light focusing point C with respect to the wafer 20 by the repetition frequency of the laser light L0). condition. As shown in FIGS. 2 and 3 , the wafer 20 has a semiconductor substrate (substrate) 21 and a functional element layer 22 . In addition, in FIGS. 2 and 3 , the structure of the wafer 20 is simplified. The detailed structure of the wafer 20 will be described later. The thickness of the wafer 20 is, for example, 775 μm. The semiconductor substrate 21 has a front surface 21a and a back surface 21b. The semiconductor substrate 21 is, for example, a silicon substrate. The semiconductor substrate 21 is provided with a notch 21c indicating the crystal direction. In the semiconductor substrate 21, an orientation plane may also be provided as an alternative to the notches 21c. The functional element layer 22 is formed on the surface 21a of the semiconductor substrate 21. The functional element layer 22 includes a plurality of functional elements 22a. The plurality of functional elements 22 a are two-dimensionally arranged along the surface 21 a of the semiconductor substrate 21 . Each functional element 22a is, for example, a light-receiving element such as a photodiode, a light-emitting element such as a laser diode, a circuit element such as a memory, or the like. Each functional element 22a may be formed three-dimensionally by stacking a plurality of layers. A plurality of streets 23 are formed on the wafer 20 . The plurality of streets 23 are areas exposed to the outside between adjacent functional elements 22a. That is, the plurality of functional elements 22 a are arranged adjacent to each other via the street 23 . As an example, the plurality of streets 23 may extend in a lattice shape so as to pass between adjacent functional elements 22a with respect to the plurality of functional elements 22a arranged in a matrix. As shown in FIGS. 2 and 3 , a plurality of lines 15 are set on the wafer 20 . The wafer 20 is scheduled to be cut along each of the plurality of lines 15 for each functional element 22 a (that is, to be wafered for each functional element 22 a). When viewed from the thickness direction of the wafer 20 , each line 15 passes through each street 23 . As an example, when viewed from the thickness direction of the wafer 20 , each line 15 extends to pass through the center of each street 23 . Each line 15 is a virtual line set on the wafer 20 by the laser processing apparatus 100 . Each line 15 may be a line actually drawn on the wafer 20 . In addition, the line 15 as the planned cutting line is not limited to the case where the street 23 is formed as a pattern as in the present embodiment (that is, the unnecessary film is removed from the street 23 in advance by a pattern mask or is arranged on the street 23 In the case of TEG) visually identifiable lines. For example, instead of forming the street 23 as a pattern (the street 23 has the same structure as the active area in the design), the line 15 may be estimated from a reference position in the design. In addition, when the wafer is a bare wafer, the design line 15 may be estimated using the notch or the orientation plane as a reference. Next, a laser processing method using the laser processing apparatus 100 will be described with reference to FIG. 4 . FIG. 4 is a flowchart showing a method of processing the wafer 20 . The wafer 20 is a wafer in which a plurality of semiconductor wafers are obtained by performing an expansion process after the modified region 11 is formed along the line 15 . As shown in FIG. 4 , first, the wafer 20 is prepared (step S11 ). Details of the prepared wafer 20 will be described later. Then, a dicing tape is attached to the back surface 21 b of the semiconductor substrate 21 of the wafer 20 . In addition, before attaching the slicing tape to the wafer 20 , a grinding process of grinding the wafer 20 and a grooving process of removing the surface layer of the street 23 may be performed. Next, in the laser processing apparatus 100, the wafer 20 is irradiated with the laser light L0 along the line 15, so that the modified region 11 is formed inside the wafer 20 along the line 15 (step S12). Here, with the slicing tape attached to the back surface 21 b of the semiconductor substrate 21 , the wafer 20 is attracted and supported by the support portion 102 , and then the focusing point of the laser light L0 is aligned with the semiconductor substrate 21 via the slicing tape. Inside, the back surface 21b is used as the laser light incident surface, and the laser light L0 is irradiated onto the wafer 20 . Next, the attached slicing tape is expanded (expanded) in an expanding device (not shown) (step S13). Thereby, the cracks extend in the thickness direction of the wafer 20 from the modified region 11 formed inside the semiconductor substrate 21 along each line 15 , and the wafer 20 is cut along the lines 15 . Thereby, the wafer 20 is wafered for each functional element 22a, and a plurality of semiconductor wafers are obtained. Specifically, the wafer portion 120x and the dicing portion 122 are separated by a gap by expanding the dicing tape attached to the wafer 20 in which the modified region 11 is formed (for example, see FIG. 10(b) , details will be given later). (described in the text), a semiconductor wafer is obtained. Next, the semiconductor wafer obtained by the above laser processing method will be described in detail. In this embodiment, notch-shaped openings are formed in a plurality of semiconductor wafers obtained from the wafer 20 . Such openings are formed according to the use of the semiconductor wafer. 5 and 6 are diagrams illustrating a use example of the semiconductor wafer 120 in which the opening 121 is formed. In the example shown in FIG. 5 , the semiconductor wafer 120 functioning as an optical semiconductor sensor has an opening 121 as a positioning (alignment) portion when installed in the light-related product 400 . That is, the semiconductor wafer 120 has the opening 121 as a portion fitted to the protrusion 401 of the optical-related product 400 . In the example shown in FIG. 6 , the semiconductor wafer 120 has an opening 121 as a hole through which light output from the light-emitting element 500 passes toward the data 600 . Here, when obtaining the semiconductor wafer 120 in which the opening 121 is formed, it is necessary to separate the portion where the opening 121 is formed from the portion that becomes the semiconductor wafer 120 (constituting the semiconductor wafer 120 ), that is, the wafer portion. In this case, it is considered that if the portion where the opening 121 is formed is separated from the wafer portion by expanding the wafer 20 in the expansion process, the contact between the portion where the opening 121 is formed and the wafer portion will occur after separation. Debris (fragments) may occur on the semiconductor wafer 120 . FIG. 7 is a diagram explaining the generation of debris. FIG. 7( a ) shows an example in which four wafering regions 200 are formed on the wafer 20 . The wafering region 200 includes a wafer portion 120x that constitutes the semiconductor wafer 120 after the expansion process, and a cutting portion 122 that is cut from the wafer portion 120x and forms the opening 121 of the semiconductor wafer 120. That is, by separating the dicing part 122 from the wafer part 120x, the semiconductor wafer 120 in which the opening part 121 is formed is obtained. Wafering area 200 is generally rectangular. In the longitudinal direction of the wafering region 200, the cutting portion 122 is formed symmetrically (right and left) with respect to the center. As shown in FIG. 7(a) , the four wafering areas 200 are arranged in four areas divided by diagonal lines passing through the center of the wafer 20 (the upper left area, the upper right area, and the lower left area in FIG. 7(a) , lower right area). Now, in the expansion device (not shown), the slicing tape attached to the wafer 20 is expanded radially from the center of the wafer 20 . In this case, as shown in FIG. 7( b ), in the upper left wafering region 200 in FIG. 7( a ), the cutting part 122 separated from the wafer part 120 x is considered to be in contact with the upper left part of the wafer part 120 x. In addition, as shown in FIG. 7(c) , in the upper right wafering region 200 in FIG. 7(a) , the cutting part 122 separated from the wafer part 120x is considered to be in contact with the upper right part of the wafer part 120x. Furthermore, as shown in FIG. 7(d) , it is considered that the cutting part 122 separated from the wafer part 120x is in contact with the upper right part of the wafer part 120x in the lower left wafering area 200 in FIG. 7(a) . In addition, as shown in FIG. 7(e) , in the lower right wafering region 200 in FIG. 7(a) , it is considered that the cutting part 122 separated from the wafer part 120x is in contact with the upper left part of the wafer part 120x. These contacts occur, for example, because a portion closer to the outer edge of the wafer 20 is significantly displaced (details will be described later). In this way, in each wafering area 200, due to the contact between the cutting part 122 and the wafer part 120x, there is a possibility that chips (fragments) may occur in the semiconductor wafer 120 after the expansion process. The principle of fragment generation will be described in detail with reference to FIGS. 8 and 9 . In addition, the fragment generation principle explained here is an example and is not limited to this. FIG. 8 is a diagram explaining the displacement amount of each part of the wafer 20 in the expansion process. 8(a) and 8(b) illustrate the state of the wafer 20 when the slicing tape attached to the wafer 20 expands in a direction extending radially from the center of the wafer 20. In the expansion process, the center of the wafer 20 substantially coincides with the center of the slicing tape on which the expansion is performed. Now, wafering areas 201, 202 are provided in the wafer 20 that are separated from each other and adjacent to each other. The wafering area 201 is closer to the center side of the wafer 20 than the wafering area 202 . Here, the amount of displacement in the expansion process increases as the distance from the center position of the expansion (here, the center of the wafer 20 ) increases. Therefore, the displacement amount of the wafering area 202 is greater than the displacement amount of the wafering area 201 . In addition, although the slicing tape can expand and contract through the expansion process, each wafer 201 and 202 of the wafer 20 that are hard enough to be regarded as rigid bodies do not expand and contract (do not deform). The slicing tape on the attached surface of the 202 contact also does not stretch. Therefore, within the wafering region 201, the amount of displacement is constant regardless of the distance from the expanded center position. Similarly, in the wafering area 202, the displacement amount is constant regardless of the distance from the expanded center position. That is, as shown in the size (thickness) of the arrows in the wafering regions 201 and 202 in FIG. 8(a) , a state in which uniform stress is applied is formed in one wafering region. As a result, the displacement of the wafering region is approximately equal to the average displacement of the slicing belt within the wafering region. Therefore, the displacement of the wafering area is determined by a center-of-gravity model represented by the distance between the center of gravity position of the wafering area and the center position of the slicing belt (the belt center position). That is, the displacement of the wafering region is approximately proportional to the distance between the center of gravity position of the wafering region and the belt center position. As shown in FIG. 8( b ), the displacement of the wafering area 201 is determined by the distance between the center of gravity position 201 c of the wafering area 201 and the belt center position TC. In addition, the displacement of the wafering area 202 is determined by the distance between the center of gravity position 202c of the wafering area 202 and the belt center position TC. Now, since the distance between the center of gravity position 202c of the wafering region 202 and the belt center position TC is larger than the distance between the center of gravity position 201c of the wafering region 201 and the belt center position TC, compared with the wafering region 201, as The wafering region 202 of the wafering region on the outer edge side is more displaced toward the expansion direction (outer edge side). Therefore, the wafering area 202 is more divisible (can be completely divided) than the wafering area 201 . Based on the above-mentioned center of gravity model, the manner in which fragmentation occurs will be explained in detail. FIG. 9 is a diagram explaining the generation of debris. FIG. 9(a) shows one wafering area 300. The wafering region 300 has a wafer portion 320x, which constitutes a semiconductor wafer after the expansion process, and a cutting portion 322, which is a portion cut from the wafer portion 320x and forms an opening of the semiconductor wafer. The wafer portion 320x is arranged to surround the cutting portion 322 and has a portion 325 closer to the outer edge than the cutting portion 322 and a portion 326 closer to the center in the radial direction of the wafer 20 . In addition, the gravity center position 320c of the wafer part 320x is located closer to the belt center position TC than the gravity center position 322c of the cutting part 322. In this case, according to the above-mentioned center of gravity model, the displacement amount of the cutting portion 322 in the expansion direction (outer edge side) is larger than the displacement amount of the wafer portion 320x. Furthermore, as mentioned above, since the wafer portion 320x has the portion 325 closer to the outer edge side than the cutting portion 322, the portion 325 on the outer edge side comes into contact with the cutting portion 322 having a large displacement amount. In this case, debris may occur in the outer edge side portion 325 of the wafer portion 320x. In addition, there may be cases where the cutting portion 322 cannot be appropriately divided. In contrast, for example, as shown in FIG. 9( b ), in one wafering region 200 , there is no wafer 20 with wafer portion 420x in the displacement direction (that is, the outer edge side) of the cutting portion 422 with a large displacement amount. , the cutting part 422 does not contact the wafer part 420x during the expansion process. In this case, no chips are generated in the wafer portion 420x, and the cutting portion 422 can be appropriately divided. In this way, by arranging the wafer portion and the cutting portion in the wafering region, the generation of debris in the expansion process can be suppressed. Hereinafter, an arrangement example of the wafering region for suppressing debris will be described with reference to FIGS. 10 to 13 . FIG. 10 is a diagram showing an arrangement example of the wafering region 200 for suppressing debris. The arrangement of the wafering area 200 of the wafer 20 shown in FIG. 10(a) is the same as the arrangement of the above-mentioned FIG. 7(a). That is, in the wafer 20 shown in FIG. 10( a ), one substantially rectangular wafering region 200 is provided in each of four regions divided by a diagonal line passing through the center of the wafer 20 . The long side of each wafered area 200 extends parallel to one diagonal line, and the short side extends parallel to the other diagonal line. In addition, in each wafering area 200, the cutting portion 122 is provided so as to be symmetrical (right and left) with respect to the central portion in the longitudinal direction. The cutting portion 122 is provided on one end side (the upper side in FIG. 10( a )) of the wafering region 200 in the transverse direction. Such a wafer 20 is expanded in a direction extending radially from the center in the expansion step in a state where the center of the wafer 20 coincides with the center position TC of the slicing belt as shown in FIG. 10( a ). Now, as shown in the partial enlarged view of FIG. 10( a ), the center of gravity position 120 c of the wafer part 120 x is located closer to the belt center position TC than the center of gravity position 122 c of the cutting part 122 . In this case, according to the above-mentioned center of gravity model, the displacement amount of the cutting portion 122 in the expansion direction (outer edge side) is larger than the displacement amount of the wafer portion 120x. Furthermore, since the upper right portion of the wafer portion 120x exists in the displacement direction of the cutting portion 122 (that is, on the outer edge side), the cutting portion 122 comes into contact with the upper right portion of the wafer portion 120x. In this way, when there is a portion of the wafer portion 120x with a small displacement in the displacement direction of the cutting portion 122 with a large displacement, the cutting portion 122 comes into contact with the wafer portion 120x. In this case, debris may occur in the wafer portion 120x. 10(b) and 10(c) are diagrams showing the configuration of the wafering region 200 that suppresses the generation of debris. In FIGS. 10(b) and 10(c) , the individual structure of the wafering region 200 is the same as that in FIG. 10(a) , but the arrangement of each wafering region 200 is different from that in FIG. 10(a) . In the example shown in FIG. 10( b ), the wafering regions 200 are respectively provided in four directions at 45 degrees with respect to the diagonal line passing through the center of the wafer 20 . The distances from the center of the wafer 20 to the four wafering areas 200 are consistent with each other. The wafering area 200 is arranged such that its short side is perpendicular to a radial line passing through the center of the wafer 20 and at an angle of 45 degrees to the diagonal. In addition, the wafering region 200 is provided such that the cutting portion 122 is arranged on the outer edge side of the wafer 20 . In this structure, as shown in the partial enlarged view of FIG. 10( b ), the center of gravity position 120 c of the wafer part 120 x and the center of gravity position 122 c of the cutting part 122 are located on a line that is 45 degrees relative to the diagonal line from the center position TC of the belt. . In addition, there is no wafer portion 120x in the displacement direction of the cutting portion 122 with a large displacement amount. Therefore, the cutting portion 122 does not come into contact with the wafer portion 120x during the expansion process, and the occurrence of debris in the wafer portion 120x can be suppressed. In the example shown in FIG. 10(c) , four wafering areas 200 are provided by rotating the four wafering areas 200 shown in FIG. 10(b) by 45 degrees. That is, the four wafering areas 200 are respectively arranged on diagonal lines. In such a structure, as shown in the partial enlarged view of FIG. 10(c) , the gravity center position 120c of the wafer part 120x and the gravity center position 122c of the cutting part 122 are located on the diagonal line. In addition, there is no wafer portion 120x in the displacement direction of the cutting portion 122 with a large displacement amount. Therefore, the cutting portion 122 does not come into contact with the wafer portion 120x during the expansion process, and the occurrence of debris in the wafer portion 120x can be suppressed. In addition, the generation of debris is suppressed in both the configurations of Fig. 10(b) and Fig. 10(c). However, for example, the cut angle of the wafer is 45 degrees (crystal direction) in the configuration of Fig. 10(b). In the case of a <100> wafer, (100)) is different from the structure in Fig. 10(c) which is 0 degrees (in the case of a crystallographic direction <100> wafer, (110)) (the cutting orientation changes). In the stealth slice forming the modified region, the cutting in the cutting direction (110) becomes good, so the arrangement in FIG. 10(c) is preferred. FIG. 11 is a diagram showing an arrangement example of the wafering region 200 for suppressing debris. As explained with reference to FIG. 10 , for the wafering areas 200 having the bilaterally symmetrical cutting portions 122 , for example, by arranging four wafering areas 200 on diagonals, chipping can be effectively suppressed. Here, as shown in the partial enlarged view of FIG. 11( a ), for the wafering region 200 provided with the left-right asymmetrical cutting portion 122 , even when it is provided on a diagonal line, there are fragments and the cutting portion 122 Undivided situation. In the wafering region 200 provided with such a left-right asymmetrical cutting portion 122, the center line of the opening angle of the portion that becomes the opening after the expansion process is located on a line that extends radially from the center of the wafer 20. Set the angle (see Figure 11(b)) or position (see Figure 11(c)). This can suppress the generation of fragments and the undivided cutting portion 122 . The center line of the opening angle of the portion that becomes the opening after the expansion process will be described in detail. As described above, the cutting portion 122 is a portion that forms the opening 121 of the semiconductor wafer 120 . In other words, the “center line of the opening angle of the portion that becomes the opening” is the intersection point between the two sides connected to the opening end of the dicing portion 122 (the two sides when the wafer 20 is viewed from above) extending toward the center of the wafer 20 and the opening. A line connecting the midpoints of the ends. In the example shown in FIG. 11( b ), the center line of the opening angle of the portion that becomes the opening is located on a line extending radially from the center of the wafer 20 (that is, connected to the center of the wafer 20 , Each wafering region 200 is arranged to be inclined (specifically, inclined at 8 degrees) from the state of FIG. 11(a) so as to match the displacement vector in the expansion process. In addition, in the example shown in FIG. 11( c ), the center line of the opening angle of the portion that becomes the opening is located on a line extending radially from the center of the wafer 20 (that is, on the line connected to the wafer 20 The wafering regions 200 are arranged to be shifted in the circumferential direction from the state in FIG. 11(a) so that the center coincides with the displacement vector in the expansion process. FIG. 12 is a diagram explaining various arrangement examples of wafering regions. In the wafering areas shown in FIGS. 12(a) to 12(i) , the wafer portion 120x exists closer to the center side of the wafer than the cutting portion 122. In the example shown in FIG. 12(a) , the wafering region has left-right symmetrical cutting portions 122 . The cutting portion 122 is provided so that the width of the opening 121 becomes wider toward the opening end side (the outer edge side of the wafer). In this way, by providing the cutting portion 122 so that the width of the opening 121 becomes wider toward the opening end side, the generation of fragments can be appropriately suppressed and the separability of the cutting portion 122 can be improved. In the example shown in FIG. 12(b) , the wafering region has a left-right asymmetrical cutting portion 122 . The cutting portion 122 is provided so that the width of the opening 121 becomes wider toward the opening end side (the outer edge side of the wafer). However, compared with the configuration of FIG. 12( a ), the opening width is narrower. For such a left-right asymmetric cutting portion 122, as described above, the generation of fragments can be suppressed by adjusting the angle (see Fig. 11(b)) or the position (see Fig. 11(c)). In addition, since the opening width is narrow, the divisibility of the cutting part 122 can be ensured although it is inferior to the structure of FIG. 12(a) . In the example shown in FIG. 12(c) , the wafering area has a circular cutting portion 122 . When forming a modified region along the line of such a circular cutting portion 122, for example, a linear processing table is used to perform a plurality of tangential processes, and the plurality of tangential lines are connected to form a substantially circular shape. With such a configuration, it is possible to appropriately suppress the generation of fragments and improve the divisibility of the cutting portion 122 . In the example shown in FIG. 12(d) , the wafering region has a triangular cut portion 122 that widens toward the opening end side (the outer edge side of the wafer). Such a triangular dicing portion 122 can also suppress the generation of debris and divide the dicing portion 122 . However, since the center side of the wafer (the tip side of the triangle) is sharp, the expansion direction in the expansion process is different from what is expected. case, there is a risk of becoming fragmented. In the examples shown in FIGS. 12(e) and 12(f) , the cutting portion 122 is provided so that the width of the opening 121 becomes constant toward the opening end side (the outer edge side of the wafer). Such cutting portion 122 cannot be divided by the expansion process alone, but can be appropriately divided by etching before the expansion process. When performing the etching process, for example, laser light is incident from the back surface 21b to form a modified region on the wafer 20, and then the entire surface of the wafer 20 is etched from the back surface 21b, and then the tape is attached to the back surface 21b. Implement expansion process. In addition, in the etching process, a mask may be attached for selective etching, and etching of only the slice street may be performed, or etching of only the opening line 152 (refer to FIG. 16) mentioned later may be performed. In addition, a mask may be attached for surface protection, and etching may be performed from the surface 21a. In the example shown in FIG. 12(g) , the cutting portion 122 is provided so that the width of the opening 121 becomes narrower toward the opening end side (the outer edge side of the wafer). For such a cutting part 122, the cutting part 122 cannot be divided by an expansion process. In the example shown in FIG. 12(h) , two cutting units 122 are provided corresponding to one wafer unit 120x. In this way, a plurality of cutting units 122 may be provided for one wafer unit 120x. In the example shown in FIG. 12(i) , the shape of the wafer portion 120x is not a rectangle but includes an irregular shape. Even when such a wafer portion 120x is used, it is possible to appropriately suppress the generation of debris and improve the divisibility of the cutting portion 122 . FIG. 13 is a diagram showing an arrangement example of a wafering region that suppresses debris. In the example shown in FIG. 13 , four wafering areas 200 are provided on a diagonal line passing through the center of the wafer 20 . In each wafering area 200 , the wafer portion 120 x is located closer to the outer edge side of the wafer 20 than the dicing portion 122 . The width of the cutting portion 122 serving as the opening is formed so as to become wider toward the center of the wafer 20 . In the example shown in FIG. 13 , the wafer portion 120x exists on the outer edge side, and the displacement amount of the wafer portion 120x is larger than the displacement amount of the cutting portion 122 in the expansion process. In this case, in the expansion process, the cutting part 122 is less likely to come into contact with the wafer part 120x, and the occurrence of debris in the wafer part 120x can be suppressed. Next, an example of the expansion process will be described with reference to FIGS. 14 and 15 . FIG. 14 is a diagram explaining an example of the expansion process. In the example shown in FIG. 14 , in the wafer 20 , a plurality of wafering regions are arranged radially from the center of the wafer 20 , and the wafer portion 120 x and the cutting portion 122 are located in the wafer 20 . Set up continuously online. For such a wafer 20, in the expansion process, as shown in FIG. 14, a circular expansion type expander is used, and the slicing tape attached to the wafer 20 extends in a direction radially extending from the center of the wafer 20. expansion. In this case, since the wafer portion 120x does not exist in the displacement direction of the cutting portion 122 that is disposed on the outer edge side and has a large displacement amount, the generation of fragments of the wafer portion 120x can be suppressed and the cutting portion 122 can be reliably divided. FIG. 15 is a diagram explaining another example of the expansion process. In the example shown in FIG. 15 , in the wafer 20 , five wafering areas 200 are provided in the upward direction in FIG. 15 and five wafering areas 200 are provided in the downward direction. In the upward wafering region 200, the cutting part 122 is provided on the upper side and the wafer part 120x is provided on the lower side in this order. In addition, in the downward wafering region 200, the cutting part 122 is provided on the lower side and the wafer part 120x is provided on the upper side in this order. With respect to such a wafer 20, in the expansion process, for example, as shown in FIG. 15(a), the dicing tape is expanded along the direction in which the dicing part 122 and the wafer part 120x are continuous as one direction (CH1). Thereafter, for example, as shown in FIG. 15(b) , the slicing tape is expanded in the direction (CH2) intersecting CH1. In this way, the expansion process can also be realized by sequentially expanding the CH1 and CH2 directions. Next, an example of setting the line 15 (the planned cutting line) for cutting the wafer 20 will be described with reference to FIGS. 16 to 18 . FIG. 16 is a diagram showing a setting example of the line 15 . The wafer 20 shown in FIG. 16 is the same as the left-right asymmetric wafer 20 shown in FIG. 11(c) described above. The line 15 is configured to include a wafer dividing line 151 that divides each wafering region 200 and an opening line 152 set so as to form a notch-shaped opening in the semiconductor wafer. The wafer part 120x and the cutting part 122 are continuously provided via the opening line 152. The opening line 152 is set to avoid contact between the wafer portion 120x and the cutting portion 122 during the expansion process. As shown in FIG. 16 , the wafer dividing line 151 has a first line 151 a, a second line 151 b, a third line 151 c, and a fourth line 151 d. The first line 151a and the second line 151b are planned cutting lines extending in the longitudinal direction in Fig. 16 in parallel with each other. One ends of both the first line 151 a and the second line 151 b extend to the outer edge of the wafer 20 . The third line 151c is a line to be cut that is continuous with the other end of the first line 151a (the end on the center side of the wafer 20) and extends in the lateral direction in FIG. 16 to a location where it intersects the second line 151b. The fourth line 151d is a planned cutting line extending in the transverse direction in Fig. 16 in parallel with the third line 151c. The fourth line 151d has a portion of the first line 152a (described below) extending from the first line 151a to the opening line 152 and a portion extending from the second line 151b to a second line 152b (described below) of the opening line 152. The fourth line 151d does not cross the cutting portion 122, but extends only to a portion that intersects the first line 152a and a portion that intersects the second line 152b. The opening line 152 is set so that the width of the opening (that is, the width of the cutting portion 122 ) becomes wider toward the opening end side. Like the wafer 20 shown in FIG. 16 , the opening line 152 of the wafer 200 in the wafer 200 that is located closer to the center side of the wafer 20 than the dicing portion 122 is directed toward the outer edge of the wafer 20 with the width of the opening. Width setting. In addition, like the wafer 20 shown in FIG. 13 , the opening line 152 of the wafering region 200 of the wafer portion 120x located closer to the outer edge side of the wafer 20 than the cutting portion 122 faces the wafer 20 with the width of the opening portion. Set in a way that the center becomes wider. As shown in FIG. 16 , the opening line 152 includes a first line 152a, a second line 152b, a third line 152c, and a fourth line 152d. The first line 152a is a planned cutting line extending in the longitudinal direction in FIG. 16 in parallel with the first line 151a. One end of the first line 152 a (a portion corresponding to the opening end of the opening) extends to the outer edge of the wafer 20 , and the other end extends to a position corresponding to the base end of the opening. The second line 152 b is a planned cutting line extending to the outer edge of the wafer 20 so as to be farther away from the first line 152 a as it approaches the outer edge of the wafer 20 . The third line 152c is a planned cutting line that is continuous with the other end of the first line 151a and extends in the transverse direction in FIG. 16 . The fourth line 152d is a planned cutting line extending to connect the third line 152c and the second line 152b. Such opening line 152 is set so that the center line CL of the opening angle of the opening is located on a line extending radially from the center of the wafer 20 (that is, the center position TC of the slicing belt). FIG. 17 is a diagram showing another setting example of the line 15 . The line 15 shown in FIG. 17 is substantially the same as the line 15 shown in FIG. 16 , but the difference is that the fourth line 151 d of the wafer dividing line 151 extends across the cutting portion 122 . In the structure shown in FIG. 17, since the 4th line 151d extends across the cutting part 122, the cutting part 122 is separated up and down. In this case, when comparing the structure shown in FIG. 16 and the structure shown in FIG. 17 , the center of gravity of the cutting portion 122 of the structure shown in FIG. 16 is farther from the center of the wafer 20 , and the separability becomes higher. In this way, from the viewpoint of the divisibility of the dicing portion 122 , it is preferable that the wafer dividing line 151 is set so as not to cross the dicing portion 122 . FIG. 18 is a diagram showing another setting example of the line 15 . The line 15 shown in FIG. 18 is substantially the same as the line 15 shown in FIG. 16 , but the difference is that the third line 151 c and the fourth line 151 d extend to the outer edge of the wafer 20 . One end of the third line 151 c extends to the third line 1151 c of the adjacent other wafering area 200 , and the other end extends to the outer edge of the wafer 20 . In addition, both ends of the fourth line 151d extend to the outer edge of the wafer 20 . In the structure shown in FIG. 18 , the number of lines to be cut is increased, and the wafer 20 is divided into finer parts. When comparing the structure shown in FIG. 16 and the structure shown in FIG. 18 , from the viewpoint of the above-mentioned center of gravity model, the structure shown in FIG. 16 is more divisible. In this way, by setting the number of planned cutting lines to the minimum required, the separability in the expansion process is improved. In addition, the structure shown in FIG. 16 also has advantages such as a small number of cuts and the ability to increase the wafer size. On the other hand, in the structure shown in FIG. 16 , the center of gravity position changes moment by moment and the moving direction changes (wafer rotation) according to the order of cutting along the planned cutting line, which may cause fragmentation during the expansion process. In this regard, for example, as in the structure shown in FIG. 18 , by increasing the number of planned cutting lines, the risk of fragmentation due to wafer rotation can be reduced. In addition, when increasing the planned cutting lines, it is preferable to increase the planned cutting lines related to the location where fragments actually occur. Next, the processing of the opening line 152 will be described in detail with reference to FIGS. 19 and 20 . FIG. 19 is a diagram explaining the processing sequence of the opening line 152. 19(b) to 19(i) illustrate the processing sequence of the opening line 152 included in one wafering region 200 of the wafer 20 shown in FIG. 19(a). In FIGS. 19(b) to 19(i) , the dotted lines represent lines that have not been laser processed, and the solid lines represent lines that have been laser processed. As shown in FIG. 19( b ), first, the wafer 20 in which the opening lines 152 (the first line 152 a , the second line 152 b , the third line 152 c , and the fourth line 152 d ) scheduled for laser processing are set is prepared. Next, as shown in FIG. 19(c) , a modified region is formed along the first line 152a. The first line 152 a extends to the outer edge of the wafer 20 . The inner side of the first line 152 a (the center side of the wafer 20 ) is a portion where the cracks related to the formation of the modified region are not to be extended (the cracks are to be stopped). Therefore, the first line 152a is irradiated with laser light from the inside toward the outside to form a modified region. In this case, the light condensing point C is, for example, from a position closer to the inside than the base end (inside end) of the first line 152a, in accordance with the base end of the first line 152a and the front end (wafer 20), the support portion 102 (refer to FIG. 1) is moved. The section inside the base end of the first line 152a is set as the laser off section 152x in which the laser is turned off (OFF). Next, as shown in FIG. 19(d) , a modified region is formed along the second line 152b. The second line 152b extends to the outer edge of the wafer 20 . The inner side of the second line 152b is a portion where cracks related to the formation of the modified region are not to be extended. Therefore, the second line 152b is irradiated with laser light from the inside toward the outside to form a modified region. In this case, the section closer to the inside than the base end (inside end) of the second line 152b is regarded as the laser off section 152x, and the focusing point C is determined according to the laser off section 152x, the second line The support part 102 (see FIG. 1 ) is moved in such a manner that the base end of the second wire 152 b and the front end of the second wire 152 b relatively move in this order. Through the processing up to this point, modified regions along the first line 152a and the second line 152b are formed (see FIG. 19(e) ). Next, as shown in FIG. 19(f) , a modified region is formed along the third line 152c. The third line 152c is irradiated with laser light toward the processed first line 152a to form a modified region. In this case, a section closer to the right side in FIG. 19(f) than the base end of the third line 152c (the end opposite to the first line 152a side) and a section closer to the right side than the distal end of the third line 152c (the first line 152a side) The section closer to the left side in FIG. 19(f) (the end of the line 152a side) is the laser off section 152x, and the focusing point C is based on the laser off section 152x, the base end of the third line 152c, the third The support part 102 (refer to FIG. 1) moves so that the front end of the line 152c and the laser cut-off section 152x move relatively in sequence. Next, as shown in FIG. 19(g) , a modified region is formed along the fourth line 152d. Regarding the fourth line 152d, laser light is irradiated toward the second line 152b, which is a processed line, to form a modified region. In this case, the section closer to the lower left side in FIG. 19(g) than the base end of the fourth line 152d (the end on the third line 152c side) and the distal end of the fourth line 152d (the second line 152b side) closer to the upper right side in Fig. 19(g) is the laser off interval 152x, and the focusing point C is based on the laser off interval 152x, the base end of the fourth line 152d, and the fourth line The support part 102 (see FIG. 1 ) is moved in such a manner that the front end of 152d and the laser off section 152x are relatively moved in sequence. Through the processing up to this point, all the modified regions along the opening line 152 are formed (see FIG. 19(h) ). Finally, as shown in FIG. 19(i) , a modified region is formed along the fourth line 151d of the wafer dividing line 151. In addition, the formation of the modified region along the fourth line 151d may be performed before the third line 152c and the fourth line 152d as the opening line 152 are formed. The modified region along the fourth line 151d is formed across the cutting portion 122. That is, the section crossing the cutting part 122 is set as the laser off section 152x, and the focusing point C is based on the section of the fourth line 151d facing the first line 152a, the section crossing the cutting part 122, and the fourth line 151d. The support portion 102 (refer to FIG. 1 ) is moved in a relatively sequential manner from the second line 152 b toward the outer section. In this case, since the first line 152a and the second line 152b have already been formed, it is assumed that the crack related to the formation of the modified region along the fourth line 151d stops at the first line 152a and the second line 152b. Through the processing up to this point, a modified region along the opening line 152 and the fourth line 151d is formed (see FIG. 19(j)). FIG. 20 is a diagram explaining laser beam irradiation in each processing location. 20(a), 20(b), 20(c) and 20(d) respectively show the laser processing of the first line 152a, the second line 152b, the third line 152c and the fourth line 152d. The upper section shows the laser processing along the line, and the lower section shows the irradiation state of the laser beam. As shown in the lower sections of Figure 20(a) and Figure 20(c) , in the case where laser processing is performed in the same direction as the crystallographic direction (110) (ie, 90 degrees or 0 degrees), or Figure 20(d ), when laser processing is performed in a direction of 45 degrees with respect to the crystallographic direction (110), by matching the processing direction with the beam shape of the elliptical laser beam, it is possible to achieve processing along the Directional laser processing. On the other hand, as shown in the lower part of Fig. 20(b), when laser processing is performed in directions other than the above-mentioned 90 degrees, 0 degrees, and 45 degrees with respect to the crystallographic direction (110), An elliptical laser beam is irradiated in the opposite direction to the crystallographic direction side. The direction opposite to the crystallographic direction side here refers to the opposite direction to the direction closest to the cleavage plane with respect to the direction in which the processing proceeds. This makes it possible to irradiate the laser beam in the desired processing direction after taking into consideration that the laser beam is bent (stretched) toward the crystallographic direction side. In addition, from the viewpoint of suppressing fragmentation, it is preferable to separate the cutting portion 122 as early as possible in the expansion process. Therefore, in order to separate the cutting part 122 reliably and as early as possible, the laser processing conditions of the opening line 152 as the planned cutting line related to the cutting part 122 may be set to be higher than that of the wafer dividing line 151 as the other planned cutting line. The laser processing conditions are easier to separate. Specifically, the number of laser scans when forming the modified region along the opening line 152 may be set to be greater than the number of laser scans when forming the modified region along the wafer dividing line 151 . FIG. 21 is a diagram explaining the processing conditions of the opening line 152 and the wafer dividing line 151. 21(a) shows the wafer 20 to be processed, FIG. 21(b) shows the opening line 152 of the wafering region 200 of the wafer 20, and FIG. 21(c) shows the processing conditions of the opening line 152 (and the conditions based on the processing). 21(d) shows the wafer zoning line 151 of the wafer zoning area 200 of the wafer 20, and FIG. 21(e) shows the processing conditions of the wafer scribing line 151 (and the processing results based on the processing conditions). As shown in FIGS. 21(c) and 21(d) , for example, in the processing of the 400 μm wafer 20 , conditions such as wavelength (1080 nm) are different between the laser processing along the opening line 152 and the laser processing along the wafer dividing line 151 . It is common in injection processing. On the other hand, as shown in FIG. 21(c) , in the laser processing along the opening line 152, the number of scans is 5 passes (SD1 to SD5 in FIG. 21(c)). In contrast, in In the laser processing along the wafer dividing line 151, the number of scans is 4 passes (SD1 to SD4). In this way, by setting the number of laser scans when forming the modified region along the opening line 152 to be greater than the number of laser scans when forming the modified region along the wafer dividing line 151 , the cutting portion 122 can be separated as early as possible. . In addition, terms such as "Z80" and "Z75" in Fig. 21(c) and Fig. 21(d) are information on the Z height which is the processing depth when laser processing is performed. Next, the effects of the wafer 20 and the processing method of this embodiment will be described. The wafer 20 of this embodiment is a wafer obtained by forming a modified region along the line 15 and then performing an expansion process to obtain a plurality of semiconductor wafers 120 , and has a plurality of wafers divided by the wafer dividing line 151 as the line 15 Region 200 , the wafering region 200 has a wafer portion 120x constituting the semiconductor wafer 120 and a portion cut from the wafer portion 120x and is a cut portion 122 that is continuous with the wafer portion 120x via an opening line 152 , which is formed in the semiconductor wafer 120 . The line 15 is set so that a notch-shaped opening 121 is formed on the wafer 120 , and the opening line 152 is set so that the width of the opening 121 becomes wider toward the opening end side or remains constant. In the wafer 20 of this embodiment, in the wafering region 200 , the wafer portion 120 x and the cutting portion 122 are formed continuously via the opening line 152 as the line 15 related to the formation of the opening portion 121 of the semiconductor wafer 120 . In the present wafer 20 , the opening line 152 is set so that the width of the opening 121 becomes wider toward the opening end side or remains constant. By setting the opening line 152 in this way, when the modified region is formed along the opening line 152 and the expansion process is performed, the gap between the wafer portion 120x (semiconductor wafer 120) and the dicing portion 122 cut from the wafer portion 120x (semiconductor wafer 120) can be suppressed. contact between. This can effectively suppress the occurrence of chips (fragments) in the semiconductor wafer 120 . In the above-mentioned wafer 20 , the opening line 152 of the wafering region 200 in the wafer 200 where the wafer portion 120 x is located closer to the center side of the wafer 20 than the dicing portion 122 may be directed toward the outer edge of the wafer 20 with the width of the opening portion 121 . The opening line 152 of the wafering region 200 located closer to the outer edge side of the wafer 20 than the cutting portion 122 of the wafer portion 120 wide or remain constant. According to such a configuration, when the wafer portion 120 Contact between portion 120x and cutting portion 122 cut from wafer portion 120x. In addition, in the expansion process, when the displacement of the portion far from the center of the wafer 20 (that is, the outer edge side of the wafer 20 ) becomes larger, the wafer portion 120 x is located closer to the wafer 20 than the cutting portion 122 In the structure on the center side, the cutting part 122 can be effectively displaced in the direction to be separated (the outer edge direction of the wafer 20 which is the direction away from the wafer part 120x), and the divisionability of the cutting part 122 can be improved. The generation of debris in the semiconductor wafer 120 is more effectively suppressed. In the above-mentioned wafer 20 , the opening line 152 of the wafering area 200 close to the outer edge of the wafer 20 may also extend to the outer edge of the wafer 20 . In this way, by extending the opening line 152 to the outer edge of the wafer 20 , the divisionability of the cutting portion 122 can be improved, and the generation of debris in the semiconductor wafer 120 can be more effectively suppressed. In the above-mentioned wafer 20 , the wafer dividing line 151 may also extend to the outer edge of the wafer 20 . In this way, by extending the wafer dividing line 151 to the outer edge of the wafer 20 , the divisibility of the wafer portion 120x can be improved. In the above-mentioned wafer 20 , the plurality of wafering regions 200 may be arranged radially from the center of the wafer 20 , and the wafer portion 120 x and the cutting portion 122 may be continuously arranged on a line extending radially from the center of the wafer 20 . settings. When a device that radially expands the wafer 20 is used as the expansion device, the plurality of wafering regions 200 are arranged radially from the center of the wafer 20, and the wafer portion 120x and the cutting portion 122 are arranged from the wafer 20. A line extending radially from the center of the circle 20 is continuously provided in order, and the wafer portions 120x and the cutting portions 122 of the plurality of wafering regions 200 are arranged along the direction of expansion. By expanding such a wafer 20 using the above-mentioned expansion device, the divisibility can be improved, and the occurrence of debris in the semiconductor wafer 120 can be effectively suppressed. In the wafer 20 described above, the opening line 152 may be set so that the center line of the opening angle of the opening 121 is located on a line that extends radially from the center of the wafer 20 . When using a device that radially expands the wafer 20 as the expansion device, by positioning the center line of the opening angle of the opening 121 on a line that radially expands from the center of the wafer 20 , it is possible to appropriately suppress The wafer part 120x and the cutting part 122 are in contact, and the wafer part 120x and the cutting part 122 can be separated. That is, generation of chips (fragments) in the semiconductor wafer 120 can be more effectively suppressed. The opening line 152 may be set so as to avoid contact between the wafer part 120x and the cutting part 122 during the expansion process. By setting the opening line 152 in this way, when the modified region is formed along the opening line 152 and the expansion process is performed, contact between the wafer portion 120x and the cutting portion 122 can be suppressed. This can effectively suppress the occurrence of chips (fragments) in the semiconductor wafer 120 . The processing method of the wafer 20 in this embodiment includes the step of preparing the wafer 20 having a plurality of wafering regions 200 divided by the wafer dividing lines 151 as the lines 15 , and the wafering regions 200 having semiconductor components. The wafer portion 120x of the wafer 120 and the portion cut from the wafer portion 120x are the cut portions 122 that are continuous with the wafer portion 120x via the opening line 152, which is an opening having a cutout shape formed in the semiconductor wafer portion 120x. The line 15 set in the pattern 121; the process of irradiating laser light along the line 15 to form a modified region; and the wafer portion 120x and the dicing portion 122 by expanding the dicing tape attached to the wafer 20 in which the modified region is formed. A process of separating the semiconductor wafers 120 at intervals. In the processing method of the wafer 20 of this embodiment, in the wafering region 200 , the wafer preparation part 120 x and the cutting part 122 are continuously connected via the opening line 152 which is the line 15 related to the formation of the opening part 121 of the semiconductor wafer 120 Formed wafer 20. Then, a modified region is formed along the line 15 of the wafer 20 , and the slicing tape attached to the wafer 20 is expanded to obtain the semiconductor wafer 120 . Here, in this processing method, in the step of obtaining the semiconductor wafer 120, the wafer part 120x and the cutting part 122 are separated with a gap. This can suppress contact between the wafer portion 120x (semiconductor wafer 120) and the cutting portion 122 cut from the wafer portion 120x (semiconductor wafer 120), and can effectively suppress the occurrence of chips (fragments) in the semiconductor wafer 120. In the above processing method, the plurality of wafering regions 200 may be arranged radially from the center of the wafer 20 , and the wafer part 120x and the cutting part 122 may be continuously provided on a line extending radially from the center of the wafer 20 In the expansion step, the slicing tape attached to the wafer 20 is expanded in a direction extending radially from the center of the wafer 20 . Thereby, the direction in which the wafer portion 120x and the cutting portion 122 are continuously provided can be aligned with the expansion direction, thereby improving the separability and effectively suppressing the generation of chips in the semiconductor wafer 120 . In the above processing method, the opening line 152 of the wafering area 200 close to the outer edge of the wafer 20 may also extend to the outer edge of the wafer 20 . In this way, by extending the opening line 152 to the outer edge of the wafer 20 , the divisionability of the cutting portion 122 can be improved, and the generation of debris in the semiconductor wafer 120 can be more effectively suppressed. In the above processing method, in the step of forming the modified region, the opening line 152 extending to the outer edge of the wafer 20 may be irradiated with laser light from the inside toward the outside of the opening line 152 to form the modified region. According to this configuration, cracks caused by the formation of the modified region can be stopped inside the opening line 152 and can be extended outside the opening line 152 due to the formation of the modified region. Accordingly, cracks can be appropriately stopped at the portion where cracks are to be stopped (inside the opening line 152 of the semiconductor wafer 120 ). In the above-mentioned processing method, in the step of forming the modified region, an elliptical laser beam may be irradiated in a direction opposite to the crystallographic direction side with respect to the direction in which the processing proceeds. When the laser beam is bent toward the crystallographic direction (stretched toward the crystallographic direction), it is considered that the elliptical laser beam is irradiated in the direction opposite to the crystallographic direction with respect to the processing direction. The above-mentioned side bending of the crystal direction enables the laser beam to be irradiated in the desired processing direction. That is, according to such a configuration, the modified region along the line 15 can be formed. In the above processing method, in the step of forming the modified region, the scanning number of the laser light when forming the modified region along the opening line 152 may be set to be higher than the scanning number of the laser light when forming the modified region along the wafer dividing line 151 . Many. According to this configuration, the number of scans of the laser light used to cut the dicing portion 122 is greater than the number of scans of the laser light used to cut the wafer portion 120x from the wafer 20 . When the wafer 20 is expanded, the dicing portion 122 can be Separate as soon as possible. By separating the dicing part 122 as early as possible, the center of gravity of the wafer 20 can be determined as early as possible, and it is possible to avoid the situation where the dicing part 122 and the wafer part 120x are easily in contact with each other due to repeated center of gravity movement, thereby causing fragments in the semiconductor wafer 120 . In the above processing method, the wafer dividing line 151 may also extend to the outer edge of the wafer 20 . In this way, by extending the wafer dividing line 151 to the outer edge of the wafer 20 , the divisibility of the wafer portion 120x can be improved. The processing method includes: preparing the wafer 20; forming a modified region along the line 15; and obtaining a plurality of semiconductor wafers 120 by expanding a slicing tape attached to the wafer 20 in which the modified region is formed. process. According to such a processing method of the wafer 20, it is possible to suppress the contact between the wafer portion 120x (semiconductor wafer 120) and the cutting portion 122 cut from the wafer portion 120x (semiconductor wafer 120), and to effectively suppress the occurrence of debris in the semiconductor wafer 120 ( scrap).

15:線(切斷預定線) 20:晶圓 100:雷射加工裝置 120:半導體晶片 120x:晶片部 121:開口部 122:切割部 151:晶片劃分線 152:開口線 200:晶片化區域 15: Line (cut the scheduled line) 20:wafer 100:Laser processing device 120:Semiconductor wafer 120x:Chip department 121:Opening part 122: Cutting Department 151: Wafer dividing line 152:Opening line 200:wafering area

[圖1]是在晶圓的內部形成改質區域的雷射加工裝置的構成圖。 [圖2]是作為加工對象的晶圓的俯視圖。 [圖3]是圖2所示的晶圓的一部分的截面圖。 [圖4]是示出晶圓的加工方法的流程圖。 [圖5]是說明形成有開口部的半導體晶片的使用例的圖。 [圖6]是說明形成有開口部的半導體晶片的使用例的圖。 [圖7]是說明碎片的產生的圖。 [圖8]是說明擴展工序中的晶圓的各部位的位移量的圖。 [圖9]是說明碎片的產生的圖。 [圖10]是示出抑制碎片的晶片化區域的配置例的圖。 [圖11]是示出抑制碎片的晶片化區域的配置例的圖。 [圖12]是說明晶片化區域的各種配置例的圖。 [圖13]是示出抑制碎片的晶片化區域的配置例的圖。 [圖14]是說明擴展工序的一個例子的圖。 [圖15]是說明擴展工序的其他例子的圖。 [圖16]是示出線的設定例的圖。 [圖17]是示出線的設定例的圖。 [圖18]是示出線的設定例的圖。 [圖19]是說明開口線的加工順序的圖。 [圖20]是說明各加工部位中的雷射光束照射的圖。 [圖21]是說明開口線和晶片劃分線的加工條件的圖。 [Fig. 1] is a structural diagram of a laser processing apparatus that forms a modified region inside a wafer. [Fig. 2] is a top view of a wafer to be processed. [Fig. 3] is a cross-sectional view of a part of the wafer shown in Fig. 2. [Fig. 4] is a flowchart showing a wafer processing method. [Fig. 5] A diagram illustrating an example of use of a semiconductor wafer in which openings are formed. [Fig. 6] Fig. 6 is a diagram illustrating an example of use of a semiconductor wafer in which openings are formed. [Fig. 7] is a diagram explaining the generation of debris. [Fig. 8] Fig. 8 is a diagram explaining the displacement amount of each part of the wafer in the expansion process. [Fig. 9] is a diagram explaining the generation of debris. [Fig. 10] Fig. 10 is a diagram showing an arrangement example of a wafering region that suppresses debris. [Fig. 11] Fig. 11 is a diagram showing an arrangement example of a wafering region that suppresses debris. [Fig. 12] Fig. 12 is a diagram illustrating various arrangement examples of wafering regions. [Fig. 13] Fig. 13 is a diagram showing an arrangement example of a wafering region that suppresses debris. [Fig. 14] is a diagram explaining an example of the expansion process. [Fig. 15] is a diagram explaining another example of the expansion process. [Fig. 16] A diagram showing an example of setting lines. [Fig. 17] A diagram showing an example of setting lines. [Fig. 18] Fig. 18 is a diagram showing an example of setting lines. [Fig. 19] is a diagram explaining the processing sequence of the opening line. [Fig. 20] is a diagram explaining laser beam irradiation in each processing location. [Fig. 21] A diagram illustrating processing conditions for opening lines and wafer dividing lines.

11:改質區域 11: Modified area

11s:改質點 11s: Modification point

15:線(切斷預定線) 15: Line (cut the scheduled line)

20:晶圓 20:wafer

100:雷射加工裝置 100:Laser processing device

102:支撐部 102: Support part

103:光源 103:Light source

104:光軸調整部 104: Optical axis adjustment part

105:空間光調變器 105: Spatial light modulator

106:聚光部 106: Condensing Department

107:光軸監測部 107: Optical axis monitoring department

108A:可見光攝像部 108A:Visible light camera department

108B:紅外攝像部 108B: Infrared camera department

109:移動機構 109:Mobile mechanism

161:聚光透鏡單元 161: condenser lens unit

162:驅動機構 162:Driving mechanism

250:管理單元 250: Management unit

251:控制部 251:Control Department

252:使用者介面 252:User interface

253:記憶部 253:Memory Department

C:聚光點 C: focus point

H:雷射加工頭 H: Laser processing head

L0:雷射光 L0: Laser light

MM1:鏡 MM1: Mirror

MM2:分色鏡 MM2: Dichroic mirror

S1,S2:測距感測器 S1, S2: ranging sensor

V0:可見光 V0: visible light

Claims (15)

一種晶圓，其特徵在於， 是在沿切斷預定線形成了改質區域後藉由實施擴展工序而得到多個半導體晶片的晶圓， 該晶圓具有由作為前述切斷預定線的晶片劃分線劃分的多個晶片化區域， 前述晶片化區域具有： 晶片部，其構成前述半導體晶片；以及 切割部，其是從前述晶片部被切割的部分，並且是經由作為前述切斷預定線的開口線而與前述晶片部連續的切割部，前述開口線被設定為在前述半導體晶片形成切口形狀的開口部， 前述開口線被設定為使得前述開口部的寬度朝向開口端側變寬或保持恆定。 A wafer characterized by: It is a wafer in which a plurality of semiconductor wafers are obtained by performing an expansion process after forming a modified region along a planned cutting line. The wafer has a plurality of wafering areas divided by wafer dividing lines as the aforementioned planned cutting lines, The aforementioned wafering area has: a wafer portion, which constitutes the aforementioned semiconductor wafer; and A cutting portion is a portion cut from the wafer portion and is continuous with the wafer portion via an opening line as the planned cutting line, the opening line being set to form a cut shape in the semiconductor wafer opening, The opening line is set so that the width of the opening portion becomes wider toward the opening end side or remains constant. 根據請求項1所述的晶圓，其中， 前述晶片部比前述切割部更靠近前述晶圓的中心側的前述晶片化區域的前述開口線，係被設定為使得前述開口部的寬度朝向前述晶圓的外緣變寬或保持恆定， 前述晶片部比前述切割部更靠近前述晶圓的外緣側的前述晶片化區域的前述開口線，係被設定為使得前述開口部的寬度朝向前述晶圓的中心變寬或保持恆定。 The wafer according to claim 1, wherein, The opening line of the wafering area of the wafer portion closer to the center side of the wafer than the dicing portion is set so that the width of the opening portion becomes wider toward the outer edge of the wafer or remains constant, The opening line of the wafering region in the wafering area closer to the outer edge side of the wafer than the dicing part is set so that the width of the opening becomes wider toward the center of the wafer or remains constant. 根據請求項1或2所述的晶圓，其中， 接近前述晶圓的外緣的前述晶片化區域的前述開口線係延伸至前述晶圓的外緣。 The wafer according to claim 1 or 2, wherein, The opening line of the wafered area close to the outer edge of the wafer extends to the outer edge of the wafer. 根據請求項1或2所述的晶圓，其中， 前述晶片劃分線係延伸至前述晶圓的外緣。 The wafer according to claim 1 or 2, wherein, The wafer dividing line extends to the outer edge of the wafer. 根據請求項1或2所述的晶圓，其中， 前述多個晶片化區域係從前述晶圓的中心呈放射狀配置， 前述晶片部和前述切割部係依次連續地設置在從前述晶圓的中心呈放射狀擴展的線上。 The wafer according to claim 1 or 2, wherein, The plurality of wafered areas are arranged radially from the center of the wafer, The wafer portion and the cutting portion are sequentially and continuously provided on a line extending radially from the center of the wafer. 根據請求項1或2所述的晶圓，其中， 前述開口線，係被設定為使得前述開口部的開口角的中心線位於從前述晶圓的中心呈放射狀擴展的線上。 The wafer according to claim 1 or 2, wherein, The opening line is set so that the center line of the opening angle of the opening portion is located on a line extending radially from the center of the wafer. 一種晶圓，其特徵在於， 是在沿切斷預定線形成了改質區域後藉由實施擴展工序而得到多個半導體晶片的晶圓， 該晶圓具有由作為前述切斷預定線的晶片劃分線劃分的多個晶片化區域， 前述晶片化區域具有： 晶片部，其構成前述半導體晶片；以及 切割部，其是從前述晶片部切割的部分，並且是經由作為前述切斷預定線的開口線而與前述晶片部連續的切割部，前述開口線被設定為在前述半導體晶片形成切口形狀的開口部， 前述開口線被設定為在擴展工序中避免前述晶片部與前述切割部之間的接觸。 A wafer characterized by: It is a wafer in which a plurality of semiconductor wafers are obtained by performing an expansion process after forming a modified region along a planned cutting line. The wafer has a plurality of wafering areas divided by wafer dividing lines as the aforementioned planned cutting lines, The aforementioned wafering area has: a wafer portion, which constitutes the aforementioned semiconductor wafer; and A dicing portion is a portion cut from the wafer portion and is continuous with the wafer portion via an opening line as the planned cutting line, the opening line being set to form an opening in the shape of a slit in the semiconductor wafer department, The opening line is set to avoid contact between the wafer portion and the cutting portion during the expansion process. 一種晶圓的加工方法，其特徵在於， 包括： 準備晶圓的工序，前述晶圓具有由作為切斷預定線的晶片劃分線劃分的多個晶片化區域，前述晶片化區域具有：晶片部，其構成半導體晶片；以及切割部，其是從前述晶片部切割的部分，並且是經由作為前述切斷預定線的開口線而與前述晶片部連續的切割部，前述開口線被設定為在半導體晶片形成切口形狀的開口部； 沿前述切斷預定線照射雷射光而形成改質區域的工序；以及 藉由擴張貼附於形成了前述改質區域的前述晶圓的帶，將前述晶片部與前述切割部隔開間隔而分離，得到前述半導體晶片的工序。 A wafer processing method, characterized by: include: A step of preparing a wafer having a plurality of wafering areas divided by wafer dividing lines serving as planned cutting lines, the wafering area having: a wafer portion constituting a semiconductor wafer; and a dicing portion formed from the aforementioned The cut portion of the wafer portion is a cutting portion that is continuous with the wafer portion via an opening line as the planned cutting line, the opening line being set as an opening portion forming a cut shape in the semiconductor wafer; The step of irradiating laser light along the planned cutting line to form a modified region; and A step of obtaining the semiconductor wafer by expanding a tape attached to the wafer in which the modified region is formed, and separating the wafer portion and the dicing portion at a distance. 根據請求項8所述的加工方法，其中， 前述多個晶片化區域係從前述晶圓的中心呈放射狀配置， 前述晶片部和前述切割部係依次連續地設置在從前述晶圓的中心呈放射狀擴展的線上， 在前述擴展工序中，係在從前述晶圓的中心放射狀地延伸的方向上擴張貼附於前述晶圓上的帶。 The processing method according to claim 8, wherein, The plurality of wafered areas are arranged radially from the center of the wafer, The wafer portion and the cutting portion are successively provided on a line extending radially from the center of the wafer, In the expansion step, the tape attached to the wafer is expanded in a direction extending radially from the center of the wafer. 根據請求項8或9所述的加工方法，其中， 接近前述晶圓的外緣的前述晶片化區域的前述開口線，係延伸至前述晶圓的外緣。 The processing method according to claim 8 or 9, wherein, The opening line of the wafered area close to the outer edge of the wafer extends to the outer edge of the wafer. 根據請求項10所述的加工方法，其中， 在形成前述改質區域的工序中，對於延伸至前述晶圓的外緣的前述開口線，係從該開口線的內側朝向外側照射雷射光而形成前述改質區域。 The processing method according to claim 10, wherein, In the step of forming the modified region, the opening line extending to the outer edge of the wafer is irradiated with laser light from the inside toward the outside of the opening line to form the modified region. 根據請求項8或9所述的加工方法，其中， 在形成前述改質區域的工序中，相對於前述開口線的行進方向，向與結晶方向側相反的方向照射橢圓形的雷射光束。 The processing method according to claim 8 or 9, wherein, In the step of forming the modified region, an elliptical laser beam is irradiated in a direction opposite to the crystal direction side with respect to the traveling direction of the opening line. 根據請求項8或9所述的加工方法，其中， 在形成前述改質區域的工序中，沿前述開口線形成改質區域時的雷射光的掃描數設定為比沿前述晶片劃分線形成改質區域時的雷射光的掃描數更多。 The processing method according to claim 8 or 9, wherein, In the step of forming the modified region, the number of scans of laser light when forming the modified region along the opening line is set to be greater than the number of scans of laser light when forming the modified region along the wafer dividing line. 根據請求項8或9所述的加工方法，其中， 前述晶片劃分線延伸至前述晶圓的外緣。 The processing method according to claim 8 or 9, wherein, The wafer dividing line extends to the outer edge of the wafer. 一種晶圓的加工方法，其特徵在於， 包括： 準備請求項1或2所述的晶圓的工序； 沿前述切斷預定線形成改質區域的工序；以及 藉由擴張貼附於形成了前述改質區域的前述晶圓上的帶，得到前述多個半導體晶片的工序。 A wafer processing method, characterized by: include: The process of preparing the wafer described in claim 1 or 2; The process of forming a modified region along the aforementioned planned cutting line; and A step of obtaining the plurality of semiconductor wafers by expanding a tape attached to the wafer in which the modified region is formed.
TW112117113A 2022-05-26 2023-05-09 Wafer and wafer processing method in which a plurality of semiconductor chips is obtained by performing an expansion process after forming a modified region along the line TW202347470A (en)

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