JPH01266623A - Coincidence detecting circuit - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a CAM array and to make the hardware small by changing the number of words of first and second areas to be compared. CONSTITUTION:When a selection of a control line 17 is instructed from a control line 7, a selecting circuit 13 makes the control line 17 active, and collation use data D1 of three words and illumination use data D2 of one word are written in CAM registers 111-113 and a CAM register 114, respectively. When counter data C1 and C2 are set, the counter data C1 is compared the data of the CAM registers 111-113 at every corresponding word, and when they coincide, a coincidence signal is outputted to a coincidence signal output line 5 through output lines 21-23, respectively. The counter data C2 is compared with the data D2 of the CAM register 114, and when they coincide, a coincidence signal is outputted to a coincidence signal line 6 through an output line 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a first,
Holds the second verification data, inputs the first and second signals consisting of one word or multiple words, and inputs the first and second signals, respectively.
, and a match detection circuit that compares the data with second verification data and outputs first and second match signals when they match.

[Conventional technology]

FIG. 4 is a configuration diagram showing a conventional example of this type of coincidence detection circuit,
5 and 6 show the content address memory array 5 of FIG.
1.52 (hereinafter referred to as CAM array 51.52) is a configuration diagram showing the inside of the CAM array 51.52.

Content address memory (hereinafter referred to as CAM) is a memory that has a data comparison function, and its operation is described in MO3 integrated circuit published by Kindai Kagakusha (P402-403). CA in case
It is used as M array 51°52.

The CAM arrays 51 and 52 hold verification data D I + D 2 input via the internal bus 53,
They are compared with the respective input signals CI*C2, and if they match, a matching signal is outputted to the respective output lines 54 and 55.

CAM arrays 51, 52 each include a buffer circuit 60 and CAM registers 61, 62 . , 6n. C
AM registers 61, 62 . ~.

6n each has CAM cells 1.72 to 7k to hold one word or one bit of data. The CAM arrays 51 and 52 input the collation data D, D2 via the buffer circuit 60, and input them into the CAM register 6 in word units.
1,62. ~.

6n. And CAM register 61°62,
~, 6n are input signals CI +
02 in word units, and if they match, a match signal is output.

(Problems to be Solved by the Invention) The above-described conventional coincidence detection circuit has independent and fixed CAM arrays 51 and 52 that compare the input signals C, , C, with the matching data D, , D, respectively. , and each is provided with a write buffer, so when comparing data with a small number of words, the CAM array 51
, 52 is inefficient, and the read/write buffer occupies a large area of hardware, making it uneconomical.

[Means to solve the problem]

The coincidence detection circuit of the present invention includes a content address memory array having a plurality of content address memory registers each including a plurality of content address memories so as to hold first and second collation data in units of words; The content address memory array is set in the first and second areas in units of words so that the data for the second comparison can be held respectively.
The first and second areas are made independent by a division instruction, and the first and second areas respectively held by the independent areas are stored with the first and second matching data. The first and second input signals respectively inputted by the regions are the first and second input signals.
and a control circuit that makes the comparison with the second area and outputs a matching signal when they match.

(Operation) Since the content address memory array is substantially one array, writing of the first and second verification data can be performed using one glue-write buffer.
By changing the number of words in the second area, the content address memory array can be used without waste.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the coincidence detection circuit of the present invention, and FIG. 2 is a configuration diagram showing a specific example of the CAM array 1 of the embodiment of FIG.

The CAM array 1 is divided into first and second regions t, . ．． 12 each contains verification data D.
I, D2 are written via the internal bus 4. counter 2
．． 3 are set with counter data C, C2 to be compared with the verification data DI and D2, respectively. 1st, 2nd
Area 1. ．． Data written in 12 DI + D
2 match the counter data C, ,D2, respectively,
The match signals are output to match signal output lines 5 and 6, respectively.

Next, the details of the CAM array 1 will be explained with reference to FIG.

In this specific example, a match of 4 words can be detected using 1 word of 3 bits. When the selection of the control line 17 is instructed from the control line 7, the selection circuit 13 activates the control line 17. When the control line 17 becomes active, the switch elements 171, 172, 173 are turned off, the CAM registers 111, 112, 113 become the first region 11, and the CAM register 114 becomes the second region 1°. CAM register 11 . via internal bus 4 and read/write buffer 12 . ．． Three words of verification data D are written to 112 and 11 degrees, and 1 is written to the CAM register 114.
Word verification data D2 is written. When 3 words of counter data C1 and 1 word of counter data C2 are set, the counter data CI is stored in the CAM register 11 . ．． 112 and 113, and if they match, a match signal is sent to the output lines 21 .
22 and 23 to the coincidence signal output line 5. Counter data C2 is the CAM register 11. data D2, and when they match, a match signal is outputted to the match signal output line 6 via the output line 24.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

The coincidence detection circuit of this embodiment is used as a chip select signal generation circuit.

The CAM array 30 divides the first and second areas 30 . ．． 30. The first is divided into
Second area 30. ．． 302 each contains verification data A.
D, , AD2 are written via data bus 34. The upper side AC and lower side AC of the address AC of the address bus 31 are the upper side bus 32 and the lower side bus 33, respectively.
is applied to the CAM array 30 via the CAM array 30. The verification data AD, , AD2 are the lower side AC, AD2 of the address AC, respectively.
, and upper side AC2, and if they match, a match signal is output to match signal output lines 35 and 36, respectively. The control circuit 38 logically ORs the match signal on the match signal output line 35 and a portion of the match signal on the match signal output line 36, and outputs an I10 select signal SEL. Of the match signals on the match signal output line 36, those other than those output to the control circuit 38 are output as they are as a highly versatile memory chip select signal C3L that specifies the upper address of the memory.

In this embodiment, the chip select logic can be easily realized, and the address signals AC,.

Comparison with AC2 It is possible to easily change the number of detection signals, so the ratio of memory select and I10 select can be freely changed, so depending on the application system, if the system has a lot of memory, increase the memory select, and if the Ilo is It can support as many I10 selects as possible, and can flexibly support various applications in chip select logic.

(Effects of the Invention) As explained above, the present invention has a content address memory array having a content address memory register for a plurality of words, and adjusts the content address memory array according to the number of words of the first and second input signals to be compared. By dividing the data into first and second regions, comparing the first and second verification data set in the first and second regions with the first and second input signals, and detecting a match. , the total number of words of the first and second input signals can be brought closer to the number of words of the content address memory array, which has the effect of reducing the unused portion of the content address memory array. ,
Since the second verification data can be set using one read/write buffer, there is an effect that the hardware can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the coincidence detection circuit of the present invention, FIG. 2 is a block diagram showing a specific example of the CAM array 1 of FIG. 1, and FIG. FIG. 4 is a configuration diagram showing a conventional example of this type of coincidence detection circuit, and FIGS. , 52). 1.30--------------- CA M
Array, 1, , 30. -----------Part 1 area, 12, 302----Second area, 2,
3------------------Counter, 4.
34-・・・・・・・・・・・・・・・・・・ Internal bus, 5.6. :15. :1B ------------ Match signal output line, 7, 37 ------------
---One control line, 111, 112, 113,
114-・””CAM register +2・・・・・・・・・
. . . Read/Write buffer, 13------------- One selection circuit, 14, +5.18, 17. 18.--Control line, +4. , 142-,183...Switch element, 21.22, 23.24--One output line, 31-- −・−
Address bus, 32----------1...
−・−Upper side bus, 33−−−−−−−−−−−−−−
-----...Lower side bus, 34---------------
−−−−−−−−Data bus, 38・・・・・・・・・
・・・・・・・・・−・・Control circuit.

Claims (1)

[Claims] First and second collation data consisting of one word or a plurality of words are held, first and second input signals consisting of one word or a plurality of words are input, and the first ,
A match detection circuit that compares the data with the second matching data and outputs the first and second matching signals when they match, and includes a plurality of match detection circuits that can hold the first and second matching data in word units. a content address memory array having a plurality of content address memory registers each consisting of a content address memory of and set the first and second areas to the set first and second areas.
The first and second areas are made independent by a division instruction, and the first and second areas are stored with the first and second matching data held respectively by the independent first and second areas. , a coincidence detection circuit having a control circuit that causes the first and second areas to compare the first and second input signals respectively inputted to the first and second areas, and outputs a coincidence signal when they match. .