KR19980035680A - Address converter circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Address converter circuit of the microprocessor.

2. The technical problem to be solved by the invention

In a microprocessor, the comparison address is translated into a physical address in a short time, enabling cache access in one CPU cycle.

3. Summary of Solution to Invention

An address converter circuit of a microprocessor, comprising: a tag way block composed of four cam cell arrays and a tag block composed of four entry comparison blocks as a comparison address storage structure, a decoder block for decoding the lower 3 bits of the comparison address, and a physical address ( Data address) storage structure comprising an SRAM cell array block consisting of four 8 * 20 SRAM cell arrays and a data block consisting of a precharge mux block for outputting a 20 bit physical address.

4. Important uses of the invention

In the present invention, a microprocessor supporting a paging address mode of memory management is used as a circuit that converts a comparative address into a physical address in a short time, thereby enabling cache access in one CPU cycle. .

Description

Address converter circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address converter circuit of a microprocessor. In particular, in a microprocessor which supports a paging address mode during memory management, a linear address is converted into a physical address. The address converter circuit for converting.

1 is a diagram of a 4 way set associative 32 entry translator circuit implemented in the prior art. Referring to the drawings, a conventional 4-way set federated 32 entry converter is composed of a tag way block 120 of four SRAM cell array blocks and four sense amplifiers and a comparison block 130 of a comparison address 101 storage structure. SRAM consisting of four 8 * 20 SRAM cell arrays as a tag block 180, a decoder block 140 for decoding the lower 3 bits 103 of the comparison address 101, and a physical address (data address) storage structure. And a data block 190 including a cell array block 110 and a precharge mux block 150 for outputting a 20-bit physical address. The tag block 180 is composed of a tag way block 120 that is four SRAM cell array blocks that store the most significant 17 bits 102 of the comparison address 101. Each way is divided into four blocks of eight entries (words) and includes four sense amplifier comparison blocks 130. The data block 190 includes an SRAM cell array block 110 and a data mux block 150 that store a 20-bit physical address.

The lower 3 bits 103 of the comparison address are used to enable read and write signals in the decoder block 140 to select one of the eight entries in the tag way block 120. 141, Tag_word [7: 0] (146, 147, 148, 149) and Data_word [7: 0] 144 are created and transmitted to the tag block 180 and the data block 190. Each tag way block 120 of the tag block 180 is a corresponding entry (word) by an enable signal of one of Tag_word [7: 0] (146, 147, 148, 149) transmitted from the decoder block 140. 17 bits of data are passed to the sense amplifier and comparison block 130, and the 17 bits of the sense amplifier and the comparison block 130 of each block are compared with the most significant 17 bits 102 of the comparison address. If all bits are the same, the Way_Hit [4: 1] 139 signal is generated and transmitted to the data block 190.

The Way_Hit [4: 1] (139) signal transmitted from the tag block 180 is transmitted to the Data_Mux Block 150 and the Data_Word [7: 0] (144) transmitted from the decoder block 140. Used to select 20-bit physical address from 80-bit data read by).

This structure reads the tag block 180 by Tag_Word [7: 0] (146, 147, 148, 149) as a result of the 3-bit decoder 140 and compares the result with the most significant 17 bits of the comparison address to Way_Hit. [4: 1] 139, which is used as a selection signal of the data mux block 150, is a reason why the access time of the converter is not fast. In addition, since each tag way block 120 has a sense amplifier and a comparison block 130, the total area of the converter is increased, and power consumption is disadvantageous.

The technical problem of the present invention is that in a microprocessor supporting a paging address mode of memory management, a comparative address is converted into a physical address in a short time, thereby enabling cache access in one CPU cycle. By providing a circuit that serves to improve the performance of the microprocessor.

1 is a diagram of a conventional four way set federated 32 entry converter circuit.

2 is a diagram of a four way set federated 32 entry converter circuit in accordance with the present invention;

3 is a diagram of an entry comparison block circuit according to the present invention;

4 is a diagram of a precharge mux circuit according to the present invention.

5 is a diagram of a two port access address translator circuit in accordance with the present invention;

6 illustrates a two port access cam cell circuit in accordance with the present invention.

7 illustrates a two port access SRAM cell circuit in accordance with the present invention.

The present invention for achieving the above object,

An address converter circuit of a microprocessor, comprising: a tag block comprising a tag way block, which is an 8 * 17 bit CAM (Contents Addressable Memory) cell array, and a four entry comparison block; A decoder block for decoding the lower three bits of the comparison address; And a precharge mux block configured to output a physical address by selecting one of four data blocks using a signal from each entry comparison block and an SRAM cell array block including four 8 * 20 bit SRAM cell arrays. It is to provide a four-way set federated address translator circuit comprising a data block.

The 4-way set federated address translator implements a tag way block, which is a comparison address storage structure, as a cam cell array, and an 8 * 20-bit SRAM cell, which is a physical address (data address) storage structure. An address translator circuit is provided that implements an array.

In the address translator, a decoder is used to decode using one decoder and use the result in a tag block and a data block in common.

In the address translator, Tag_Word [7: 0], which is a signal for selecting an entry in a way, is applied to Tag_Entry_Hit [7: 0], which is a result of comparing a tag block and a comparison address, to simultaneously perform decoding and tag access. Use

The address translator includes an entry comparison block circuit for logic ANDing Tag_Entry_Hit [7: 0] as a tag comparison result and Tag_Word [7: 0] as a decoding result, and logic Way to generate the Way_Hit [4: 1]. do.

The address converter includes a precharge mux block circuit for selecting a 20-bit data address (physical address) from the 80-bit read data of the SRAM cell array block as Way_Hit [4: 1] signal information that is an output of the entry comparison block. do.

A multi-port access four way set federated address translator circuit,

A tag block consisting of four 8 * 17 bit cam cell arrays and a tag block consisting of eight entry comparison blocks; A decoder block for decoding the lower 3 bits of the X_ comparison address and the Y_ comparison address; The SRAM cell array block, which consists of four 8 * 20-bit SRAM cell arrays, and the signal from each entry comparison block are used to select one of the four data blocks to select the X_port physical address and the Y_port physical address. And a data block consisting of two precharge mux blocks to be output.

Provides an address converter circuit for implementing the tag block, the comparison address storage structure, into a multi-port access cam cell array, and implementing the SRAM cell array block, the physical address (data address) storage structure, into a multi-port access SRAM cell array. do.

In the multi-port access 4-way cell federated address translator, a decoder is used for each port to decode and use the result in the tag block and the data block in common.

In the multi-port access four-way cell federated address translator, Tag_Word [7: 0], which selects an entry in a way, is applied to Tag_Entry_Hit [7: 0], which is a comparison address comparison result of a tag block, for decoding and tag access. Use a parallel process.

In the multi-port access four-way cell federated address translator, a logic AND of Tag_Entry_Hit [7: 0], which is a tag comparison result, and Tag_Word [7: 0], which is a decoding result, are logically divided into Way_Hit [4: 1. Use an entry comparison block to construct].

In the multi-port access 4-way cell federated address translator, a 20-bit data address (physical address) is selected from 80-bit read data of an SRAM cell array block as Way_Hit [4: 1] signal information that is an output of an entry comparison block. Use precharge mux blocks.

Accordingly, according to the present invention, in a microprocessor supporting a paging address mode of memory management, by converting a comparison address into a physical address in a short time, enabling cache access in one CPU cycle It can improve the performance of the microprocessor.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a diagram of a four way set federated 32 entry converter circuit in accordance with the present invention. Referring to the drawings, a four-way set federated 32 entry converter circuit comprises a tag consisting of four tag way blocks 220, which are an 8 * 17 bit CAM (Contents Addressable Memory) cell array, and four entry comparison blocks 260. Block 280; A decoder block 140 for decoding the lower three bits 203 of the comparison address 201; SRAM cell array block 210 consisting of four 8 * 20-bit SRAM cell arrays and one of four SRAM cell array blocks 210 are selected using signals from each entry comparison block 260. And a data block 290 consisting of a precharge mux block 270 that outputs a 20 bit physical address 275.

The tag block 280 uses a tag way block 220, which is an 8 * 17 bit cam cell array that stores the most significant 17 bits 202 of the comparison address 201, and four entry_comparison blocks 260, respectively. Implemented. The decoder block 240 is a decoder that decodes the lower 3 bits 203 of the comparison address 201 because 3 bits decoding is required to implement 4 way, 32 entries. Tag_Word [7: 0] (246), Data_Word [7: 0] 244 is created and transmitted to the entry_comparison block 260 of the tag block 280 and the SRAM cell array block 210 of the data block 290.

In each tag way block 220 of the tag block 280, the comparison address most significant 17 bits 202 while creating the Tag_Word [7: 0] 246 and the Data_Word [7: 0] 244 in the decoder block 240. ) Is compared with the cam cell contents of all entries, and each Tag_Entry_Hit [7: 0] 221 is created and transmitted to the entry_comparison block 260. Each entry_comparison block 260 of the tag block 280 is a Tag_Word [7: 0] 246 coming from the decoder block 240 and a Tag_Entry_Hit [7: 0] 221 coming from the corresponding tag way block 220. The signal is logically ANDed and the result is logically ORed to generate a Way_Hit [4: 1] (269) signal, which is commonly transmitted to 20 precharge mux blocks 270.

While creating Way_Hit [4: 1] 269 using the comparison address 201 in the tag block 280, each SRAM cell array block 210 of the data block 290 is assigned a Data_Word [ 7: 0] (244) is read, and the corresponding word data is read and 20 bits are sent to each of 20 precharge mux blocks 270. Each precharge mux block 270 uses 4-way data from the entry comparison block 260 of the tag block 280 to select 4-bit data from the SRAM cell array block 210 using the Way_Hit [4: 1] (269) selection signal. One bit is selected, and the output 20 bits of the 20 precharge mux blocks 270 become the physical address 275 which is the output of the address translator.

3 is a diagram of an entry comparison block circuit according to the present invention. Referring to the drawings, the entry comparison block circuit includes predetermined NMOS transistors 309, 370, 371, 372, 373, 374, 375, 376, 377, 380, 381, 382, 383, 384, 385, 386, 387. And inverters 353 and 354. The NMOS transistors of the entry-comparison block circuit are Tag_Word [7: 0] (346 in FIG. 3) coming from the decoder block (240 in FIG. 2) of FIG. 2 and Tag_Entry_Hit coming from the corresponding tag way block (220 in FIG. 2). Logically AND the [7: 0] (321 in FIG. 3) signal and perform a logical OR on the result to produce a Way_Hit [4: 1] (361) signal, and the precharge mux in FIG. Common to block 270 of FIG. 2.

4 is a diagram of a precharge mux circuit according to the present invention. Referring to the drawings, the precharge mux circuit is composed of predetermined NMOS transistors 409, 471, 472, 473, 474, 481, 482, 483, 484, inverters 453, 454, and the like. The precharge mux circuit uses the Way_Hit [4: 1] 469 select signal from the entry comparison block (260 of FIG. 2) of the tag block (280 of FIG. 2) to select the SRAM cell array block (FIG. 2). Selects one bit of the four-bit data Read_Data [4: 1] 468 from 210, and the output 20 bits of the precharge mux block 270 of FIG. This is the output physical address (275 in FIG. 2).

When writing data to the address translator according to the present invention, a way_select [1: 0] signal (242 in FIG. 2) having a comparison address, a corresponding physical address, and write way selection information is required. The selection [1: 0] signal (242 in FIG. 2) is delivered from the LRU block of the Address Translator Control Block. In the present invention, the lower three bits of the comparison address (203 in FIG. 2) are decoded to decode Tag_Word [7: 0] (246 in FIG. 2) and Data_Word [7: 0] (244 in FIG. 2) into a decoder block (240 in FIG. 2). ), And the way_select [1: 0] signal (242 in FIG. 2) is also decoded in the decoder block (240 in FIG. 2) to create Write_Way [4: 1]. In the tag block, Tag_Word [7: 0] and Write_Way [4: 1] is used to write the comparison address 17 bits to one of the corresponding 32 entries, and in the data block, data_Word [7: 0] and Write_Way [4: 1] are used to physically write to one of the 32 entries. Write address 20 bits.

The Multi_Port Access Address Translator may be implemented using the address translator implemented in the present invention, and FIG. 5 is a diagram of a two-port access address translator circuit according to the present invention.

Referring to the drawings, a tag block 580 consisting of four tag way blocks 520, which are an 8 * 17 bit cam cell array, and eight entry comparison blocks 561, 562; A decoder block 540 for decoding the lower 3 bits 505 and 506 of the X_comparison address 501 and the Y_comparison address 502; An SRAM cell array block 510 composed of four 8 * 20-bit SRAM cell arrays and a signal from each entry comparison block 561, 562 are used to select one of the four SRAM cell array blocks 510. And a data block 590 consisting of two precharge mux blocks 571 and 572 that selectively select to output an X_port physical address 577 and a Y_port physical address 578.

The two-port address translator requires two data physical addresses from a Pentium or higher microprocessor, and is an address translator that satisfies this requirement.

6 is a diagram of a two-port cam cell circuit in accordance with the present invention. 7 is a diagram of a two port SRAM cell circuit according to the present invention. Referring to the drawings, the tag block 580 of FIG. 5 includes four 8 * 17 bit cam cell array blocks using a cam cell shown in FIG. 6, a tag way block 520, and eight entry comparison blocks 561 and 562. It is composed of

The data block 590 includes four 8 * 20 bit SRAM cell array blocks 510 and two precharge mux blocks 571 and 572 using the SRAM cells shown in FIG. 7.

The decoder block 540 decodes the lower three bits 505 and 506 from the two X and Y comparison addresses 501 and 502, respectively, to X_Tag_Word [7: 0] (547) and Y_Tag_Word [7: 0]. (548), X-Data_Word [7: 0] (545), Y_Data_Wore [7: 0] (546), and decode the way_select [1: 0] signal 542 to write_Way [4: 1] To determine which way to write the X_comparison address and the X_physical address to the tag block 580 and the data block 590.

The two-port address translator writes using the X_port at the write operation time, and the read operation time operates in the same manner as the signal port address translator implemented in the present invention in parallel with the X_port and the Y_port.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, in the address converter circuit used in a microprocessor, an access time of the address converter is determined by using a structure in which a tag block is implemented as a cam to simultaneously process entry decoding and cam access to quickly obtain a Way_Hit signal. In addition, the chip area and power consumption are reduced by not using a sense amplifier in each block of the tag. Also, circuits such as an entry selection block and a precharge mux block are developed to reduce the area of the address translator. , Faster access time.

Claims (13)

In a four way set federated address translator circuit, A tag block including a tag way block that is a predetermined number of cam cell arrays and an entry comparison block; A decoder block for decoding the lower three bits of the comparison address; And And a precharge mux block configured to output a physical address by selecting one of the SRAM cell array blocks by using a signal from each of the entry comparison blocks. 4 way set federated address translator circuit comprising data blocks. The method of claim 1, And the tag way block is implemented as an 8 * 17 bit cam cell array as a comparison address storage structure. The method of claim 1, And the SRAM cell array block is implemented as an 8 * 20 bit SRAM cell array as a physical address storage structure. The method of claim 1, And said decoder decodes using one decoder and uses the result in common in a tag block and a data block. The method of claim 1, And decode and tag access in parallel by applying a signal for selecting an entry in the entry comparison block to a signal that is the result of the comparison address comparison of the tag block. The method of claim 1, The entry comparison block logically ANDs the signals coming from the decoder block and the signals coming from the tag way block, and generates a logical elegant signal, and transmits them to the precharge mux block in common. Converter circuit. The method of claim 1, And the precharge mux block circuit selects a predetermined bit physical address from the multiple bit read data of an SRAM cell array block as output signal information of the entry comparison block. A multi-port access four way set federated address translator circuit, A tag block comprising a tag way block composed of a predetermined number of cam cell arrays, and an entry comparison block having a multiple of two times the tag way block; A decoder block for decoding the lower 3 bits of the X_ comparison address and the Y_ comparison address; A SRAM cell array block composed of a predetermined number of SRAM cell arrays and a signal from each entry comparison block are used to select one of the SRAM cell array blocks to output an X-port physical address and a Y-port physical address. And a multi-port access four way set federated address translator circuit comprising a data block consisting of two precharge mux blocks. The method of claim 8, The tag way block is implemented as a multi-port access cam cell array as a comparison address storage structure, and the SRAM cell array block is implemented as a multi_port access SRAM cell array as a physical address storage structure. Port access 4-way set federated address translator circuit. The method of claim 8, And the decoder uses one decoder for each port to decode and use the result in common in a tag block and a data block. The method of claim 8, And decode and tag access in parallel by applying a signal for selecting an entry in the entry comparison block to a signal that is the result of the comparison address comparison of the tag block. The method of claim 8, The entry comparison block logically ANDs the signals coming from the decoder block and the signals coming from the tag way block, and generates a logical elegant signal and transfers the result to the precharge mux block in common. Way set federated address translator circuit. The method of claim 8, Each of the two precharge mux block circuits selects an X_port physical address and a Y_port physical address of a predetermined bit from the multi-bit read data of an SRAM cell array block as output signal information of the entry comparison block. Multi-port access 4-way set federated address translator circuit.