JPH0795266B2 - Match detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a first word composed of one word or a plurality of words,
It holds the second collation data, inputs the first and second signals consisting of one word or a plurality of words, compares them with the first and second collation data, respectively, and when they match, the first and second respectively. The present invention relates to a match detection circuit that outputs a match signal of 2.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional example of this type of coincidence detection circuit,
5 and 6 show the content address memory array 5 of FIG.
1 is a configuration diagram showing the inside of 1,52 (hereinafter referred to as CAM arrays 51,52).

The content address memory (hereinafter referred to as CAM) is a memory that has a data comparison function, and its operation is MO issued by Kyundai Kagaku Co.
It is described in S integrated circuits (P402 to 403) and is used as the CAM arrays 51 and 52 when a large number of comparison operations are simultaneously performed.

The CAM arrays 51 and 52 hold the matching data D ₁ and D ₂ respectively input via the internal bus 53, compare them with the input signals C ₁ and C ₂ respectively input, and if they match, output a match signal to the output line 54 respectively. , 55.

Each of the CAM arrays 51 and 52 has a buffer circuit 60 and CAM registers 61, 62, ..., 6n. CAM registers 62,62, ~, 6n
Has CAM cells 71, 72 to 7k for holding k bits of data in one word. The CAM arrays 51 and 52 input the collation data D ₁ and D ₂ via the buffer circuit 60 and store the data in word units in the CAM registers 61, 62, to 6n. And CA
The data stored in the M registers 61, 62, to 6n are compared with the input signals C ₁ and C ₂ on a word-by-word basis, and if they match, a match signal is output.

[Problems to be Solved by the Invention]

The above-mentioned conventional coincidence detection circuit is provided with CAM arrays 51 and 52 for independently comparing input signals C ₁ and C ₂ with collation data D ₁ and D ₂ , respectively, and a read / write buffer is provided for each of them. Is provided, the use efficiency of the CAM arrays 51 and 52 is low when comparing data with a small number of words,
Further, there is a drawback that the read / write buffer occupies a large area of hardware and is uneconomical.

[Means for Solving the Problems]

The coincidence detection circuit of the present invention includes a content address memory array having a plurality of content address memory registers including a plurality of content address memories so as to hold the first and second verification data in word units; The content address memory array is set to the first and second areas in word units so that each of the two verification data can be held, and the first and second areas are set in the set first and second areas.
Collating data of the first collating data is stored, the first and second regions are made independent by the division instruction, and the first and second collating data held by the independently made regions and the first and second collating data, respectively. The first and second input signals respectively input to the regions of
And a control circuit for comparing the second region and outputting a coincidence signal when they coincide with each other.

[Action]

Since the content address memory array is substantially one array, the first and second collation data writing can be performed by one read / write buffer.
By changing the number of words in the second area, the content address memory array can be used without waste.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the coincidence detection circuit of the present invention, and FIG. 2 is a configuration diagram showing a specific example of the CAM array 1 of the embodiment shown in FIG.

The CAM array 1 is divided into first and second areas 1 ₁ and 1 ₂ according to a division instruction from the control line 7, and the divided first and second areas 1 ₁ and 1 ₂ are collated before division. Data for D ₁ , D ₂
Is written via the internal bus 4. Counter output C ₁ of the counter 2 and 3 are respectively compared with the reference data D _1, D _2, C ₂ is set. When the data D ₁ and D ₂ written in the first and _second areas 1 ₁ and 12 match the counter data C ₁ and D ₂ , respectively, a match signal is output to the match signal output lines 5 and 6, respectively. It

Next, a specific example of the CAM array 1 will be described with reference to FIG.

In this specific example, a match detection of 4 words can be performed with 1 word of 3 bits. When the selection of the control line 17 is instructed from the control line 7, the selection circuit 13 activates the control line 17. When the control line 17 becomes active, the switch elements 17 ₁ , 17 ₂ and 17 ₃ are turned off, and the CAM registers 11 ₁ , 11
_2, 11 ₃ is the first region 1 becomes _1, CAM register 11 ₄ is the second region 1 _2. Before division, 3-word collation data D ₁ is written to CAM registers 11 ₁ , 11 ₂ , and 11 ₃ via internal bus 4 and read / write buffer 12, and _1- word collation data D is written to CAM register 11 _{4. 2} is written. When the 3-word counter data C ₁ and the 1-word counter data C ₂ are set, the counter data C ₁ is compared with the data in the CAM registers 11 ₁ , 11 ₂ , 11 ₃ for each corresponding word, and if they match, they match The signal is output to the coincidence signal output line 5 via the output lines 21, 22, and 23, respectively. Counter data C ₂ is the data D ₂ of the CAM register 11 _4, matching the coincidence signal is output to the match signal output line 6 via the output line 24.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

The coincidence detection circuit of this embodiment is used as a chip select signal generation circuit.

The CAM array 30 is divided into first and second areas 30 ₁ and 30 ₂ according to a division instruction from the control line 37, and first and second areas 3
The verification data AD ₁ and AD ₂ are input to the data bus 3 to 0 ₁ and 30 ₂ , respectively.
Written before splitting through 4. The upper side AC ₂ and the lower side AC ₁ of the address AC of the address bus 31 are given to the CAM array 30 via the upper side bus 32 and the lower side bus 33, respectively. The matching data AD ₁ and AD ₂ are respectively compared with the lower side AC ₁ and the upper side AC _{2 of the} address AC, and if they match, a match signal is output to the match signal output lines 35 and 36, respectively. The control circuit 38 takes the logical sum of the match signal on the match signal output line 35 and a part of the match signal on the match signal output line 36, and outputs the I / O select signal SEL. Of the match signals on the match signal output line 36, signals other than those output to the control circuit 38 are output as they are as the chip select signal CSL of the highly versatile memory that specifies the upper address of the memory.

In this embodiment, the chip select logic can be easily realized, and the number of comparison detection signals with the address signals AC ₁ and AC ₂ can be easily changed, so that the ratio of the memory select and the I / O select can be changed. Can be freely changed, so if the system has a large amount of memory according to the application system, it can handle many memory selects, and if there are many I / Os, it can handle many I / O selects. it can.

〔The invention's effect〕

As described above, the present invention provides first and second content address memory arrays according to the number of words of the first and second input signals to be compared with the content address memory arrays having the content address memory registers for a plurality of words. The first and second input data by comparing the first and second matching data set in the first and second areas with the first and second input signals. Since the total number of words of the input signal of 2 and the number of words of the content address memory array can be made close to each other, there is an effect that the unused portion of the content address memory array is reduced. Since one read / write buffer can be used to set data, there is an effect that the hardware can be made small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the coincidence detection circuit of the present invention, FIG. 2 is a block diagram showing a specific example of the CAM array 1 of FIG. 1, and FIG. 3 is a second block diagram of the present invention. A block diagram showing an embodiment of
FIG. 4 is a block diagram showing a conventional example of this type of coincidence detection circuit,
5 and 6 show the content address memory array 5 of FIG.
1 is a configuration diagram showing the inside of 1,52 (hereinafter referred to as CAM arrays 51,52). 1,30 ...... CAM array, 1 _1, 30 ₁ ...... first region, 1 _2, 30 ₂ ...
… Second area, 2,3 …… Counter, 4,34 …… Internal bus,
5,6,35,36 …… Matching signal output line, 7,37 …… Control line, 11 ₁ , 11 ₂ , 11, ₃ , 11 ₄ …… CAM register, 12 …… Read / write buffer, 13 …… Selection circuit , 14,15,16,17,18 ...... Control line, 14 ₁ , 14 ₂ ~, 18 ₃ ...... Switch element, 21,22,2
3,24 …… Output line, 31 …… Address bus, 32 …… Upper side bus, 33 …… Lower side bus, 34 …… Data bus, 38 ……
Control circuit.

Claims (1)

[Claims] 1. A content address register for holding collation data, a content address memory array comprising an arbitrary number of said content address registers, an arbitrary number of collation data held in said content address memory array, and an input signal. In the coincidence detection circuit which outputs a corresponding coincidence signal when there is matching data for comparison by comparing with, the arbitrary number of verification data are written in the arbitrary number of content address registers forming the content address memory array. Means, means for dividing the arbitrary number of content address registers forming the content address memory array into first and second areas, and arbitrary number held by the divided first and second areas, respectively. And the matching data is compared with the first and second input signals input to the first and second regions, respectively, and they match each other. Coincidence detection circuit, characterized in that each outputs a coincidence signal corresponding to it is if data.