JPS63124298A - Memory device - Google Patents

Abstract

PURPOSE:To efficiently perform a write-access by providing a means for accessing in parallel to m-piece of memory chips group at every n-piece of the memory chips provided with a read/write control means respectively, and further, for erasing at once the stored contents of the aggregations of i-th order in the every group. CONSTITUTION:16 number of the memory chips M1-M16 are divided into 4 groups (bank) at every 4 chips, and M1-M4 are called a first bank, and similarly M5-M8 a second bank, M9-M12 a third bank and M13-M15 a fourth bank. Continuous addresses are assigned to the first-the fourth bank at intervals, in such a way as the address 1 to the first bank, the address 2 to the second bank, the address 3 to the third bank, the address 4 to the fourth bank, and the address 5 to the first bank again, the address 6 to the second bank and so on. As the result, each erase bank includes the continuous address area of the quarter of a whole capacity. Thus, the write access can be efficiently performed against the continuous addresses one after another, and simultaneously the continuous address areas can be efficiently erased integrally too.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory device using electrically rewritable nonvolatile memory called EEFROM or EAROM.

Conventional technology Semiconductor memories such as EEPROM and EAROM are being improved more and more, but at present they require 10,000 times longer time to write and erase than ordinary semiconductor RAM. However, the electrically rewritable and nonvolatile features are very convenient, so there is an extremely high demand for incorporating this type of memory into systems.

Problems to be Solved by the Invention The biggest problem in using EEPROMs and the like is that it takes a long time for writing and erasing. Tsumashi,
When a write access is made to this type of memory chip, the memory chip cannot be accessed for write or read until after a long wait for the write operation to be completed. Therefore, in a system that frequently performs write access, access efficiency becomes extremely poor.

Therefore, the present applicant previously proposed a memory device that uses a plurality of memory chips of this type and attaches a read/write control circuit to each memory chip so that each memory chip can be accessed in parallel. did. According to this configuration, consecutive addresses are assigned to each chip intermittently, such as address 1 to the first memory chip, address 2 to the second memory chip, address 3 to the third memory chip, and so on. There is no longer a large waiting time for write access.

However, in the above case, consecutive address areas cannot be erased all at once. For example, when erasing addresses 1 to 128, address 1 is the first
If the chip address 2 was the second chip and the address 3 was the third chip, it would take a lot of time to erase the entire chip, and the process would be troublesome. This type of memory chip has a function for erasing the entire chip at once in order to perform erasing efficiently. This chip erase function cannot be used in the above case.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to enable efficient write access in a memory device using a large number of memory chips, such as an EEPROM, and to provide continuous address areas. The purpose is to be able to erase them all at once.

Means for Solving the Problems Therefore, in this invention, m×n memory chips are divided into m groups of n pieces each, and each group is provided with a read/write control means so that each group can be controlled in parallel. The i-th (i=1.2...+
Erase control means is provided for erasing the memory contents of a set of memory chips n) as one unit at a time.

Even if the read/write control means of an active group is in the process of write access, the read/write control means of other groups can perform write access and read access.

Further, the erase control means erases a set of the i-th memory chip of each group, that is, m memory chips at once. In this way, the areas that are erased each time are areas with consecutive addresses.

Embodiment FIG. 1 shows the overall structure of a memory device according to an embodiment of the present invention.

In this embodiment, 16 memory chips M1 to M16 are used, and a read/write bank control circuit 1 and an erase/spank control circuit 2 are attached to these.

The 16 memory chips M1 to M16 are divided into four groups of four each. This group is herein referred to as a bank. M1 to M4 are the first bank, M5 to M8 are the second bank, M9 to M12 are the third bank, and M13 to M16 are the fourth bank.
Also, the first set of memory chips M1 in each bank is M1,
M5, M9, and M13 are referred to as a first erase bank. Similarly, the set of M2, M6, MIO1M14 is the second erase bank, the set of M3, M7, Mll, M2S is the third erase bank, and the set of M4, M8, M12, M16 is the fourth erase bank.
Among the address signals that designate one word of the 0-wire memory device called an erase bank, the lower two bits of the address signal f are sent to the read/write puncture control circuit 1 as a signal that designates one of the first to fourth banks. entered, top 2
The bit address signal e is input to the erase bank control circuit 2 as a signal specifying one of the first to fourth erase banks, and the remaining intermediate address signal g is input to each memory chip M1 to M16 in parallel. .

Therefore, the relationship between the memory address, the bank, and the erase bank is as shown in FIG.

Address 1 is the first bank, address 2 is the second bank, address 3 is the third bank, address 4 is the fourth bank, address 5 is the first bank again, address 6 is the second bank, and so on. Consecutive addresses are allocated to the first to fourth banks intermittently. As a result, each erase puncture includes a continuous address area of one-fourth of the total capacity. Figure 2 shows the configuration of the erase bank control circuit 2;
The figure shows the configuration of the read/write puncture control circuit 1.

First, the read operation will be explained. In this case, address signal e+Lg and read signal R are applied. The upper address signal e is decoded by the decoder 21 shown in FIG. 2, and one of its four outputs is activated. The output of the decoder 21 becomes erase bank control signals 21 to 4 through the gate ρ. Also, the read signal R is an OR circuit n
is applied to gate B through the gate B, at which point gate 22 is opened. In other words, a control signal is sent to one erase bank designated by the upper address signal e among the first to fourth erase banks! 1~! 4 will be supplied.

Similarly, in the read/write bank control circuit 1, the lower address signal f is decoded by the decoder 11, and its output passes through the gate 12 at the timing of the read signal R.
Any one of bank read signals R1 to R4 becomes active.

For example, the control signal for the second erase bank! 2 becomes active, and at the same time, the read signal R3 of the third bank becomes active, the memory chip MIO belonging to both the second erase bank and the third bank becomes active, and this chip MI
Information of the word corresponding to the address signal g is read from O.

Next, the write operation will be explained. In this case, an address signal eX fXg and a write signal W are provided. The operation of the erase bank control circuit 3 at this time is the same as above, and the erase bank control signal 21~! at the timing of the write signal W! One of the four becomes active. In the read/write control circuit 1, the output of the decoder 11 passes through the OR circuits 13 to 16 at the timing of the write signal W and is input to the write control circuit 17. A corresponding one of the bank write signals W1 to W4 is activated.

For example, if the control signal -e3 of the third erase bank is activated and the write signal W2 of the second bank is activated, the memory chip M7 belonging to both the third erase bank and the second bank becomes active. This chip M7
Data bus information is written in the area corresponding to the address signal g. Although it takes a considerable amount of time to complete the write operation to memory chip M7, the other three banks other than the second bank to which memory chip M7 belongs can be read without waiting for the write operation to complete. Access and write access are possible.

Next, the operation of batch erasing in units of erase banks will be explained. In this case, an upper address signal e specifying an erase bank, a write signal W, and an erase signal M are applied.

Although not shown, the erase signal M causes each of the memory chips M1 to M16 to enter a chip erase mode.

At the timing of the write signal W, the erase puncture control circuit 2 outputs one of the erase bank control signals 21 to -e4 corresponding to the address signal e in an active state.

Furthermore, in the read/write control circuit 1, the erase signal M is input to any of the four OR circuits 13, 14, 15, and 16, and this signal is input to the write control circuit 17 at the timing of the write signal W. In response to this, the write control circuit 17 outputs four outputs (bank write signals) Wl to W4.
are all active.

As a result of the above, for example, the control signal for the fourth erase bank! 4
When activated, all four memory chips M4, M8, M12, and M2C included in this fourth erase bank are erased at once. The area erased in this way is an area with consecutive addresses.

Effects of the Invention As explained in detail above, the memory device according to the present invention uses a large number of memory chips such as EEPROM, and even if the writing and erasing operations of each chip take a long time, It is possible to efficiently perform write access to consecutive addresses one after another, and it is also possible to efficiently erase consecutive address areas all at once, making this type of memory practical for horizontal aperture systems. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall schematic configuration of a memory device according to an embodiment of the present invention, FIG. 2 is a block diagram of the erase bank control circuit in FIG. 1, and FIG. 3 is a block diagram of the erase bank control circuit in FIG. The block diagram of the write control circuit and FIG. 4 are memory maps of the same embodiment. M1 to M16...Memory chip, l...Read/write control circuit, 2...Erase bank control circuit Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure j 3rXI Figure 4

Claims (1)

[Claims] Divide m×n memories into m groups of n each,
Each group is provided with a read/write control means so that each group can be accessed in parallel, and the i-th (
A memory device provided with an erasure control means for erasing the memory contents of a set of memories (i=1, 2, . . . , n) as one unit at a time.