JPH01265571A - Manufacture of high electron mobility transistor - Google Patents

Abstract

PURPOSE:To make a width of a gate, a space between a gate and a source, and a space between the gate and a drain small to enable a transistor of this design to be high in an operational speed by a method wherein a source, a drain, and a gate electrode are formed in a self-aligned manner. CONSTITUTION:An AlGaAs buffer layer 11, a non-doped GaAs layer 12, an n-type AlGaAs layer 13, an n<+>-type GaAs layer 14, and a Si3N4 layer 20 are formed on a GaAs semi-insulating substrate 10. The layers 20 and 14 are removed through an etching to be partially left unremoved, and a SiO2 layer 24 is formed thereon. The layer 24 is removed leaving its side walls 25a and 25b unremoved, and then the Si3N4 layer 20 is selectively removed through an etching. Resist is provided to the left of the side wall 25a and the right of the side wall 25b, and Al or the like is evaporated to form a source electrode 27, a drain electrode 28, and a gate electrode 29 in a self-aligned manner. After the resist is removed, an ion trimming is performed at an incident angle of 60 degrees to remove the metal evaporated on the side walls 25a and 25b. The space d4 between a source and a drain can be nearly equal to 1mum.

Description

[Detailed Description of the Invention] [Summary] Regarding a high electron mobility transistor in which the source, drain, and gate electrodes are formed by self-alignment, the width of the gate electrode, the distance between the gate and the source, and the width of the gate and drain amount are reduced. In a method for manufacturing a high electron mobility transistor in which a two-dimensional electron gas layer formed at a heterojunction interface is used as a channel layer, a semiconductor layer having a first insulator formed on its surface is etched so as to separate from each other. forming a source layer and a train layer separated by a certain distance; forming sidewalls of a second insulator of a different material from the first insulator on each of the source layer and the drain layer having the first insulator; The first insulator is selectively etched and removed, and metal is deposited to form a source electrode and a drain electrode on the source layer and drain layer surrounded by the sidewalls, respectively, and The structure is such that a gate electrode is formed between them.

[Industrial application field]

The present invention relates to a method for manufacturing a high electron mobility transistor,
In particular, the present invention relates to a method of manufacturing a high electron mobility transistor in which source, drain, and gate electrodes are formed using self-aligned lines.

In recent years, there has been a demand for higher speed information processing devices or communication devices such as computers, and to this end, there is an urgent need to develop higher speed semiconductor devices. One such high-speed semiconductor device is a high electron mobility transistor (HEMT).

[Conventional technology]

FIG. 2 shows a cross-sectional structure of a conventional HEMT.

In the figure, 10 is a GaAS semi-insulating substrate, 11 is an AeGaAS buffer layer with a thickness of approximately 2000 mm, and 12G;
J! l approximately 1000A (7) Non-doped GaAs1l,
13 is n-AtGaASL doped with 3i to about I x 10"ax'3 and has a thickness of about 1000 people!, 14a, 1
4b is a source layer and drain layer of n''-GaAs doped with approximately 5×1018 CjI'3 of Si and has a thickness of about 2000 nm, and 15.16 is an AuG layer with a thickness of about 200 nm.
A source electrode and a train electrode are formed by layering Au with a thickness of about 3000 mm, and 17 is a gate electrode of A with a thickness of about 3000 mm.

HEMl; tGaAs layer 12 and n-AJ! GaAs[1
In order to use the two-dimensional electron gas layer formed at the heterojunction interface with 13 as a channel layer. Electrons are not scattered by impurities, have high electron mobility, have a larger transfer conductance ga+ than ordinary MESFETs (metal semiconductor field effect transistors), and operate at high speed.

[Problem to be solved by the invention]

In the conventional HEMT, the n"-GaAS layer 14 and the electrodes 15 to 17 are formed by ordinary photolithography. Therefore, there is a limit to miniaturization, and the gate electrode 1
7 width dl, gate-source width d2. The width d3 between the gate and drain is usually about 1 μm, and the width is 0.
．． There is a problem in that it is practically difficult to reduce the thickness to 5μ or less.

If the above widths d and -d are large, the source resistance is large,
The gate-source capacitance is large and the transfer conductance ga is small, making it impossible to achieve high speed.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a high electron mobility transistor in which the width of the gate electrode, the distance between the gate and the source, and the amount of the gate and drain are reduced.

[Means to solve the problem]

A method for manufacturing a high electron mobility transistor according to the present invention includes a method for manufacturing a high electron mobility transistor in which a two-dimensional electron gas layer formed at a heterojunction interface is used as a channel layer. Semiconductor 71 (1
4) to form a source II (14a) and a drain Im (14b) that are spaced apart from each other by a certain distance vtm, and the source layer (14a) and drain layer (14b) each having the first insulator (20) are etched. Forming side walls (25a, 25b) with a second insulator made of a different material from the first insulator (20), selectively etching and removing the first insulator (20), and depositing metal. A source electrode (27) and a drain electrode (28) are respectively formed on the source layer (14a) and drain layer (14b) surrounded by the sidewalls (25a, 25b), respectively.

25b), a gate electrode (29) is formed between them.

(Function) In the method of the present invention, the source 71 (14a) and the drain JW (14b) are formed with a minimum fixed distance apart by ordinary photolithography, and this source layer (14a)
) and the train layer (14b), respectively, have side walls (25a, 25
b), and the gate electrode (29) is connected between the side walls (25a, 25b) by the source electrode (27) and the drain electrode (2
8) At the same time, the width of the gate electrode and the distance between the gate and the source and the distance between the gate and the drain can be reduced because the self-alignment is formed.

〔Example〕

FIG. 1 shows a cross-sectional structure of an embodiment of the method of the present invention.

First, as shown in FIG. 1(A), on a GaAs semi-insulating substrate 10, an A2GaAs buffer W111 with a thickness of about 2000 layers and a non-doped GaAs layer 12 with a thickness of 1000 layers are formed.
, a 5X1 n-AlGaAs layer 13.3i doped with Si to a thickness of about 1000 layers
0I8α-3 doped approximately 2000 n+-
GaASJi! il 4 respectively. Thereafter, about 4000 O8izN4 layers (first insulator) 20 are formed by plasma CVD, and resists 21 and 22 for source and drain are formed at intervals of approximately 1 μm.

Next, the 5t3Nt layer 20 is etched by reactive ion etching (RIE) using CHFz (methane trifluoride).
, and further CCez F2 (2-foot conversion 2
Reactive ion etching is performed for approximately 2 minutes using methane chloride in an environment of 100 W and 4 Pa, and the thickness is approximately 2.
000 n''-GaAs semi-insulating etch.

As a result, a source layer 14a and a drain layer 14b are formed. Thereafter, the resists 21 and 22 are removed, and an O8!02 (second insulator) layer 24 of about 4,000 layers is formed on the entire surface. This results in the state shown in FIG. 1(B).

Next, reactive ion etching is performed for 10 minutes using CHF3 at 100 W and 4 Pa for 5 tOz.
Layer 24 is etched to a thickness of 4000 mm to form side walls 25a-25d of 3i02 shown in FIG. 1(C).

After this, 5ixNn, which is a dummy electrode, was etched by reactive ion etching using NF3 (trifluoride trifluoride).
Layer 20 is selectively etched to leave sidewalls 25a and 25b, resulting in the state shown in FIG. 1D.

Next, the left side and side of the side wall 25a on the n-AeGaAs layer 13? , 25 A resist is provided on the right side of b, and Ti/P
Thickness of t/Au is 500 and 100, respectively.

3000 people will be deposited. This may be replaced with the vapor deposition of A.

Thereafter, the resist is removed, and etching is performed using Ar ions at an acceleration voltage of 500 V and an incident angle of 60 degrees for approximately 10 minutes by ion milling to remove the Ti/Pt/Au on the side walls 25a and 25b. Remove.

As a result, as shown in FIG. 1(E), the source electrode 27.
Drain electrode 28. A gate electrode 29 is formed by a self-line. Here, the distance d4 between the source and drain is approximately 1 μm, and the width of the side walls 25b and 25c is approximately 0.4 μm in width between the gate and source and between the gate and drain.
m, and the width of the gate electrode 29 is approximately 0.2 μm.

In this way, the source layer 14a and the drain layer 14b are approximately 1
Source electrodes 27.μmfl1. drain l8i
28. Since the gates ff1wA29 are each formed by a cell line and a line, the width of the gate electrode 29 and the distance between the gate and the source and the distance between the gate and the drain can be made much smaller than before, the source resistance is reduced, and the capacitance between the gate and the source is reduced. decreases and transfer conductance q- increases, leading to faster transistor operation.

〔Effect of the invention〕

As described above, according to the method of manufacturing a high electron mobility transistor of the present invention, the width of the gate electrode and the distance between the gate and source,
It is possible to reduce the distance between the gate and drain, and the speed of transistor operation is increased, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of each step of an embodiment of the method of the present invention, and FIG. 2 is a cross-sectional structural diagram of an example of a conventional HEMT. In the figure, 14 is an n''-GaAS layer, 14a is a source layer, 14b is a drain layer, 20 is an S!zN4 layer, 21.22 is a resist, 24 is a SiO2!i, 25a and 25b are side walls, and 27 is a source electrode. , 28 indicates the drain electrode, and 29 indicates the gate electrode. ) (D) Ladle fat maichi') I-plane elliptical mouthpiece for each crop 1 Figure (Gu no 2) (E) Figure 1 ('?p) 3) C of the l-IEMT in the east Figure 2

Claims (1)

[Claims] A method for manufacturing a high electron mobility transistor using a two-dimensional electron gas layer formed at a heterojunction interface as a channel layer, comprising: a semiconductor layer (20) having a first insulator (20) formed on its surface; 14
) are etched away from each other at a certain distance from the source layer (
14a) and a drain layer (14b), each of the source layer (14a) and drain layer (14b) having the first insulator (20) is made of a material different from the first insulator (20). Side wall with second insulator (2
5a, 25b), selectively etching and removing the first insulator (20), and depositing metal to form a source layer (14a) surrounded by the sidewalls (25a, 25b), respectively; A source electrode (27) and a drain electrode (28) are formed on each of the drain layers (14b), and a gate electrode (29) is formed between the sidewalls (25a, 25b). A method for manufacturing an electron mobility transistor.