JP3450183B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for high-speed operation. 2. Description of the Related Art In recent years, there has been a demand for faster information processing devices such as computers or communication devices, and there has been an urgent need to develop higher-speed semiconductor devices. One of such high-speed semiconductor devices is a high electron mobility transistor (HEMT). A conventional HEMT is, as shown in FIG.
A two-dimensional electron gas layer formed on the side of the GaAs layer 23 at the heterojunction interface between the As layer (electron transit layer) 23 and the n-AlGaAs layer (electron supply layer) 24 is used as a channel layer (electron transit layer). Therefore, the electrons are not scattered by the impurity, the mobility of the electrons is large, the transfer conductance gm is larger than that of a normal MESFET (metal semiconductor field effect transistor), and the high-speed operation is performed. [0004] The HEMT is n ⁺ -GaAs.
Layer 25 and electrodes 26-28 are formed by conventional photolithography. Therefore, miniaturization is limited, and the gate length Lg, the gate-source width Lgs, and the gate-drain width Lgd are each about 1 μm.
In other words, when normal photolithography is used, the gate length Lg, the gate-source width Lgs, and the gate-drain width Lgd are large, so that the source resistance is large.
The capacitance Cgs between the gate and the source is large, the transfer conductance gm is small, and the high speed of the semiconductor element cannot be realized. In order to operate the HEMT at high speed, the gate length Lg, the width Lgs between the gate and the source, the gate
The width Lgd between the drains must be 0.5 μm or less. It is necessary to use an electron beam method or the like for such fine processing, which is practically difficult. Also, the gate electrode 26
When the size is reduced, the electric resistance increases and the loss increases, so that it is impossible to realize a high-speed semiconductor device. Note that FIG.
In the figure, 21 is a substrate and 22 is a buffer layer. In order to solve such a problem, Japanese Patent No. 2670293 discloses a method in which an insulating film 29 is provided on opposite side walls of a source region 25a and a drain region 25b as shown in FIG. By the usual photolithography, the gate length Lg, the width Lgs between the gate and the source, and the width Lgd between the gate and the drain are set to 0.5.
It has been proposed to increase the speed of a semiconductor element by forming the semiconductor element to a thickness of μm or less. However, in this method, the resistance of the gate electrode 26 increases with the miniaturization of the pattern, so that there is a problem that the speed and efficiency of the semiconductor element cannot be improved. SUMMARY OF THE INVENTION The present invention has been made in view of such problems of the prior art, and provides a method of manufacturing a semiconductor device which solves the problems of the conventional devices that high definition and high speed cannot be achieved. The purpose is to: In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of:
On a substrate, a buffer layer, an electron transit layer, n-AlGaAs
After forming an electron supply layer made of and a contact layer made of n ⁺ -GaAs, a SiO ₂ film is formed,
The SiO ₂ film and the n ⁺ -GaAs are etched to form a source region and a drain region made of an island-shaped semiconductor layer, and then an SiO ₂ film is formed to form a gate portion and a SiO ₂ film of a source / drain portion. Is removed by etching so that only SiO ₂
The film is left, and then the substrate is moved from 30 to 60 from the ion irradiation direction.
° by rotating and tilting the SiO 2 by the RIE method.
₂ After removing the corner at the upper part of the side wall of the film, the n
Etching AlGaAs to remove surface defects due to plasma damage, then forming a T-type Al gate electrode,
Next, after the SiO ₂ film in the source / drain portions is removed by etching, AuGe source / drain electrodes are formed. Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a view showing one embodiment of a semiconductor device manufactured by a method according to the present invention, wherein 1 is a substrate, 2 is a buffer layer, 3 is an electron transit layer, 4 is an electron supply layer, and 5 is A contact layer, 6 is an insulating film on the contact layer, 7 is an insulating film on the side wall of the island-shaped semiconductor layer, 8 is a gate electrode, 9 is a source electrode, and 10 is a drain electrode. The substrate 1 is made of GaAs single crystal or Si.
It is composed of a single crystal or the like. The buffer layer 2 has a thickness of 2000 mm.
Of i-AlGaAs or the like, and is provided to reduce the dislocation density in the semiconductor layer. The electron transit layer 3 has a thickness of 10
It is composed of, for example, i-GaAs of 00 °. The electron supply layer 4
N-AlGaAs doped with about 5 × 10 ¹⁷ cm ^{−3 of} Si
s and the like. The contact layer 5 is made of 1 × 10 ^{18 of} Si.
It is made of n ⁺ -GaAs doped at about cm ^-3 . The contact layer 5 and a part of the electron supply layer 4 are formed separately in an island shape. The insulating film 6 on the contact layer 5 is formed of SiO ₂ having a thickness of about 4000 °. The insulating film 7 on the side wall of the island-shaped semiconductor layer is made of SiO.
Formed ₂ or the like, for example, the source-drain interlayer spacing (Lgs + Lg + Lsd) to 1 [mu] m, if the gate length Lg was 0.2 [mu] m, the width (Lgs or Lgd)
Is 0.4 μm. Here, by cutting off the upper edge corner of the insulating film of the island-shaped semiconductor layer, defects such as holes generated at the time of forming the gate electrode can be suppressed. The gate electrode 8 is formed by depositing Al at 3000 .ANG. Or depositing Au / Pt / Ti at 3000 .ANG.
It is formed by vapor deposition of about {500}. The source electrode 9 and the drain electrode 10 are formed by depositing AuGe at 3000 °. As described above, the insulating film 7 is provided on the opposing side walls of the two island-shaped semiconductor layers, and the gate electrode 8 is formed from the insulating film 7 to the semiconductor layer 4.
g, the width Lgs between the gate and the source and the width Lgd between the gate and the drain can be reduced, the gate resistance can be reduced, the capacitance between the gate and the source can be reduced, and the transmission conductance gm can be increased. Can be Further, since the insulating film 7 is provided under the umbrella portion of the gate electrode 8, the gate electrode can be formed with high yield. Next, a method of manufacturing a semiconductor device according to the present invention will be described. First, as shown in FIG.
An i-AlGaAs buffer layer 2, an i-GaAs electron transit layer 3, an n-AlGaAs electron supply layer 4, and n ⁺ -G
The aAs contact layer 5 is formed by MOCVD or MBE, respectively. Thereafter, the SiO _{2 is formed} by a sputtering method.
A film 6 is formed. After that, a resist 11 for source and drain is formed. Next, as shown in FIG. 3, the SiO ₂ film 6 is etched by anisotropic etching RIE using CHF _3, CC1 ₂ F, anisotropic etching (RIE using Cl ₂ or CCl ₄ (Reactive ion etching))
Etches the SiO ₂ film 6 and the n ⁺ -GaAs layer 5. As a result, a source region and a drain region made of the island-shaped semiconductor layer are formed. Next, as shown in FIG. 4, after removing the resist 11, the plasma CV having a good step coverage is obtained.
The SiO ₂ film 7 is formed at a low temperature by a D method, a laser CVD method, a catalytic CVD method, or the like. Next, as shown in FIG. 5, the SiO ₂ film 7 in the gate portion and the source / drain portion is etched away by anisotropic etching RIE using CHF ₃ . That is, the SiO ₂ film 7 is formed only on the side wall portions of the island-shaped semiconductor layers in the source / drain portions. Next, as shown in FIGS. 6 and 12, the substrate 1 is tilted by 30 to 60 ° from the ion irradiation direction, and the substrate 1 is rotated (ω = 5 to 10 rpm) while using CHF _3. Side wall SiO ₂ film 7 by anisotropic etching RIE
Is etched to remove the corner at the upper part of the side wall. afterwards,
Using a H ₂ SO _{4 to} H ₂ O ₂ —H ₂ O-based etchant, the recess portion n-AlGaAs is photo-etched by 100 °,
Eliminates surface defects due to plasma damage. Next, as shown in FIG. 7, Al or Au / Pt / Ti serving as the gate electrode 8 is formed to a desired thickness by a vacuum evaporation method. Next, as shown in FIG. 8, after forming a gate resist 12 for forming a T-type gate having an arbitrary cross-sectional area with reduced electric resistance, a pattern is formed at 55 ° C. H ₃ PO _4.
A T-type Al gate electrode 8 is formed with the liquid. Next, as shown in FIG. 9, a source / drain lift-off resist 13 is applied. Next, as shown in FIG. 10, the lift-off resist 13 for source / drain is patterned. Next, as shown in FIG. 11, after the SiO ₂ film 6 of the source / drain portion is subjected to HF wet etching, AuGe is deposited as the source / drain electrode 9 by 3000 °. Next, as shown in FIG. 12, the AuGe is lifted off and the source / drain electrodes 9 are patterned. As described above, in the method of manufacturing a semiconductor device according to the present invention, an insulating film is provided on the side wall portions of the two island-shaped semiconductor layers opposed to each other, and the insulating film is formed from the insulating film to the semiconductor layer. , The gate electrode can be formed, and the side wall SiO ₂ can be formed.
Of the semiconductor device, the gate length, the width between the gate and the source, the width between the gate and the drain can be reduced, the gate resistance can be reduced, and the capacitance between the gate and the source can be reduced. Since the conductance gm can be increased, the speed and efficiency can be increased, and the insulating film is provided under the umbrella of the T-type gate electrode, the gate electrode can be formed with a high yield. The occurrence of defects can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing one embodiment of a semiconductor device manufactured by a method according to the present invention. FIG. 2 is a view showing a manufacturing process of a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 5 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 6 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 7 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 8 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 9 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 10 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 11 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 12 is a view showing another manufacturing step of the method for manufacturing a semiconductor device according to the present invention. FIG. 13 is a view showing a conventional semiconductor device. FIG. 14 is a view showing another conventional semiconductor device. [Description of Signs] 1 ‥‥‥ substrate, 2 ‥‥‥ buffer layer, 3 ‥‥‥ electron transit layer, 4 ‥‥‥ electron supply layer, 5 ‥‥‥ contact layer, 6 ‥
{Insulating film on contact layer, 7} insulating film on side wall of island-shaped semiconductor layer, 8} gate electrode, 9} source electrode, 10} drain electrode

Claims (1)

(57) Claims 1. A buffer layer, an electron transit layer, an electron supply layer composed of n-AlGaAs, and n
After forming a contact layer made of ⁺ −GaAs,
An O ₂ film is formed, and then the SiO ₂ film and the n ⁺ -Ga
As the forming a source region and a drain region made of etched semiconductor island, then the source and drain portions of the SiO ₂ film of the gate portion and the source and drain portions to form a SiO ₂ film is removed by etching Then, the SiO ₂ film is left only on the side wall of the island-shaped semiconductor layer, and then the substrate is rotated while being inclined at an angle of 30 to 60 ° from the ion irradiation direction.
After removing the corner at the upper portion of the side wall of the SiO ₂ film by the IE method, the n-AlGaAs in the recess is etched to remove surface defects due to plasma damage.
l gate electrode is formed, and then S
After etching and removing the iO ₂ film, the AuGe source
A method for manufacturing a semiconductor device for forming a drain electrode.