JPH01264255A - Memory - Google Patents

Abstract

PURPOSE:To obtain a high-integration and high S/N memory by a method wherein a channel part of a switching MOST inside a cell is formed on a side wall of a groove formed in a silicon substrate and this groove is formed to be a continuous belt shape. CONSTITUTION:A thin insulating layer of silicon oxide or the like is formed on the surface of a substrate; a word line W of a low-resistance material such as polycrystalline silicon or the like is formed on a side face of a groove; this line is oxidized; an insulating layer is formed. Then, the insulating layer at a bottom part of the groove is removed; after that, a low-resistance material such as n-type polycrystalline silicon or the like is filled into the groove; an accumulation capacitance ST is formed; by means of a heat treatment process, an n-type diffusion layer region N1 is formed in the bottom part of the groove by diffusion from the ST. Then, the ST is covered with a thin insulating layer; after that, a plate PL is formed on it by using, e.g., polycrystalline silicon. Lastly, the PL is covered with an insulating layer; after that, an n-type diffusion region N2 is formed on the surface of the silicon substrate by ion implantation or the like; in addition, the surface of the silicon substrate is exposed; a data line D is formed by using a low-resistance material such as Al or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic memory, and particularly to a one-transistor memory cell structure of a highly integrated and high S/N dynamic memory.

(Prior art) The mainstream of dynamic memory (DRAM) cells is the so-called 1-transistor (hereinafter I) consisting of one switching MOS transistor (MO8T) and one capacitor.
T) It is a cell. High integration and high S using IT sector JV
/N RAM, it is necessary to ensure a sufficient capacity of the capacitor within the cell even if the cell area is reduced. For this reason switching capacitor HO5
So-called stacked capacitor (STC) cells have been devised that are formed of polycrystalline silicon over the T and isolation regions. An example of an STC cell is shown in Figure 2 and International Electron Device Meeting, Technical Digest, 1978, pp. 348-3.
51 pages (IEDM Tech, Dig, pp348-
351° 1978).

Furthermore, in order to prevent capacity reduction due to higher integration, many cell structures have been proposed in which a capacitor is formed on the sidewall of a trench dug into a silicon substrate. The most basic cell structure among these is shown in Japanese Patent Laid-Open No. 51-130178.

However, in these cell structures, the channel length of the switching MO8T becomes shorter as the integration becomes higher, so the power supply voltage has to be lowered. Therefore, even if a certain amount of capacitor capacity is secured, the amount of stored charge decreases. There was a problem.

Therefore, by forming the channel part of the switching MO8T on the side wall of the hole, the channel length can be controlled by the depth of the hole even if the integration is high, and a capacitor can be provided on the side wall of the hole, or polycrystalline silicon can be used on the switching MO5T. A cell structure was proposed to form. For example, International Electron Devices Meeting, Technical Digest, 1985, pp. 714-7.
17 pages (IEDMTech, Dig, pp714-
Examples of this include the cell structure shown in Japanese Patent Publication No. 717.1985) and the cell structure shown in Japanese Patent Application Laid-Open No. 62-196867.

[78M to be solved by the invention] The cell structure using the sidewall MO8T described above is a cell structure suitable for a one-intersection cell configuration, and a two-intersection cell configuration has the problem that high integration is impaired. there were. This is because the cell size of the cell structure is determined by the width and pitch of the word Ii. The two-intersection cell configuration has a high S/
This is essential in order to obtain N RAM, and this is discussed in detail in, for example, Jikai [1i51-74535].

Figures 3(a) and 3(b) are from Japanese Patent Application Laid-Open No. 1986-1961167.
FIG. 2 is a plan view and a cross-sectional view, respectively, of the cell structure shown in FIG. MO5T on the side wall of the hole dug into the silicon substrate
is formed, and the information on the data line formed by the n-type diffusion layer passes from the side wall MO8T through the n-type diffusion layer N1 at the bottom of the hole, and is recorded and accumulated in the storage capacitor ST formed at the center of the hole.

The cell structure shown in FIG. 3 has a one-intersection cell configuration, and it is clear that the cell area will be approximately doubled if it is configured as a two-intersection cell configuration.

The object of the present invention is to solve the above problems by providing a highly integrated and high S/S/
[Means for solving the problem] The above purpose is to provide a channel part of a switching MO8T in the cell on the side wall of a trench dug into a silicon substrate, and to form this trench into a hole. This is achieved by forming it in a continuous band rather than in a continuous strip.

[Effect]

If the channel part of the switching MO8T is formed on the trench sidewall, even if the cell area is reduced, the channel length is determined by the trench depth, so there is no need to lower the power supply voltage.
A sufficiently large accumulated charge can be secured. Also, by forming the groove in a band shape.

Since the cell dimensions can be determined by the groove width rather than the word line pitch, a highly integrated groove-shaped two-intersection cell configuration can be realized. As a result, a highly integrated and high S/N memory can be obtained.

〔Example〕

The present invention will be explained in detail below. Although the case where a p-type substrate is used will be described here, the same applies to the case where an n-type substrate is used.

FIG. 1(a) is a plan view showing an embodiment of the present invention, FIG. 1(b)
(c) and (d) are A-A' and B-B in (a), respectively.
' , a cross-sectional view taken along line CC'.

In (,), the unit cell is surrounded by a two-dot broken line.

In the embodiment of the present invention shown in FIG. 1, the switching MO8T is folded along the groove in the STC cell shown in FIG. 2. A data line or 100 pieces of information is selectively recorded and stored in the storage capacitor ST by the word line W.

The features of the embodiment of the invention shown in FIG. 1 are as follows.

(2) The channel length of the switching MO8T can be determined by the groove depth, regardless of the cell area. Therefore, even with high integration, there is no need to lower the power supply voltage. Furthermore, compared to the STC cell shown in FIG. 2, the switching MO8T occupies a smaller area and is highly integrated.

(2) The capacitance of the capacitor is formed on the top surface of the ST and on the side surface substantially perpendicular to the groove. Therefore, depending on the groove depth,
Sufficient capacitor capacity can be obtained.

Due to the above method (■), a sufficiently large charge can be stored within a small cell area.

■It has a two-intersection cell configuration.

I) RAM with high integration and high S/N can be obtained by the above method.

(2) As is clear from comparing FIGS. 1(b) and 2(c) with FIG. 2, contacting the data line N2 is easier than in the conventional STC cell shown in FIG. This is because the step difference in the contact portion is smaller by at least the thickness of the word line W. ■High resistance to soft errors caused by alpha rays. This is because the area of the region N1 where the W product capacitance is in contact with the substrate is small and it is difficult to collect carriers generated in the substrate, and the distance between N1 and the α-ray generation position such as data aD, D is large, and many α-rays are This is because it attenuates before reaching .

FIG. 4 shows a sectional view of another embodiment of the invention.

The plan view is similar to FIG. 1(a). FIG. 4 is a sectional view taken along line AA' in FIG. 1(a).

This embodiment differs from the embodiment of the present invention shown in FIGS. 1(a) to 1(c) in that an insulating layer ISφ is provided over the entire groove bottom and an n-type polycrystalline silicon layer is provided thereon. As a result, n-type diffusion MN1
area becomes even smaller.

Soft errors due to alpha rays can be suppressed to an extremely small level.

FIGS. 5(a)-(8) are process diagrams showing the embodiment of the present invention shown in FIGS. 1(-)-(c). FIG. 5(,) is a plan view, and FIGS. 5(b) to 5(e) are sectional views taken along line AA' in FIG. 1(a).

First, a band-shaped groove is formed on a silicon substrate using a mask. The depth of the groove may be approximately the channel length of the switching MO3T.

Next, as shown in the plan view of FIG. 5(a), an isolation region is formed in a region other than the n-type diffusion layer and the region that will become the channel portion of the switching MO8T.

For this purpose, for example, silicon nitride SN may be appropriately provided and, using this as a mask, the other parts may be oxidized.Then, the silicon oxide is etched so as to have a groove width of -.

Next, as shown in FIG. 5(b), a thin insulating layer of silicon oxide or the like is formed on the surface of the substrate.

Subsequently, as shown in FIG. 5(Q), a word line W is formed on the side surface of the groove using a low resistance material such as polycrystalline silicon, and this is oxidized to form an insulating layer.

Next, as shown in FIG. 5(d), after removing the insulating layer at the bottom of the trench, a low resistance material such as n-type polycrystalline silicon is filled in the trench to form a storage capacitor ST. Through the subsequent heat treatment process, an n-type diffusion layer region N1 is formed at the groove bottom by diffusion from ST, but N1 may be formed in advance by ion implantation into the groove bottom.

Next, as shown in FIG. 5(e), after covering with a 5TtI thin insulating layer, a plate PL is formed of polycrystalline silicon, for example.

Finally, after covering the PL with an insulating layer, an n-type diffusion layer region N2 is formed on the silicon substrate surface by ion implantation, etc., and after exposing the silicon substrate surface, data lo- 1(b), the embodiment of the present invention shown in FIGS. 1(a) to 1(c) is completed.

FIG. 6 shows a sectional view of another embodiment of the invention.

The n-type diffusion lN2 contact to the data line was made at the bottom of the trench. By selecting the word line W, information is recorded and stored in the storage capacitor ST from the n-type diffusion layer N1.

FIG. 7 shows another embodiment of the invention. FIG. 7(a') is a plan view in which the unit cell is surrounded by a two-dot broken line. Figure 7 (
b) is a sectional view taken along line AA' in (a). A word line W was provided at the corner of the bottom of the groove. Since ST is formed along the side wall of the trench above the word line W, any capacitance can be obtained by making the trench deep regardless of the channel length of the word line.

FIG. 8 shows another embodiment of the invention. The plan view is shown in Figure 7 (
Same as a). Figure 8 shows A-A in Figure 7(a).
FIG. The seventh point is that an insulating layer ISφ is provided over the entire trench bottom, and an n-type polycrystalline silicon layer is provided on top of it.
This is different from the embodiment of the invention shown in Figures (a) to (b).

This further reduces the area of the n-type diffusion layer N1,
Soft errors due to alpha rays can be suppressed to an extremely small level.

〔Effect of the invention〕

As explained above, according to the present invention, high integration
A high S/N memory is provided.
54. Brief explanation of drawings
.

1 and 4 to T are embodiments of the present invention, B
FIGS. 2 and 3 are diagrams showing conventional examples.

D, D-...Data line, W...Word line, L...
Diffusion layer region, Nl, N2...n-type diffusion layer, ST...
Storage capacitor, PL...plate, SUB...p-type substrate, IS...insulating layer, Po...n-type polycrystalline silicon,
SN...sily nitride--ζ02. Iso-+-++-
Meh \+--, ++, /〆“1-N, 2■ Figure 1 (d) N/ 5LIB c
C' morphism Figure 2 (α) Figure 2 (b) A÷-1111----------1-YuA/
PO polysilicon 4 Figure 15 IS medium round ball 1 Figure S (α) 5th concave (b) (C) 5th z (d) W Ward Keisho PL Flute No.
Otsuguchi PON2W NI TS 3LIBt'
On Anoh-Silicon Figure 7 A' (α) L 71 W$'iFJ#+FjS.

Figure 7 (b) Po 7t’l #6wagon Figure 8 1o J+, ff Tsuei 1

Claims (1)

[Claims] 1. On the side walls of a plurality of grooves formed along at least one direction of the surface of a first conductivity type silicon substrate, word lines formed respectively along the direction of each groove, and the word lines and an insulating layer are formed. A field effect transistor in which at least a part of the substrates facing each other serves as a channel part, and a second conductivity type region provided in a part of the side surface or bottom of the groove and a part of the surface of the substrate serves as a source/drain. , a low-resistance material connected to one of the second conductivity type regions and serving as a charge storage section; a bit line connected to the other of the second conductivity type regions; and the charge storage section and an insulating layer. A memory characterized in that it has electrodes that serve as plates and are formed by sandwiching the electrodes.