JPH0126194B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device used for impedance conversion in an electret condenser microphone or the like. Conventionally, there are high impedance conversion circuits using J-FETs (junction field effect transistors) as shown in FIGS. 1 to 3. Figure 1 shows two diodes 2 and 3 bidirectionally connected between the gate G and source S of FET 1 , and Figure 2 shows a resistor 4 of several hundred MΩ connected between the gate and source of FET 1 . It is connected. Also, Figure 3 shows
Two PNP transistors 5 and 6 are connected between the gate and source of FET 1. One transistor 5 has its base and collector shorted, and the other transistor 6 has its base and emitter shorted. ing. Each of these connected circuit elements has the role of discharging an input pulse. By the way, the impedance conversion circuit shown in FIG. 1 consists of one FET 1 and two diodes 2,
3. In Figure 2, one FET 1 and one resistor 4,
In Fig. 3, the configuration consists of one FET 1 and two PNP transistors 5 and 6. If each of these were made from a single component, it would be very expensive.
Furthermore, when used in condenser microphones, etc., there are disadvantages in that the number of assembly steps increases and the size also increases. Therefore, recently, manufacturing as an integrated circuit incorporating all the components has become mainstream. here,
The impedance conversion circuit shown in Fig. 3, which has excellent stability characteristics and whose chip manufacturing process is almost the same as manufacturing a single FET, will be explained. In the circuit configuration shown in Figure 3, the stability (recovery time t _r of the output signal with respect to the input signal), which is an important characteristic as an impedance converter, is determined by the leakage current between the gate and source (±I _GSO ) at 0.3V. Fourth
It is already known that there is a correlation as shown in the figure. t _r must normally be several seconds or less, and for that purpose, the value of ±I _GSO must be several tens of nA or more.
However, if it becomes too large, there will be effects such as a decrease in input impedance and deterioration of noise characteristics, so a suitable value is several tens to several hundred nA (20 to 200 nA). ±I _GSO is calculated as follows in Figure 3: −I _GSO = −I _F +h _FE ×(−I _F )=−I _F (1+h _FE ) +I _GSO =+I _F + ^R h _FE ×(+I _F )=+I _F ( 1+ ^R h _FE ), and the current amplification factor of each transistor 5 and 6 is
The value of ±I _GSO is influenced by ^R h _FE . usually,
The ±I _F of FET 1 alone at 0.3V is less than 1 nA (picoampere order), and unless the h _FE and ^R h _FE of the transistors 5 and 6 mentioned above are several hundred to several thousand, it will not work as an impedance converter. will not be able to fulfill its role. Now, in manufacturing a semiconductor device chip having the circuit configuration shown in FIG. 3, it is desirable that the process be as streamlined and simple as possible. Figure 5a
An example of a manufacturing method in which two PNP transistors 5 and 6 are simultaneously manufactured using a process that is almost the same as that for manufacturing a single FET 1 is shown in d. First, as shown in FIG. 5a, an N-type epitaxial layer is grown on a P-type silicon substrate 11.
Isolation diffusion is performed to separate this epitaxial layer into three island regions (N ^- layer) 12, 13, and 14 that will become the bases of the FET channel and the two PNP transistors. Next, as shown in FIG. 5b, an oxide film (SiO ₂ ) is formed on the surface of the substrate 11.
15 is formed, and this oxide film 15 is coated with PEP ( P hoto
By simultaneously providing the gate diffusion hole 16 of FET 1 and the emitter diffusion holes 17 and 18 of transistors 5 and 6 by engraving process, and diffusing P -type impurities such as boron, the gate region 19,
Emitter regions 20 and 21 are formed. Next, in a similar manner, as shown in FIG .
form 23. Finally, wiring 24 is provided between the FET 1 and the two transistors 5 and 6 using an electrode material such as aluminum (Al) to obtain a semiconductor device having a circuit configuration similar to that shown in FIG. 3. Here, the gate region 19 is electrically connected to the silicon substrate 11, and the collector regions of the transistors 5 and 6 utilize the silicon substrate 11. Here, the impurity concentration of each region is, for example, 3×10 ¹⁵ cm ⁻³ for the base and channel, 4×10 ¹⁶ cm ⁻³ for the collector, and 2×10 ²⁰ cm ⁻³ for the emitter and gate. As is clear from the above manufacturing process, the channel region 25 of FET 1 and the base regions 26 and 27 of transistors 5 and 6 are formed to have exactly the same thickness. Therefore, h _FE and ^R h _FE of transistors 5 and 6 are N
The shape of the epitaxial layer is determined by the concentration of the island regions 12-14 of the epitaxial layer. However, the characteristic distribution of ±I _GSO of the structure manufactured by this method is −
Although I _GSO almost satisfies the requirements, the level of +I _GSO is too low and stability deteriorates. Therefore,
This means that it cannot be used for impedance conversion of condenser microphones, etc. These phenomena are caused by +I _F (several pA) and -I _F (several tens to hundreds of pA) at around 0.3V for FET 1 alone.
In addition, the base widths of transistors 5 and 6 are exactly the same, and (1+h _FE ) of transistor 5 and (1+ ^R h _FE ) of transistor 6 are 1.
This is thought to occur because the difference is not more than an order of magnitude. ＋I _GSO
In order to raise the voltage to a level of 10 to 100 nA, ^R h _FE of transistor 6 needs to be two orders of magnitude larger than h _FE of transistor 5 . For example, transistor 5 : −I _F × (1 + h _FE ) ≒ 100 pA ×
(1+ 103 )=100nA Transistor 6 ^: + _IF × (1 _+RhFE ⁾ ≒1pA×
(1+ 10 ⁵ )=100 nA The h _FE of transistors 5 and 6 is determined by the base concentration in this example as described above. Therefore , h _FE (h _FE

Claims (1)

[Claims] 1. A junction field effect transistor, a first bipolar transistor whose emitter is connected to the source of the junction field effect transistor, and whose base and collector are connected to the gate, respectively; and a first bipolar transistor whose source is connected to the source of the junction field effect transistor. The base and emitsuta are
In a method of manufacturing a semiconductor device comprising a second bipolar transistor having a collector connected to its gate, the first conductivity type semiconductor substrate is used as a common collector region of the first and second bipolar transistors, and one part of the semiconductor substrate is forming at least two base regions of a second conductivity type and a channel region of the junction field effect transistor on the main surface; and forming an oxide film and an oxidation-resistant film on the semiconductor substrate on which the base region and the channel region are formed. a step of sequentially depositing films and forming a first opening in the oxide film and the oxidation-resistant film at a position corresponding to a region where the emitter of the second bipolar transistor is to be formed; oxidizing, and after removing the oxide film in the first opening and the oxidation-resistant film, a region of the oxide film where the gate of the junction field effect transistor is to be formed and an emitter of the first bipolar transistor; forming second and third openings at positions corresponding to the respective formation regions; and diffusing a first conductivity type impurity into the base and channel regions through the first, second, and third openings. simultaneously forming a gate region of the junction field effect transistor, an emitter region of the first bipolar transistor, and an emitter region of a second bipolar transistor deeper than the emitter region of the first bipolar transistor; A method for manufacturing a semiconductor device, comprising: