JPH03219641A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a bipolar transistor provided with an SBD (Schottky barrier diode) of a structure in which an output voltage of 'L' is not affected by a collector series-resistance by a method wherein an npn transistor and the SBD are formed in separate element formation regions. CONSTITUTION:An SBD is formed inside a separate element formation region which has been separated from a transistor by an isolation region 7; a cathode electrode 14 is formed on a cathode contact region 13 connected to a buried layer 12; an anode electrode 15 is formed on an n-Si epitaxial layer 3. By interconnections on a substrate, the cathode electrode 14 is connected to a collector electrode 11 and the anode electrode 15 is connected to a base electrode 10. In this case, the potential VA at a point A becomes VA = VBE-VF when the voltage between a base and an emitter is designated as VBE and the forward voltage of the SBD is designated as VF. The VA (corresponding to the output voltage of 'L') can be controlled irrespective of the value of rSC. Since the value of rSC can be neglected, the degree of pattern-designing freedom can be made large.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a bipolar transistor with Schottky barrier diodes (58 ports) 8II L 11
■ Output voltage. , is 1/1 N! compared to a bipolar transistor formed in the element formation region of a semiconductor substrate for the purpose of providing a bipolar transistor with SBD having a structure that is not affected by the collector series resistance rsc. A Schottky barrier diode formed in an element formation region separate from the element formation region across an I region, a wiring connecting the cathode of the Schottky barrier diode to the collector of the bipolar transistor, and an anode of the Schottky barrier diode. and a wiring connected to the base of the bipolar transistor.

[Industrial application field]

The present invention relates to a semiconductor device having a bipolar transistor with SBD.

As is well known, the bipolar transistor with SBD has 58 ports inserted between the collector and terminal of the bipolar transistor, and the carriers accumulated in the base region during the switching operation of the transistor are released through the SOD to improve the switching speed. T
It is widely used in TL integrated circuits and the like.

[Conventional technology]

FIGS. 3(1) and 3(2) are a sectional view and a plan view of a conventional bipolar transistor with SBD.

In the figure, an n-type buried layer 2 is formed on the surface of a p-type silicon (p-9i) substrate 1, and an n-type silicon (n-St) layer is formed on the surface of the p-type silicon (p-9i) substrate 1.
Shrimp layer 3 is growing.

An isolation region 7 is formed around the element formation region by diffusing p-type impurities.
is formed, and the n-5i copper layer 3 in the element formation region becomes a collector region.

A p-type base region 4 is provided in the collector region.
An n-type emitter region 5 is formed therein.

Further, an n-type collector contact layer 6 is formed in the collector region so as to reach the buried layer 2.

An insulating film 8 covering the entire surface of the substrate includes an emitter region 5° and a base region 4. Openings are made on the collector contact layer 6, and the emitter electrodes 9. Base electrode 10. A collector electrode 11 is formed.

The base electrode 10 is formed across both the base region 4 and the collector region 3, and the base electrode 10/collector region 3
An SBD is formed between them.

In this way, conventionally, the base window of the npn (npn) transistor and the anode side window of the SBD were commonly opened in the same element formation region as one element.

[Problem to be solved by the invention]

The problems with the conventional example will be explained using the following equivalent circuit.

FIG. 4 shows an equivalent circuit of a conventional example.

In this case, the potential vA at point A is the voltage between the base and emitter of V, . . . , the forward voltage of the SBD is . “If the output current of L11 is I.L.

Va ``Vmi Vr+rsc' lot, and V
a (corresponding to the "L" output voltage VOL) is greatly influenced by the rscO value.

In practice, the output transistor has a large +IOL value (rs
Since the c'lot value cannot be ignored, r3. It is necessary to design a small value, but it is structurally impossible to reduce this to 0.

An object of the present invention is to provide an Ibora transistor with an SBD structure in which the output voltage VOL of L11 is not affected by the collector series resistance rsc.

[Means to solve the problem]

The above-mentioned problem is solved by a bipolar transistor formed in an element formation region of a semiconductor substrate and a Schottky barrier diode formed in an element formation region separate from the element formation region separated by one isolation region.

This is achieved by a semiconductor device having a wiring connecting the cathode of the Schottky barrier diode to the collector of the semi-bolar transistor, and a wiring connecting the anode of the Schottky barrier diode to the base of the bipolar transistor.

[Effect]

In the present invention, by forming the npn) transistor and the SBD in separate element formation regions, the cathode of the SBD is connected to the outside of the collector series resistor rsc, so that the output voltage V.

VOL=VA=VI VF (see FIG. 2), and this result is used to prevent the output voltage V.L from being influenced by the collector series resistance rsc.

〔Example〕

FIGS. 1 (1) and (2) show an SB according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view and a plan view of a bipolar transistor with D.

In the figure, an n-type buried layer 2 is formed on the surface of a p-3i substrate 1.
is formed, and n-3i shrimp N3 are grown on it.

An isolation region 7 is formed around the element formation region by diffusing p-type impurities.
is formed, and the n-3t copper layer 3 in the element forming region becomes a collector region.

A p-type base SM region 4 is formed in the collector region, and an n-type emitter region 5 is formed in the base region 4.

Further, an n-type collector contact layer 6 is formed in the collector region so as to reach the buried layer 2.

An insulating film 8 covering the entire surface of the substrate includes an emitter region 5° and a base region 4. Openings are made on the collector contact layer 6, and the emitter electrodes 9. Base electrode 10. A collector electrode 11 is formed.

The SBD is formed in a separate element formation region separated from the above transistor by a separation region 7, and a cathode electrode 14 is formed on a cathode contact 7113 connected to the buried layer 12, and an n-3i dielectric layer 3 An anode electrode 15 is formed thereon.

The cathode electrode 14 is connected to the collector electrode 11 and the anode electrode 15 is connected to the base electrode 10 by wiring on the substrate.

FIG. 2 is an equivalent circuit of the embodiment.

In this case, the potential at point A is ■. If the voltage between base and emitter is V, 5BDO forward voltage is 2.

VA=V. -vF, vA ('“L 11 output voltage■.Equivalent to L)
can be controlled independently of the rscO value.

Furthermore, since the 1rlcO value can be ignored, the degree of freedom in pattern design increases.

Next, an example of the effects of the embodiment is shown in FIG.

The figure is ■. , I. The L dependence is shown for the embodiment and the conventional example.

Here, +VIE+ vF is current dependent.

Vsi=0.8V.

VF = 0.5V.

rsc=3Ω And so.

In the example, ■ as in the conventional example. As L increases, ■.

, no increase was observed.

[Effects of the Invention] As explained above, according to the present invention, the output voltage of II L 11 is ■. A bipolar transistor with an SBD having a structure in which , is not affected by the collector series resistance rsc was obtained.

[Brief explanation of drawings]

FIG. 1 (11, (2)) shows an SBD according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view and a plan view of a bipolar transistor. FIG. 2 is an equivalent circuit of the embodiment. FIGS. 3(1) and 3(2) are a cross-sectional view and a plan view of a conventional bipolar transistor with SBD. Figure 4 shows the equivalent circuit of the conventional example. FIG. 5 is a diagram showing an example of the effects of the embodiment. In the figure, l is a p-5i substrate. 2 is a buried layer 3 is an n-Si shrimp layer 4 is a base region. 5 is the emitter area. 6 is a collector contact layer. 7 is a separation area. 8 is an insulating film. 9 is an emitter electrode. 10 is a base electrode. 11 is a collector electrode 12, and a buried layer 13 for SBD is a cathode contact layer. 14 is a cathode electrode. 15 is an anode electrode (1) cross-sectional view; (2) plan view; Fig. 2 Explaining the effect of a real whip example Fig. 13 Fig. M5

Claims (1)

[Scope of Claims] A bipolar transistor formed in an element formation region of a semiconductor substrate; a Schottky barrier diode formed in an element formation region separate from the element formation region across an isolation region; A semiconductor device comprising: a wiring whose cathode is connected to the collector of the bipolar transistor; and a wiring whose anode of the Schottky barrier diode is connected to the base of the bipolar transistor.