JPH01256148A - Bicmos gate array lsi - Google Patents

Abstract

PURPOSE:To make it possible to operate the title LSI at high speed and at a low power consumption and also to accomplish high degree of integration by a method wherein a logic circuit is constituted using the substrate element, consisting of a CMOS transistor, and the auxiliary element composed of a bipolar transistor. CONSTITUTION:A fundamental element 1 arranged in an array form, an auxiliary element 2 is also arranged adjacent to the fundamental element array, a high polar CMOS (BiCMOS) buffer circuit, having a totem pole output stage, is constituted by wiring-connecting a multistage series gate, having low driving capability, or a high load driving gate. As a result, high integration can be accomplished, the BiCMOS buffer which is operated at high speed can be formed, a leakage current is reduced, and power consumption is also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor hybrid circuit device comprising CMOS transistors and bipolar transistors, and particularly to a BiCMOS gate array LSI that achieves high integration.

[Summary of the Invention] The present invention achieves high speed, low power consumption, and high integration in a BiCMOS gate array LSI by configuring logic gates using basic elements consisting of CMOS transistors and auxiliary elements consisting of bipolar transistors. It is something.

[Prior art] A schematic diagram of a conventional BiCMOS gate array LSI is shown in the second diagram.
As shown in the figure.

In Fig. 2, 4 is a basic element consisting of a CMOS transistor and a bipolar transistor, and 5 is a ■0 cell area.6 Conventional B i CMOS gate array LS
As is clear from FIG. 2, I was composed of a basic element area in which basic elements 4 are arranged in an array, and an IO cell area 3.

[Problem to be Solved by the Invention 1] However, in the above-mentioned conventional technology, since the basic element includes two types of elements, a CMOS transistor and a bipolar transistor, it is difficult to miniaturize the basic element, that is, to achieve high integration. there were. In addition, although the BiCMO3 circuit has significantly improved load capacitance characteristics compared to the MO3 circuit, the delay time during no-load is increased, so
Even if three circuits were configured, there was a problem in that the speed was not simply increased, but on the contrary, the power consumption only increased.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a B i CMOS gate array LSI that has high speed, low power consumption, and high degree of integration.

[Means for Solving the Problems] The BiCMOS gate array LSI of the present invention includes a plurality of C
The device is characterized in that it has a basic element made of a MOS transistor and an auxiliary element made of a plurality of bipolar transistors, and the basic element and the auxiliary element are arranged.

[Embodiment] FIG. 1 is a chip configuration diagram of a BiCMOS gate array LSI in an embodiment of the present invention.

In FIG. 1, ■ is a basic element consisting of a plurality of CMOS transistors, 2 is an auxiliary element consisting of at least two bipolar transistors, and 3 is an auxiliary element consisting of at least two bipolar transistors.
is the IO cell area.

Basic elements l are arranged in an array and logic gates are assembled to improve the degree of integration. Further, by arranging the auxiliary element 2 adjacent to the basic element array and wiring-connecting it to a multi-stage series gate with low driving capability or a high-load driving gate, a BiCMOS buffer circuit having a totem pole output stage is constructed.

In this example, the basic element array was divided into two and the auxiliary elements were arranged between the basic element arrays, but this embodiment can also be implemented by not dividing the basic element array and arranging the auxiliary elements at both ends of the basic element array. It has the same effect as the example.

[Advantageous Effects of the Invention 1] As described above, according to the present invention, high integration is possible because the logic gate is configured with a basic element array consisting of CMOS transistors.

Further, according to the present invention, since the auxiliary elements made of bipolar transistors are arranged adjacent to the basic element array, the BiCMOS buffer circuit can be easily formed and the speed can be increased.

Further, according to the present invention, since the number of bipolar transistors is extremely small compared to the conventional example, leakage current is reduced and power consumption is reduced.

Further, according to the present invention, since the number of bipolar transistors can be reduced, the defect rate due to crystal defects etc. can be dramatically improved, and manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a chip configuration diagram showing an embodiment of the BiCMOS gate array LSI of the present invention. FIG. 2 is a chip configuration diagram showing a conventional BiCMOS gate array LSI. l... Basic element (CMOS transistor) 2... Auxiliary element (bipolar transistor) 3... IO cell area 4... Basic element (0MO5 transistor and bipolar transistor) Applicant: Seiko Epson Corporation

Claims (1)

[Claims] In a BiCM@O@S gate array LSI consisting of CM@O@S transistors and bipolar transistors, a basic element consisting of a plurality of CM@O@S transistors;
A BiCM@O@S gate array LSI, characterized in that it has an auxiliary element consisting of a plurality of bipolar transistors, and the basic element and the auxiliary element are arranged.