JPS63150935A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase working speed, and to improve the characteristics of the reduction of power consumption by composing a fundamental cell of two input-gate CMOS transistors and one N-P-N bipolar transistor and driving a bipolar transistor organizing the output step of a logic gate and the bipolar transistor while logically connecting the CMOS transistor taking a logic in a gate array LSI. CONSTITUTION:When either one of inputs 14 or 15 is positioned at a '1' level, either of NMOSs 10, 11 is turned ON. Loading is discharged by a path tying an output terminal 16 and a fixed potential terminal 201, and an output reaches a 4 '0' level. Either one of PMOSs 8, 9 is turned OFF at that time, a path tying a power terminal 200 and a base terminal for an N-P-N 13 is brought to a detached state. Both the base terminal for the N-P-N 13 and an emitter terminal are fixed at a '0' level. When both inputs are positioned at the '1' level, both the NMOSs 10, 11 are turned ON. Since both the PMOSs 8, 9 are turned OFF, the output reaches the '0' level by the same reason as one of the inputs is brought to the '1' level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor large-scale integrated circuits, and particularly to 0MO3
) This invention relates to a high-speed, low-gt power gate array LSI consisting of transistors and bipolar transistors.

[Summary of the invention]

The present invention is a gate array LSI consisting of transistors and N'PN bipolar transistors. Njista and IN
Low power consumption characteristics of cMOS gate array 13 and bipolar gate array LSI, consisting of PN bipolar transistors and logically connecting bipolar transistors that form the output stage of logic gates and transistors that drive the bipolar transistors and take logic. It is intended to supply

[Problem that the invention seeks to solve]

A gate array LSI is a 1
Among the several photomasks, only the masks corresponding to the wiring are created according to the product to be developed, and an LSI having the desired electric circuit operation can be manufactured in a short period of time and at low cost. Gate arrays I and S have bonding pads and input/output circuits on the outside of the chip, and inside, basic cells consisting of elements such as transistors are arranged in a matrix, and adjacent cells are arranged in order to obtain the desired electrical circuit operation. Connect the basic cells and perform NAND
One LSI is constructed by configuring electrical logic circuits such as gates and flip-flops, and connecting a plurality of 14-channel logic circuits according to a logic diagram.

In the conventional CM''''OS gate array L3 design, the basic cell is composed of 0 MO3) transistors, hence the CMO
It has been used as a large-scale integrated circuit device with the low power consumption characteristic of three circuits.

However, MOS transistors have a small transfer conductance, and when the load capacity is large or when the transistors are connected in series and the drain parasitic capacitance is large, charging and discharging takes a long time and the transmission speed becomes slow.

Furthermore, in the conventional bipolar gate array LSI, the basic cell is composed of a bipolar transistor and a resistor, and it has been used as a high-speed integrated circuit device because of the large transfer conductance, which is a characteristic of bipolar circuits. However, the bipolar transistor circuit is a circuit in which current flows constantly due to its circuit configuration and operation, and has the disadvantage of high power consumption because a large current flows into and out of a low impedance circuit.

An object of the present invention is to compensate for the above-described drawbacks of low speed operation of the 0M0S gate array LSI and high power consumption of the bipolar gate array LSI, and to provide a high speed and low power consumption gate array Is.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention includes (1) a master slice type gate array LSI;
In this case, the basic cells constituting the logic gates drive the bipolar transistors and bipolar transistors constituting the output stage of the logic gates, and the logic
MO3) is characterized by consisting of a transistor.

(2) In the above item 1, the basic cell includes a first P-type field effect transistor whose gate is connected to the first input terminal, and a first P-type field effect transistor whose gate is connected to the input terminal.
and a first NPN bipolar transistor whose base, collector, and emitter terminals are respectively programmably wired. (3) In accordance with item 1 or 2 above. The base terminal of the first NPN bipolar transistor in the first basic cell is connected to the drain terminal of the logic P-type field effect transistor, the collector terminal is connected to the power supply terminal, and the emitter terminal is connected to the output terminal. It is characterized by

(4) In the above item 1 or 2, the base terminal of the second NPN bipolar transistor in the second basic cell is connected to the source terminal of the N-type field effect transistor that takes logic, and the collector terminal is the output connected to the terminal,
It is characterized in that the emitter terminal is connected to a fixed potential terminal.

(5) In the above paragraph 1 or 2, the first ON
The emitter terminal of the I'N bipolar transistor and the collector terminal of the second NPN bipolar transistor are connected to the same output terminal, so that they are totem-pole connected.

(6) In the above paragraph 1 or 2, the above NPN
A resistor is connected between the base terminal and emitter terminal of the bipolar transistor.

[Effect]

The present invention focuses on the low current consumption characteristics of the CM''68 circuit and the high speed operation characteristics of the bipolar circuit, and attempts to obtain a high speed and low attenuation gate array 1S structure using a composite circuit that combines both circuits as a basic cell. 0M with very high input impedance.
O3) It is composed of transistors, and the output stage is composed of NPN bigolar transistors with large transfer conductance. Here, since the NPN bipolar transistor is driven using the output current of the 0MO8 circuit as a base current, the control of the NPN bipolar transistor becomes very easy.

The configuration described above achieves the above object.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

Figure 1 shows an example of the configuration of a basic cell, including a P-type field effect transistor (hereinafter referred to as PMO13), an N-type field effect transistor C (hereinafter referred to as NMOB), an NPN bibo 2 transistor (hereinafter referred to as NPN), and a It consists of a resistor made of silicon or a diffusion layer.

In Figure 1, 2 is the gate of puosl, 3 is PM
Of9217)K), 4 is the gate of NMO81,
5 indicates the gate of NMOS 2, 6 indicates a resistor, and 7 indicates NPN1.

Figure 2 shows a two-person N8R circuit.

In FIG. 2, 8 and 9 indicate PMo S, and PMO
The source terminal of i98 is connected to the power supply terminal 200, the drain terminal of 2MO38 is connected to the source terminal of PMO39, and the PMO89
The drain terminals of PM188 and PMOS9 are connected to different input terminals 15 and 14, respectively. In addition, 10.11 in the figure indicates an NMOS, each source terminal of NM S10 and NMO311 is connected to the fixed potential terminal 201, each drain terminal is connected to the output terminal 16, and NMτ3
The respective gate terminals of NM'i5'' 311 and 10 are connected to the above-mentioned input terminals 14 and 15. Furthermore, 13 in the figure indicates NPN, and the collector terminal is connected to the power supply terminal 2.
00, the base terminal is connected to the drain terminal of PM089, the emitter terminal is connected to the output terminal 16, and the base terminal and emitter terminal of the NPH are connected by a resistor 12.

The logical operation in FIG. 2 is as follows.

First, when either input 14 or 15 is at the ``1'' level, either NM''''oS 10 or 11 is on, and the load capacitance is discharged through the path connecting the output terminal 16 and the fixed potential terminal 201. , the output becomes @0'' level. At this time, either one of 2MO38゜9 is off, the path connecting the power supply terminal 2゜O and the base terminal of NPNl3 is cut off, and both the base terminal and emitter terminal of NPNl5 are at the 10" level. Fixed.

That is, although the collector terminal is connected to the power supply terminal 200, no forward bias is applied between the base terminal and the emitter terminal, and the NPN 13 is in an off state.

Also, when both inputs are at ul'' level, NM3110.
11 are both turned on, and both PMOSs 8 and 9 are turned off, so the output becomes ``O#'' level for the same reason as when one of the inputs is at 11'' level.

On the other hand, when both inputs are at 0'' level, NMO910, 1
1 are both turned off, and the path connecting the output terminal 16 and the fixed potential terminal 201 becomes disconnected. Also PMOS8
．． 9 are both turned on, and the load capacitance is charged through the path connecting the power supply terminal 200 and the output terminal 16. At this time, PM
The current flowing through O38,9 not only charges the load capacitance through the resistor 12, but also flows as the base current of the NPN13, forming a forward bias condition between the base terminal and the emitter terminal, turning it on. .

Therefore, the load capacitance is charged not only by the charging current from the PMOs 38 and 9 (but also by adding the charging current from the NPN 15), and the output becomes @1'' level.Here, the resistor 12 is connected to the Sometimes, it divides the charging current for the load capacitor and the base current, and when the NPN/Ibora transistor is off, it has the function of drawing out the accumulated charge accumulated in the base.

The above configuration realizes N'''6R logic.

According to this embodiment, the N''5a'5a circuit generation caused by the decrease in PMOS transfer conductance and the increase in drain parasitic capacitance that occurs when configured with a 0M03 circuit is reduced to
Compensated by the large transfer conductance of the PN bipolar transistor, it is possible to realize high-speed NOR operation.

Further, according to the present embodiment, the 0MO8) transistor and the N
Minimum configuration of PN bipolar transistor requires 2 manpower N”5
Since the ``R@ path'' can be realized, it becomes easy to construct a large-scale integrated circuit.

Further, according to this embodiment, a high input impedance circuit using 0MO3)7 transistors and a low output impedance circuit using NPN bipolar transistors can be realized, and as a result, low power consumption characteristics and high speed operation characteristics can be realized.

FIG. 3 shows an example of a layout pattern constituting this bipolar/CMτS dual current circuit.

In Fig. 3, 17 indicates a contact hole, 18 indicates a peer hole, and the input terminal and output terminal are as follows:
The cell is connected to the outside of the cell via a peer hole using at least two or more layers of metal wiring.

According to this embodiment, not only a minimum-configuration NOR circuit is formed using an 0MO3) transistor and an NPN bipolar transistor, but also logic connections are easy and wiring efficiency is improved by making the NPN bipolar transistors horizontally symmetrical. can be realized.

Another logic circuit embodiment is shown in FIG.

Figure 4 shows an example of the configuration of a four-person NAND circuit.
This compensates for the reduction in transfer conductance and increase in drain parasitic capacitance due to series connection.

Although there is a difference between NMO8 correction and PMτS correction,
The basic concept of compensating for the drop in transfer conductance of MOS transistors due to series connection is the same as that of the NOR circuit.

The logical operation in FIG. 4 is as follows.

PMO319, 20, 21, 22 each have their source terminals connected to 1
fi source terminal 200 , and each drain terminal is connected to output terminal 33 . Also NMO323,24,2
5 and 26 have their drain terminals and source terminals connected to each other, and the drain terminal of NMO 825 is connected to the output terminal 33, uM.

The source terminal of S26 is connected to the fixed potential terminal 2 via the resistor 27.
Connected to 01. In addition, the collector terminal of NPN28 is connected to the output terminal 33, and the base terminal &'iNMO326
The emitter terminal is connected to the fixed potential terminal 201, and the base terminal and emitter terminal are connected to the resistor 201.
7. Furthermore, PMO322 and NMO
The gate terminal of s23 is connected to the input terminal 29, and the gate terminal of PMOS21
and the gate terminal of NMO324 are input terminal 3o, and the gate terminal of PMO324 is
The gate terminals of S20 and NMO325 are connected to the input terminal 31,
The gate terminals of PMO819 and NMO326 are input terminal 3.
Connected to 2.

In the above configuration, when any one of the inputs 29, 30, 31, and 52 is at the 10'' level, the path connecting the output terminal 33 and the power supply terminal 200 is opened, and the load capacitance is charged. At this time, the NMOS side is turned off. Fixed potential terminal 201
The path connecting output terminal 53 is left open and NP
The base and emitter of N28 are set at a fixed potential. Therefore, the NPN 28 has no forward bias between its base and emitter and is off. As a result of the above, the output is 1
“It becomes a level.

Also human power 29. ．． 50, 51.32 are all''1〃1
〃The level and PMOS are all turned off, and the path connecting the power supply terminal 200 and the output terminal 33 is disconnected. -10,000NMO
All of S are turned on, and the path connecting the fixed potential terminal 201 and the output terminal 33 is connected. As a result, the charges stored in the load capacitance are discharged to the fixed potential terminal 201 through the paths of NM0823.24, 25, and 26. At this time, the discharge current is shunted by the resistor 27, and a part of the current acts as a base current, applying a forward bias between the base and emitter of the NPN 28 and turning on the NPN 28.
In addition to the path of 4, 25e26, the discharge path by NPN 28 is opened, and the discharge is rapidly made to bring the output to the @Om level.

According to this embodiment, it is possible to configure a NAND circuit with a minimum configuration using an oMos transistor and an NPN bipolar transistor.

4-person NAN using Konohibola/CMO3 composite circuit
An example of the layout pattern of the D circuit is shown in FIG.

Still another embodiment is shown in FIG.

Figure 6 shows a totem pole output type 2-input NAND circuit, and Figure 7 shows a totem pole output type 2 input NAND circuit.
It shows an example of a layout pattern of an OR circuit.

According to the above embodiment, since the output stage is constituted by a totem pole of NPN bipolar transistors, high-speed operation is possible even when the load capacitance becomes large.

〔Effect of the invention〕

As described above, according to the present invention, it is possible not only to configure a high input impedance circuit using 0MO8) transistors and achieve low power consumption characteristics, but also to configure a low output impedance circuit using NPN bipolar transistors.
This has the effect of realizing high-speed operation characteristics.

Furthermore, according to the present invention, not only the totem pole output (,
NPN bipolar transistors can be used as a transfer conductance correction circuit for MOS transistors, which has the effect of improving not only the delay characteristics due to load capacitance, but also the delay characteristics due to the reduction in transfer conductance caused by series connection of MOS transistors. has.

Further, according to the present invention, the basic cell includes two PMOSs,
Since it can be configured with two NMO3 and one NPN elements, it has the effect of realizing a very small basic cell and easily configuring a large-scale integrated circuit.

Further, according to the present invention, the basic cell has a symmetrical configuration, and mirror inversion arrangement can be realized during logic wiring, which has the effect of improving wiring efficiency.

[Brief explanation of the drawing]

FIG. 1 is a basic cell configuration diagram showing an embodiment of the semiconductor integrated circuit device of the present invention. FIG. 2 is a two-man N10R circuit diagram showing an embodiment of the semiconductor integrated circuit device of the present invention. FIG. 3 is a layout pattern diagram for realizing FIG. 2. FIG. 4 is a four-person NAND circuit diagram showing an embodiment of the semiconductor integrated circuit device of the present invention. FIG. 5 is a layout pattern diagram for realizing FIG. 4. FIG. 6 is a totem pole output type two-manpower NAND circuit diagram showing an embodiment of the semiconductor integrated circuit device of the present invention. FIG. 7 is a layout pattern diagram of a totem pole output type two-input NOR circuit showing an embodiment of the semiconductor integrated circuit device of the present invention. 2.3,8,9,19,20,21.22゜55.54
．． 44.45-=・PMO84,5,10,11,25
,24,25゜26.55,36,46.47...
・・NMO87, 15, 2B, 57.38.4B, 49
・・・・・・・・・・・・ NPN 6.12, 27, 39, 40, 50, 51...
...Resistance 14.15, 29, 30, 51. ! 52,41°42・
... Input terminal 200 ... Power supply terminal 201 ... Fixed potential terminal 16.35.45 ... Output terminal 17 ...
・Contact hole 18・・・・・・Pier hole or above Applicant Seiko Epson Co., Ltd. 1 mountain '1.31 yen

Claims (6)

[Claims] (1) In a master slice type gate array LSI, basic cells that make up various logic gates drive bipolar transistors and bipolar transistors that make up the output stage of the logic gates, and CM@O@ takes logic.
A semiconductor integrated circuit device comprising an S transistor. (2) The basic cells include a first P-type field effect transistor whose gate is connected to the first input terminal, a first N-type field effect transistor whose gate is connected to the input terminal, and a first P-type field effect transistor whose gate is connected to the input terminal. A second P-type field effect transistor whose gate is connected to the second input terminal, a second N-type field effect transistor whose gate is connected to the input terminal, and each of the base, collector, and emitter terminals are each wired in a programmable manner. A semiconductor integrated circuit device according to claim 1, comprising a first NPN bipolar transistor. (3) The base terminal of the first NPN bipolar transistor in the first basic cell is connected to the drain terminal of the logic P-type field effect transistor, the collector terminal is connected to the power supply terminal, and the emitter terminal is connected to the output terminal. Claim 1 or 2 characterized in that
The semiconductor integrated circuit device described in . (4) The base terminal of the second NPN bipolar transistor in the second basic cell is connected to the source terminal of the logic N-type field effect transistor, the collector terminal is connected to the output terminal, and the emitter terminal is connected to the fixed potential terminal. A semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is connected. (5) The emitter terminal of the first NPN bipolar transistor and the collector terminal of the second NPN bipolar transistor are connected to the same output terminal to form a totem pole connection. The semiconductor integrated circuit device described in item 2. (6) The semiconductor integrated circuit device according to claim 1 or 2, wherein a resistor is connected between the base terminal and emitter terminal of the NPN bipolar transistor.