JPH01255275A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a MOSFET excellent in noise index which can be operated at a high speed at high frequencies without deteriorating cut-off characteristics when the size of a gate electrode is reduced by making the depth of a junction of a drain region larger than that of the junction of a source region. CONSTITUTION:In an insulated gate type field effect transistor, the depth of the junction of a region which extends at least to the part directly under a gate electrode 13 of a drain region 15 is increased than that which extends to the part directly under the electrode 13 of a source region 16. For example, a gate oxide film 12 is formed on a P-type silicon substrate 11, and the gate electrode 13 made of W is formed thereon. Then, the surface is covered with a photoresist, the part at the drain side from substantially the center on the electrode 13 is selectively opened, and P<+> is ion implanted by 150keV of acceleration voltage and approx. 1X10<13>cm<-2> of dose. Then, the photoresist is removed, P<+> is ion implanted to the whole surface by 50keV of acceleration voltage and approx. 2X10<14>cm<-2> of dose to form drain and source regions 15, 16 having different junction depths.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including an insulated gate field effect transistor.

[Conventional technology]

Conventionally, in this type of insulated gate field effect transistor (hereinafter referred to as MO3FET), the junction depths of source and drain regions 55 and 56 were equal, as shown in FIG.

[Problem to be solved by the invention]

The conventional MOSFET described above has the following drawbacks. M
In order to operate an OSFET at high frequency and high speed, it is necessary to try to reduce the size of the device, especially the gate length. If the gate length is further reduced, the short channel effect will cause the MOS
Since the cutoff characteristic of the FET deteriorates, in order to prevent this, the junction of the source/drain region directly under the gate electrode must be made shallow. On the other hand, when the drain junction is made shallower, in actual operation, the drain is positively biased with respect to the substrate, and the electric field distribution in the channel portion directly under the gate electrode becomes extremely high near the drain junction.

Therefore, the scattering of carriers traveling in the channel section increases and the noise figure of the amplifier deteriorates.

Therefore, with conventional MOSFETs, it is difficult to reduce the gate length and realize a device with excellent high frequency characteristics.

[Means to solve the problem]

In the MOSFET of the present invention, the junction in the node and drain regions (the junction in the source region) is more clean.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

FIGS. 2 to 4 are longitudinal cross-sectional views of the device following the manufacturing process order. The steps will be explained below in order. In Figure 2, P
A gate oxide film 22 is formed on a mold silicon substrate 21, and a gate electrode 23 is provided thereon.

In this case, W is used as the material for the gate electrode 23. Next, in FIG. 3, the surface is covered with a photoresist 34, a hole is selectively opened approximately at the center of the gate electrode 23 on the drain side, and an n-type diffusion layer 35 is formed by ion implantation.

The conditions for ion implantation were to use 31F+ as the ion species, an acceleration voltage of 150 KeV, and a dose of I x 10 ''cm-2.
If the junction depth is 0.3μm, the layer resistance will be 1500Ω/
It will be about the size of your mouth. Next, in FIG. 4, the photoresist is removed and a shallow n-type diffusion layer 46. is formed by ion implantation on the entire surface.
Form 47. The conditions for ion implantation are 31 for the ion species.
Using P+, the dose was 2X at an acceleration voltage of 50 K e V.
When the thickness is about 1014 cm-2, the layer resistance at a junction depth of 0.15 μm is about 300Ω/hole. Finally, returning to FIG. 1, aluminum electrodes 18 are formed to take out the source and drain regions.

According to this example, the MOSFET obtained in this way has a high gm value without deteriorating its cutoff characteristics even if the gate electrode size becomes 2 μm or less, and it is possible to obtain a low noise figure by searching for a drain side junction. It is possible.

FIG. 6 shows P-chMO8FE as another embodiment of the present invention.
A vertical cross-sectional view of T is shown. In this embodiment, an n-type silicon substrate 61 is used as the substrate, and IIB+ is used as the ion species to form the source/drain regions, but the other steps are the same as in the first embodiment to form a P-ch M OS.
You can get FET.

〔Effect of the invention〕

As explained above, the present invention makes the depth of the junction in the drain region larger than that in the source region, so that when the dimensions of the gate electrode are reduced, the cutoff characteristics are not deteriorated and the noise figure is excellent. A MOSFET capable of high frequency and high speed operation can be realized.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a MOSFET according to an embodiment of the present invention, and FIGS. 2 to 4 are MOSFETs according to an embodiment of the present invention.
A vertical cross-sectional view during the manufacturing process of ET, Figure 5 is a conventional MOSF
A vertical cross-sectional view of ET, FIG. 6 is a MOS of another embodiment of the present invention.
FIG. 3 is a longitudinal cross-sectional view of the FET. 11, 21.31.41.51.61...Silicon substrate, 12.22.32.42.52.62...
...gate oxide film, 13.23.33.43.53.
63... Gate electrode 4iL34... Photoresist, 15.35.45°47, 55.65...
...Drain region, 16,46°56.66...
...Source region, 18,58.68...Aluminum electrode. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] 1. A semiconductor device in an insulated gate field effect transistor, wherein a junction depth of at least a region of the drain region extending directly below the gate electrode is greater than a junction depth of the source region extending directly below the gate electrode.