JPH01255254A - Packaging method for semiconductor integrated circuit - Google Patents

Packaging method for semiconductor integrated circuit

Info

Publication number
JPH01255254A
JPH01255254A JP8368488A JP8368488A JPH01255254A JP H01255254 A JPH01255254 A JP H01255254A JP 8368488 A JP8368488 A JP 8368488A JP 8368488 A JP8368488 A JP 8368488A JP H01255254 A JPH01255254 A JP H01255254A
Authority
JP
Japan
Prior art keywords
integrated circuit
noise
semiconductor integrated
electronic device
electromagnetic wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8368488A
Other languages
Japanese (ja)
Inventor
Yoshinori Yamamoto
山本 美範
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP8368488A priority Critical patent/JPH01255254A/en
Publication of JPH01255254A publication Critical patent/JPH01255254A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To attenuate an electromagnetic noise generated from an electronic device to the degree not to become a problem in practice without an EMI filter and a shielding case by adding a shielding function to a package itself of an integrated circuit. CONSTITUTION:In an electronic device using a digital signal, electromagnetic wave failure removing means is provided at the package itself of a semiconductor integrated circuit used in the device. For example, a whole DIP is molded with a conductive molding material 42, and the material 42, a lead terminal 41, leads and the integrated circuit are insulated thereamong by an insulating film 43. The material 42 is brought into contact with a tab securing lead, which is connected to a GND. Thus, an electromagnetic wave noise can be attenuated to the degree not to become a problem in practice without an EMI filter and a shielding case. As a result, its component cost is reduced, the mounting efficiency of a board is improved, its assembling cost is decreased, and the device can be further reduced in size and weight.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路のパッケージ方法に係り、よ
り詳しくは電磁波障害技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packaging method for semiconductor integrated circuits, and more particularly to electromagnetic interference technology.

〔発明の概要〕[Summary of the invention]

近年電子機器の増加により、該電子機器から発生する電
磁波ノイズ(ELEOTRO−MAGNFJT工C−工
NTF:RFAGE以下FXMIと称す)が大きな問題
となりてきている。゛この為日本ではVaC工(情報処
理装置など電磁波障害自主規制協議会)で自主規制が始
まっている。その結果各メーカーは、集積回路の外部に
KMエフイルターを取り付けたり、シールドケースで遮
弊する等の対策をとっている。
In recent years, with the increase in the number of electronic devices, electromagnetic noise (ELEOTRO-MAGNFJT Engineering C-Engineering NTF: RFAGE, hereinafter referred to as FXMI) generated from the electronic devices has become a major problem.゛For this reason, in Japan, the VaC (Voluntary Control Council for Electromagnetic Interference from Information Processing Equipment) has begun to implement voluntary regulations. As a result, manufacturers are taking measures such as installing KM filters on the outside of integrated circuits and shielding them with shield cases.

本発明は、前述の問題を解決する為、電磁波ノイズの発
生源である集積回路のパッケージ自体を導電性モールド
材を用いる事により、電磁波ノイズを遮弊し、他の半導
体集積回路、更には他の電子機器に対する電磁波障害を
防ぐ事が可能となり、更には電子機器のコストダウンを
計ることがでる。
In order to solve the above-mentioned problem, the present invention uses a conductive molding material for the package itself of the integrated circuit, which is the source of electromagnetic noise, to block electromagnetic noise, and to protect the integrated circuit from other semiconductor integrated circuits and other devices. It becomes possible to prevent electromagnetic wave interference to electronic devices, and furthermore, it is possible to reduce the cost of electronic devices.

〔従来の技術〕[Conventional technology]

集積回路単体でKMI対策を講じる事が不可の為、EM
エフイルターを外付けしたり、或は電子機器を導体で遮
弊し電磁波ノイズが゛外部に出るのを防ぐしか方法はな
かった。
Since it is impossible to take KMI measures for a single integrated circuit, EM
The only way to prevent electromagnetic noise from escaping was by attaching an external filter or shielding electronic equipment with a conductor.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

最近電子機器の増加により、該電子機器から発生する電
磁波ノイズが大きな問題となってきている。特にディジ
タル信号を用いた電子機器は広い周波数にわたりノイズ
が発生する為、ディジタル機器のノイズ問題がクローズ
アップされている。
With the recent increase in the number of electronic devices, electromagnetic noise generated from the electronic devices has become a major problem. In particular, since electronic devices that use digital signals generate noise over a wide range of frequencies, the problem of noise in digital devices is attracting attention.

該高周波ノイズは、他の集積回路や電子機器の機能を防
害する可能性がある為、電子機器メーカーはKMエフイ
ルターや、シールドケースを用いてノイズ対策を講じて
いる。その為、部品コストの上昇、基板の実装効率の低
下、及び組立てコストが上昇し、更には電子機器の大型
化を伴うことになった。そこで本発明の目的は、上記の
問題点を解決する事にある。
Since the high frequency noise may damage the functions of other integrated circuits and electronic devices, electronic device manufacturers take noise countermeasures by using KM filters and shield cases. As a result, component costs have increased, board mounting efficiency has decreased, assembly costs have increased, and electronic devices have also become larger. Therefore, an object of the present invention is to solve the above problems.

〔課題を解決するための手段〕[Means to solve the problem]

前項問題を解決する為本発明により、集積回路のパッケ
ージ自体にシールド機能を付加する事により、電子機器
のトータルコストの低減を計ることができる。
In order to solve the above problem, the present invention adds a shielding function to the integrated circuit package itself, thereby making it possible to reduce the total cost of electronic equipment.

〔実施例〕〔Example〕

以下に本発明の実施例を図面に従って説明する。第1図
はディジタル電子機器の概念図であり、電磁波ノイズの
発生経路を示している。第2図は各種’td子機器にお
いて現在採用されている電磁波ノイズの対策例を示す概
念図であり、ノイズが発生する危険性のある全ての端子
にKMIフィルターを挿入し、更に集檀回路全体を導体
でシールドしている様子を示している。第3図はD工P
と呼ばれている集積回路のパッケージ図面であり、(α
)は平面図、(b)は側面図、(C)は断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a digital electronic device, showing the generation path of electromagnetic noise. Figure 2 is a conceptual diagram showing an example of electromagnetic noise countermeasures currently adopted in various 'td child devices.KMI filters are inserted into all terminals where there is a risk of noise generation, and the entire collection circuit is This shows how the wire is shielded with a conductor. Figure 3 shows D-engineering P.
It is a package drawing of an integrated circuit called (α
) is a plan view, (b) is a side view, and (C) is a sectional view.

第4図は本発明を示す図面であり、D工P全体を導電性
のモールド材でモールドしたことを示している。導電性
モールド材と、リード端子、リード線、及び集積回路は
、絶縁膜により絶縁されている。また、導電性モールド
材は、タブ固定用リードに接触しており、タブ固定用リ
ードはGNDに接続する。GND電極はノイズ的に安定
した(7NDである必要がある。
FIG. 4 is a drawing showing the present invention, and shows that the entire D-work P is molded with a conductive molding material. The conductive mold material, lead terminals, lead wires, and integrated circuit are insulated by an insulating film. Further, the conductive mold material is in contact with the tab fixing lead, and the tab fixing lead is connected to GND. The GND electrode must be stable in terms of noise (7ND).

以上により集積回路より発生する電磁波ノイズをパッケ
ージングしている導電性モールド材でキャッチし、モー
ルド材と接触しているタブ固定用リードを介してグラン
ド電極に流し出し、ノイズを除去することができる。
As described above, the electromagnetic noise generated by the integrated circuit can be caught by the conductive molding material used in the packaging, and then flowed out to the ground electrode via the tab fixing lead that is in contact with the molding material, thereby eliminating the noise. .

以上説明したように本発明により、電子機器より発生す
る電磁波ノイズを、E Mエフイルター。
As explained above, according to the present invention, electromagnetic wave noise generated from electronic equipment can be filtered out by an EM filter.

及びシールドケースなしで実用上問題にならない程度ま
で減衰させることができる。
And it can be attenuated to a level that poses no problem in practice without a shield case.

〔発明の効果〕〔Effect of the invention〕

本発明により、電磁波ノイズを、EMエフイルター、及
びシールドケースなしで実用上問題にならない程度まで
減衰させることができ、その結果部品コストの低減、基
板の実装効率の向」二、組立てコストの低減、更には機
器の小型化、軽量化が実現できる。
According to the present invention, it is possible to attenuate electromagnetic wave noise to the extent that it does not pose a practical problem without using an EM filter or a shielding case.As a result, component costs are reduced, board mounting efficiency is improved, and assembly costs are reduced. Moreover, it is possible to make the equipment smaller and lighter.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はディジタル電子機器の概念図であり、1・・・
・・・集積回路、2・・・・・・導体を通過するノイズ
の伝送経路、3・・・・・・空中を飛んでいる電磁波ノ
イズ、4・・・・・・シールドケース 第2図は電子機器における電磁波ノイズ対策を示した概
念図であり、 21・・・・・・集積回路、22・・・・・・EMエフ
イルター、23・・・・・・シールドケース 第6図(α)〜(C)はD工pの外形図であり(α)は
平面図であり、 31・・・・・・リード端子、32・・・・・・モール
ド材(b)は側面図であり、 31・・・・・・リード端子、32・・・・・・モール
ド材(C)は断面図であり、 31・・・・・・リード端子、62・・・・・・モール
ド材である。 第4図(α)〜(C)は本発明を示す図面であり、 (α)は平面図であり、 41・・・・・・リード端子、42・・・・・・導電性
モールド材 is)は側面図であり、 41・・・・・・リード端子、42・・・・・・導電性
モールド材、43・・・・・・リード端子絶縁膜、44
・・・・・・導電性モールド材を覆った保護膜 (C)は断面図であり、 41・・・・・・リード端子、42・・・・・・導電性
モールド材、46・・・・・・リード端子絶縁膜、44
・・・・・・導電性モールド材を覆った保護膜 である。 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上柳雅誉(他1名) オ 1(力 募21刀 (シ2 <C) 操=)画 (b) (こ) 徐牛[η
Figure 1 is a conceptual diagram of a digital electronic device, with 1...
...Integrated circuit, 2...Noise transmission path passing through conductor, 3...Electromagnetic wave noise flying in the air, 4...Shield case Figure 2 shows It is a conceptual diagram showing electromagnetic wave noise countermeasures in electronic equipment, and includes 21... integrated circuit, 22... EM filter, 23... shield case Figure 6 (α). ~ (C) is an external view of D-work p, (α) is a plan view, 31... lead terminal, 32... mold material (b) is a side view, 31...Lead terminal, 32...Mold material (C) is a sectional view, 31...Lead terminal, 62...Mold material. 4 (α) to (C) are drawings showing the present invention, (α) is a plan view, 41... lead terminal, 42... conductive mold material is ) is a side view, 41... Lead terminal, 42... Conductive molding material, 43... Lead terminal insulating film, 44
. . . The protective film (C) covering the conductive molding material is a cross-sectional view. 41 . . . Lead terminal, 42 . . . Conductive molding material, 46 . . . ...Lead terminal insulating film, 44
......A protective film that covers the conductive mold material. Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Masayoshi Kamiyanagi (and 1 other person)

Claims (1)

【特許請求の範囲】[Claims]  デジタル信号を使用する電子機器において、該電子機
器内に使用されている半導体集積回路のパッケージ自体
に電磁波障害除去手段を有する事を特徴とする半導体集
積回路のパッケージ方法。
1. A method for packaging a semiconductor integrated circuit in an electronic device using digital signals, characterized in that the package itself of the semiconductor integrated circuit used in the electronic device has an electromagnetic interference removing means.
JP8368488A 1988-04-05 1988-04-05 Packaging method for semiconductor integrated circuit Pending JPH01255254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8368488A JPH01255254A (en) 1988-04-05 1988-04-05 Packaging method for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8368488A JPH01255254A (en) 1988-04-05 1988-04-05 Packaging method for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH01255254A true JPH01255254A (en) 1989-10-12

Family

ID=13809317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8368488A Pending JPH01255254A (en) 1988-04-05 1988-04-05 Packaging method for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH01255254A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758481A (en) * 1993-08-13 1995-03-03 Nec Corp Semiconductor integrated circuit unit
KR19990001668A (en) * 1997-06-17 1999-01-15 윤종용 Electromagnetic Shielding Semiconductor Package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758481A (en) * 1993-08-13 1995-03-03 Nec Corp Semiconductor integrated circuit unit
KR19990001668A (en) * 1997-06-17 1999-01-15 윤종용 Electromagnetic Shielding Semiconductor Package

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