JPH01254021A - Frequency divider - Google Patents

Abstract

PURPOSE:To attain smooth switching of frequency division period by providing an initializing means initializing the frequency division means by an output of an end point detection means and a latch means storing a period switching signal inputted externally and giving the signal to a multiplexer. CONSTITUTION:With a reference clock given, each frequency stage divides the clock and a multiplexer 5 selects one of them and gives an output. Then an end point detection means 10 detects an end point being the end of the period of an output 10. An end point signal is given at the end of period to activate an initializing means 8 thereby initializing each frequency division stage. Before the end point signal is given, if a strobe for frequency division switching comes from an external software, it is stored in a latch 7 to switch the multiplexer 5 when the end point signal arrives. Thus, smooth frequency division period is switched.

Description

[Detailed description of the invention] [Field of application in the cement industry] This invention relates to a frequency dividing device.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional frequency dividing means. In the figure, 11 to 141 are frequency dividing stages, and 15) is a frequency dividing stage +lI to
(Multiplexer connected to 41, 1i (Id circuit, 191 is a frequency division stage) 11-141 A reference clock given to VC, (101 is a frequency division output, uuh is a minute period switching signal issued by an external software.

In the above conventional software-based frequency divider circuit, each frequency divider stage...~(
4) is the frequency divided output rack multiplexer plow 1 rotation II! I
, 51 selects only one frequency-divided output (1α).

[Problem that the invention seeks to solve]

In the conventional frequency divider, 1 multiplexer control bit 1 directly controls the multiplexer control circuit, 1llal.

Therefore, the timing of switching the multiplexer depends largely on the external strobe on the software side. So minute 8
Since the 8th period is switched, abnormal synchronization like 1J21 may occur.

This invention was made to solve the above-mentioned problems. 1. Smooth Fi! The object of the present invention is to obtain a frequency dividing device capable of performing two switchings of the f1 period.

[Means to solve the problem]

The present invention includes endpoint detection means for detecting work/topoints from the output of the frequency division means, initialization means for initializing the frequency division means using the output of the endpoint detection means,
A latch means is provided for storing a synchronization switching signal inputted from the outside and applying this signal to a multiplexer.

[Effect]

The present invention detects an endpoint, uses this endpoint signal to initialize all frequency division stages, and latches a synchronized switching signal input from the outside to perform smooth frequency division switching.

[Implementation sequence of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Figure @1 is a block diagram of a frequency dividing circuit according to an embodiment of the present invention. The same reference numerals as in FIG. 8 refer to all corresponding parts, and the explanation thereof will be omitted. As is clear from FIG. 1 of this embodiment d, (61 is an end point detection means connected to ~14Hc in each frequency division stage and detects the end point of its output.

(8) is connected to the end point 414 output means 161K, and each frequency division stage 111 to (4
). (7) is composed of a latch circuit for storing a strobe signal for changing the frequency division period from external software.

Next, the operation of the above embodiment will be explained with reference to FIGS. 1 and 2.

When the reference clock is input to the frequency divider, each frequency division is 1 to 1.
Klofke division by 41. Among them, multiplexer 6
) selects one and outputs it. At that time, the end point which is the end of the cycle of the end point detection means (output 110 by 61) is detected.

If it is true at the end of the judgment, end point No. 15 is output and the initialization means (8) is activated to initialize each frequency division stage. Also, if a strobe for frequency division switching is received from external software before the endpoint signal is output, it is held in the latch 17), and when the endpoint signal is input, it is sent to the multiplexer 61i. Make it feel sharp.

As described above, in this embodiment, an end point detection device (6) for detecting the end of Fi synchronization, an initialization means (8) for initializing each frequency division stage, and a device for holding a strobe signal are used. Since the latch metal is provided, it is possible to smoothly change the division cycle without any abnormal @ period. Therefore, since there is no need for the software to determine the switching timing, the load placed on the software can be reduced.

It should be noted that in the above-mentioned implementation series, a case in which four frequency division stages are provided will be described, but the number of frequency division stages may be any number.

〔Effect of the invention〕

As described above, according to the present invention, the endpoint detection means detects the endpoint from the output of the frequency division means, the initialization means initializes the frequency division means by the output of the endpoint detection means, and the endpoint detection means detects the endpoint from the output of the frequency division means. Since launch means is provided for storing the synchronization switching signal and applying it to the ig'i multiplexer, it is possible to obtain a frequency dividing device capable of smoothly switching the frequency dividing ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frequency dividing device according to an embodiment of the present invention, and FIG. 2 shows signals of the frequency dividing device. ;ll-14
1 is the frequency division stage +5) is the multiplexer I (17 means, 16
) is the endpoint detection means, (7) is the latch means, (
8) is an initialization means. In addition, the same reference numeral a l1=itJ − in the figure, or O indicating the corresponding part.

Claims (1)

[Claims] A frequency dividing means consisting of a plurality of different frequency dividing circuits, a multiplexer connected to the frequency dividing means, an end point detecting means for detecting the end of a cycle from the output of the frequency dividing means, and an output of the end point detecting means. A frequency dividing device comprising: initializing means for initializing the frequency dividing means; and latch means for storing a period switching signal inputted from the outside and applying this signal to the multiplexer.