JPH01253294A - Printed wiring substrate and manufacture thereof - Google Patents

Printed wiring substrate and manufacture thereof

Info

Publication number
JPH01253294A
JPH01253294A JP8110988A JP8110988A JPH01253294A JP H01253294 A JPH01253294 A JP H01253294A JP 8110988 A JP8110988 A JP 8110988A JP 8110988 A JP8110988 A JP 8110988A JP H01253294 A JPH01253294 A JP H01253294A
Authority
JP
Japan
Prior art keywords
plating
solder
printed wiring
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8110988A
Other languages
Japanese (ja)
Other versions
JP2655870B2 (en
Inventor
Hiroshi Tsukagoshi
洋 塚越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Motor Co Ltd
Original Assignee
Yamaha Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Motor Co Ltd filed Critical Yamaha Motor Co Ltd
Priority to JP63081109A priority Critical patent/JP2655870B2/en
Publication of JPH01253294A publication Critical patent/JPH01253294A/en
Application granted granted Critical
Publication of JP2655870B2 publication Critical patent/JP2655870B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE:To improve the solder in permeability and increase its adhesive area so as to improve its solderability by a method wherein a wiring pattern of a printed wiring board is formed of a plating film mainly composed of plating particles whose diameters are 3-10mum. CONSTITUTION:A first and a second Cu plating layer, 8 and 9, are formed in lamination on a base board 2 and moreover a solder layer 10 is formed thereon for the formation of a wiring circuit section 3. A connecting circuit section 4 is structured in such a manner that the first and the second Cu plating layer, 8 and 9, are formed on an inside circumference of a through-hole 13 provided to the board 2 penetrating through it and a solder layer 10 is formed on the inner face of the through-hole 13. The second Cu plating layer 9 is formed of plating particles whose diameters are 3-10mum. Then, interfaces between the plating particles become gaps into which solder permeates easily. By these processes, the solder is improved in permeability and increased in an adhesive area, so that the solderability can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は絶縁性ベース基板上に金属配線をめっきにより
パターン形成したプリント配線基板及びその製造方法に
関し、特にスルーホールの内周面に形成されためっき膜
あるいは基板表面上のパターンめっき膜に外部接続端子
等をはんだ付けする場合の、はんだ付は性の改善に関す
る。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a printed wiring board in which metal wiring is patterned by plating on an insulating base substrate, and a method for manufacturing the same, and in particular to a printed wiring board formed on the inner peripheral surface of a through hole. Soldering is related to improving properties when external connection terminals and the like are soldered to a plating film or a pattern plating film on the surface of a substrate.

〔従来の技術〕[Conventional technology]

プリント配線基板において、ベース基板上に金属配線を
パターン形成したり、スルーホール内周面にめっき膜を
形成したりする方法としては、従来、例えばいわゆるア
ディティブ法、サブトラクティブ法がある。アディティ
ブ法は、スルーホール等が形成された絶縁性ベース基板
上にめっきレジスト膜をパターン形成し、この状態で無
電解めっきすることにより配線パターンを付加形成する
方法である。また、サブトラクティブ法は、銅張f1層
板からなるベース基板に、めっきレジスト膜をパターン
形成した後電気めっきを施し、しかる後下地の銅板の不
要部分をエツチングにより除去するようにした方法であ
る。
In printed wiring boards, conventional methods for patterning metal wiring on a base substrate and forming a plating film on the inner peripheral surface of a through hole include, for example, the so-called additive method and subtractive method. The additive method is a method in which a plating resist film is patterned on an insulating base substrate in which through holes etc. are formed, and a wiring pattern is additionally formed by electroless plating in this state. The subtractive method is a method in which a plating resist film is patterned on a base substrate made of a copper-clad F1 layer board, electroplated, and then unnecessary portions of the underlying copper plate are removed by etching. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上記プリント配線基板を使用する場合、配線
パターンに外部回路との接続端子をはんだ付は接続し、
あるいは搭載部品の端子を基板のスルーホールに挿入し
てはんだ付は接続することとなる。従って当然ながら、
配線パターン等のめっき膜のはんだ付は性が高いことが
要請される。
By the way, when using the above printed wiring board, connect the connection terminal with the external circuit to the wiring pattern by soldering.
Alternatively, the terminals of the mounted components are inserted into the through holes of the board and the connections are made by soldering. Therefore, of course,
High soldering properties of plating films such as wiring patterns are required.

また、スルーホール部分のはんだ付けにおいては、挿入
端子とスルーホール内面のめっき膜との間にはんだが充
分に浸透することが要請される。ところが、上記従来の
アディティブ法、サブトラクティブ法で形成された配線
パターンでは、はんだ付は性において必ずしも満足でき
るものではなく、改善の余地がある。
Furthermore, when soldering the through-hole portion, it is required that the solder sufficiently penetrate between the insertion terminal and the plating film on the inner surface of the through-hole. However, with the wiring patterns formed by the conventional additive method or subtractive method, the soldering performance is not necessarily satisfactory, and there is room for improvement.

本発明は、上記従来の要請に鑑み、はんだ付は性を大幅
に改善できるプリント配線基板及びその製造方法を提供
することを目的としている。
SUMMARY OF THE INVENTION In view of the above-mentioned conventional demands, the present invention aims to provide a printed wiring board and a method for manufacturing the same, which can significantly improve soldering properties.

〔問題点を解決するための手段〕[Means for solving problems]

本件発明者は、上記はんだ付は性の改善を図るため、配
線パターンの金属組織を観察した結果、該パターンを構
成するめっき粒子の直径がはんだ付は性を決定している
点を見出した。そしてこのめっき粒子の直径を所定範囲
に規制しつつ配線パターンを形成すれば上記目的を達成
できることに想到して本願発明を完成した。ここで言う
めっき粒子の直径とは、配線パターンを電子顕微鏡等で
基板と直角方向から観察した場合に認められる凸状粒子
の、基板表面と平行な面内における直径をいう。
In order to improve the solderability, the inventor of the present invention observed the metal structure of the wiring pattern and found that the diameter of the plating particles constituting the pattern determines the solderability. The present invention was completed based on the idea that the above object could be achieved by forming a wiring pattern while regulating the diameter of the plating particles within a predetermined range. The diameter of the plating particles referred to herein refers to the diameter of convex particles observed in a plane parallel to the substrate surface when the wiring pattern is observed from a direction perpendicular to the substrate using an electron microscope or the like.

そこで本願の特定発明は、ベース基板上にめっき膜から
なる配線パターンを形成してなるプリント配線基板にお
いて、上記配線パターンを構成するめっき粒子の大部分
が、基板表面と平行な面内における直径3〜10μmを
有していることを特徴としている。
Therefore, the specific invention of the present application provides a printed wiring board in which a wiring pattern made of a plating film is formed on a base substrate, in which most of the plating particles constituting the wiring pattern have a diameter of 3 in a plane parallel to the substrate surface. It is characterized by having a diameter of ~10 μm.

また、本願の関連発明は、プリント配線基板の製造方法
において、ベース基板を電極と対向するようにめっき液
中に浸漬するとともに、該基板表面に沿ってめっき液を
流動させながら電気めっきを行うことによりめっき粒子
を直径3〜10μmにすることを特徴としている。
Further, a related invention of the present application is a method for manufacturing a printed wiring board, in which a base substrate is immersed in a plating solution so as to face an electrode, and electroplating is performed while the plating solution is flowing along the surface of the substrate. It is characterized in that the plated particles are made to have a diameter of 3 to 10 μm.

本発明におけるめっき粒子とは、上述のように、配線パ
ターンを構成するめっき膜の表面状態を電子顕微鏡等に
より観察した場合に認められるもので、表面の凹凸を構
成する粒状単位をいう、このめっき粒子の直径は該粒状
単位を平面から見た場合の径であるが、この粒径の測定
にあたっては、例えば、所定の長さ9N域に認められる
粒子数をカウントし、このカウント数で上記所定長さを
割り、さらにそのときの倍率で割ることによって求める
As mentioned above, the plating particles in the present invention refer to particles that are observed when the surface condition of the plating film constituting the wiring pattern is observed using an electron microscope, etc. The diameter of a particle is the diameter when the granular unit is viewed from a plane, but when measuring this particle size, for example, the number of particles observed in a predetermined length region of 9N is counted, and this count is used to calculate the above-mentioned predetermined number. It is calculated by dividing the length and then dividing by the current magnification.

まず、本願発明において、めっき粒子径を3〜10μm
に限定したのは、以下の理由による。
First, in the present invention, the plating particle size is 3 to 10 μm.
The reason for this limitation is as follows.

即ち、本発明者の実験により、粒子径3μm未満及び1
0μ鋼を越える場合は、はんだ付は性の向上効果が得ら
れず、3〜10μmにした場合にのみはんだ付は性が向
上することが判明したからであり、より好ましくは粒子
径5μm程度がよい。
That is, according to the inventor's experiments, particle diameters of less than 3 μm and 1
This is because it has been found that when the particle size exceeds 0 μm, the effect of improving soldering properties cannot be obtained, and that the soldering properties are improved only when the particle size is 3 to 10 μm. More preferably, the particle size is about 5 μm. good.

はんだ付は性を向上させるには、めっき膜を構成するめ
っき粒子同士の境界部分に、はんだが容易に浸透し、は
んだとめっき膜との接着面積を増大できることが重要で
あると考えられる。しかしながら粒径が3μl以下の場
合は、めっき膜表面があまりに平滑となり、粒子同士の
境界部にはんだが浸透するための凹部がほとんど存在せ
ず、その結果上述のようにはんだ付は性を向上できない
ものと考えられる。一方、粒子径が10μmを越えると
一定面積における粒子同士の境界数がそれだけ減少し、
そのためはんだの接着面積が充分でなく、結局この場合
もはんだ付は性を改善できないものと考えられる。
In order to improve soldering properties, it is considered important that the solder easily penetrates into the boundaries between the plating particles that make up the plating film, and that the adhesion area between the solder and the plating film can be increased. However, when the particle size is less than 3 μl, the surface of the plating film becomes too smooth, and there are almost no recesses for solder to penetrate at the boundaries between particles, and as a result, soldering properties cannot be improved as described above. considered to be a thing. On the other hand, when the particle size exceeds 10 μm, the number of boundaries between particles in a given area decreases accordingly.
Therefore, the solder bonding area is not sufficient, and it is considered that soldering cannot improve the properties in this case as well.

次に、本願の関連発明において、めっき液を基板表面に
沿って流動させながらめっきを施すようにしたのは、以
下の理由による。
Next, in the related invention of the present application, the reason why plating is performed while the plating solution is flowing along the substrate surface is as follows.

即ち、本発明者等の実験研究により、めっき膜を構成す
るめっき粒子の直径は、めっきの方法如何で決定される
ことが判明したからである。例えば静止状態のめっき液
中に被めっき部材を浸漬して行う電気めっきにより形成
しためっき膜では、上述のめっき粒子はほとんど認めら
れない。一方、無電解めっきにより形成されためっき膜
では、めっき粒子径は25μm以上となる。
That is, through experimental research conducted by the present inventors, it has been found that the diameter of the plating particles constituting the plating film is determined by the plating method. For example, in a plating film formed by electroplating in which a member to be plated is immersed in a stationary plating solution, the above-mentioned plating particles are hardly observed. On the other hand, in a plating film formed by electroless plating, the plating particle size is 25 μm or more.

これに対して、本願の関連発明方法に従って、ベース基
板を電極と対向するようにめっき液中に浸漬し、該めっ
き液を基板表面に沿って流動させながらめっきを行った
場合は、その電流密度、めっき液の流速等を適宜選定す
ることにより3〜10μmの粒子径を存するめっき膜が
得られる。
On the other hand, when plating is performed by immersing the base substrate in a plating solution so as to face the electrodes and flowing the plating solution along the substrate surface according to the related invention method of the present application, the current density By appropriately selecting the flow rate of the plating solution, etc., a plating film having a particle size of 3 to 10 μm can be obtained.

〔作用〕[Effect]

本願の特定発明では、プリント配線基板の配線パターン
を、主として粒子径3〜10μmのめっき粒子からなる
めっき膜で形成したので、めっき粒子同士の境界部がは
んだが浸通し易い隙間となり、つまりはんだの浸透性が
向上してはんだの接着面積が大幅に増大し、その結果は
んだ付は性が大幅に改善される。
In the specific invention of the present application, since the wiring pattern of the printed wiring board is formed with a plating film mainly composed of plating particles with a particle size of 3 to 10 μm, the boundaries between the plating particles become gaps through which solder can easily penetrate. Penetration is improved and the solder adhesion area is greatly increased, resulting in greatly improved soldering properties.

また、本願の関連発明では、めっき液をベース基板に沿
って流動させながら電気めっきを行うようにしたので、
このめっき液の流動速度、電流密度等を適宜選定するこ
とにより、該めっきにより形成されためっき膜のめっき
粒子を3〜10μmの粒子径にすることができる。この
場合、例えばめっき液の流動速度を一定範囲で増大させ
るとめっき粒子の直径が大きくなり、また電流密度を一
定範囲で大きくした場合も直径が大きくなる。このよう
にめっき粒子径を適宜選定できる結果、はんだの浸透性
を向上でき、はんだ付は性を向上できる。
Furthermore, in the related invention of the present application, electroplating is performed while the plating solution is flowing along the base substrate.
By appropriately selecting the flow rate, current density, etc. of this plating solution, the plating particles of the plating film formed by this plating can be made to have a particle size of 3 to 10 μm. In this case, for example, when the flow rate of the plating solution is increased within a certain range, the diameter of the plating particles increases, and when the current density is increased within a certain range, the diameter also becomes large. As a result of being able to appropriately select the plating particle size in this way, solder permeability can be improved and soldering properties can be improved.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例によるプリント配線基板を説
明するための図である。
FIG. 2 is a diagram for explaining a printed wiring board according to an embodiment of the present invention.

図において、1はプリント配線基板であり、これはベー
ス基板2の上、下両面に、配線回路部3゜3を形成する
とともに、該両配線回路部3.3のランド部5同士を接
続回路部4で接続し、さらにランド部5を除いた部分を
耐熱樹脂からなるソルダレジスト6で覆うことによって
構成されている。
In the figure, 1 is a printed wiring board, which forms wiring circuit parts 3.3 on both the upper and lower surfaces of the base board 2, and connects the land parts 5 of both wiring circuit parts 3.3 with each other. The parts 4 are connected to each other, and the parts other than the land parts 5 are covered with a solder resist 6 made of heat-resistant resin.

なお、このソルダレジスト6は外部端子等のはんだ付は
接続時に、はんだがランド部5以外の部分に付着するの
を防止するためのものである。
The purpose of this solder resist 6 is to prevent solder from adhering to parts other than the land portions 5 when soldering external terminals and the like.

上記配線回路部3は、上記ベース基板2上に第1、第2
Cuめっき層8,9を積層形成し、さらにこれの上面に
ハンダ層10を形成して構成されている。また、上記接
続回路部4はベース基板2に貫通形成されたスルーホー
ル13の内周面に第1、第2Cuめっき層8.9を形成
し、これの内面にはんだ層10を形成して構成されてい
る。
The wiring circuit section 3 is provided with first and second circuits on the base substrate 2.
It is constructed by laminating Cu plating layers 8 and 9 and further forming a solder layer 10 on the upper surface thereof. Further, the connection circuit section 4 is constructed by forming first and second Cu plating layers 8.9 on the inner peripheral surface of a through hole 13 formed through the base substrate 2, and forming a solder layer 10 on the inner surface of the first and second Cu plating layers 8.9. has been done.

第3図及び第4図は上記実施例基板1の製造工程におけ
る、第2Cuめっき層9を形成するためのめっき装置を
示す、このめっき装置は、第2CUめっき眉9を形成す
る際に、これを構成するめっき粒子を本発明の粒子径3
〜10μmに形成できるように構成されている。
3 and 4 show a plating apparatus for forming the second Cu plating layer 9 in the manufacturing process of the embodiment substrate 1. The plating particles constituting the particle size 3 of the present invention
The structure is such that it can be formed to a thickness of ~10 μm.

上記めっき装置の全体構成を示す第4図において、この
めっき装置24は、本体部25と、該本体部25に、め
っき液タンク26内の硫酸銅等の酸性鋼めっき液Pを供
給する供給装置27とから構成されている。この供給装
置27は、供給ポンプ28と、供給側ヘッダ29.排出
側ヘッダ30間を連結する第1.第2供給通路31.3
2、第1、第2排出通路33.34と、該各通路に配設
された第1.第2開閉弁35.36、第1.第2流量計
37.38、第1.第2Hff弁39.40とで構成さ
れている。
In FIG. 4 showing the overall configuration of the plating apparatus, the plating apparatus 24 includes a main body 25 and a supply device for supplying an acidic steel plating solution P such as copper sulfate in a plating solution tank 26 to the main body 25. It consists of 27. This supply device 27 includes a supply pump 28 and a supply side header 29 . The first one connects the discharge side headers 30. Second supply passage 31.3
2, first and second discharge passages 33 and 34, and a first discharge passage disposed in each passage. 2nd on-off valve 35.36, 1st. 2nd flow meter 37.38, 1st. It is composed of a second Hff valve 39 and 40.

また、上記本体部25は、第3図に示すように、めっき
室を構成するケーシング43内にめっき電極44.44
を対向配設し、該両電極間に被めっき板を保持する保持
ブラケット45を設けて構成されている。上記めっき電
極44は電源の陽極に、保持ブラケット45は陰極にそ
れぞれ接続されている。上記保持ブラケット45に被め
っき板を装着すると、酸ケーシング43はこの板により
第1゜第2めっき室46.47に区分けされ、これによ
り上記第1供給、排出通路31.33及び第2供給、排
出通路32.34がそれぞれ連通することとなる。
In addition, as shown in FIG.
are arranged facing each other, and a holding bracket 45 for holding the plate to be plated is provided between the two electrodes. The plating electrode 44 is connected to the anode of the power source, and the holding bracket 45 is connected to the cathode. When the plate to be plated is attached to the holding bracket 45, the acid casing 43 is divided into the first and second plating chambers 46, 47 by this plate, whereby the first supply, the discharge passage 31, 33 and the second supply, The discharge passages 32 and 34 will communicate with each other.

次に上記第2図のプリント配線基板1の製造手順につい
て第3図ないし第5図を参照しながら説明する0本実施
例方法は、上述のアディティブ法とサブトラクティブ法
との中間に位置することから、セミアデイティブ法と称
される。
Next, the manufacturing procedure of the printed wiring board 1 shown in FIG. 2 will be explained with reference to FIGS. 3 to 5. The method of this embodiment is located between the above-mentioned additive method and subtractive method. Therefore, it is called a semi-additive method.

■ 例えば、ガラス繊維入りエポキシ樹脂層を約10層
積層してプレス成形し、さらに銅めっきの密着力向上用
接着剤を塗布してなるベース基板2を準備し、所定位置
にスルーホール13を貫通形成する(第5図(al)。
■ For example, prepare the base substrate 2 by laminating and press-molding about 10 layers of epoxy resin containing glass fibers, and then applying an adhesive to improve the adhesion of copper plating, and penetrate the through holes 13 at predetermined positions. (Fig. 5(al)).

■ 該ベース基板2にめっき前処理としての活性化処理
を施した後、無電解めっきにより、該ベース基板2の両
表面及びスルーホール13の内周面に第1Cuめっき層
8を2〜5μ鶏の厚さに形成し、該ベース基板2に導電
性を与える(第5図(bi)。
(2) After the base substrate 2 is activated as a pre-plating treatment, a first Cu plating layer 8 of 2 to 5 μm is coated on both surfaces of the base substrate 2 and the inner peripheral surface of the through hole 13 by electroless plating. (FIG. 5(bi)).

■ 上記容筒1Cuめっき層8上に、怒光性ドライフィ
ルムを熱圧着し、さらに上記配線回路部3に対応した形
状のマスクを密着して露光、現像する。これによりパタ
ーン溝開口16を有するめっきレジスト膜15で覆われ
ためっきレジスト基板18が得られる(第5図tel)
(2) A photosensitive dry film is thermocompression bonded onto the Cu plating layer 8 of the container 1, and a mask having a shape corresponding to the wiring circuit section 3 is closely attached to the film, followed by exposure and development. As a result, a plating resist substrate 18 covered with a plating resist film 15 having patterned groove openings 16 is obtained (tel in FIG. 5).
.

■ 次に上記めっき装置24により、上記めっきレジス
ト基板1日に上記第2Cuめっき層9を形成する。この
場合先ず、めっきレジスト基板18をケーシング43内
の保持ブラケット45に装着し、循環ポンプ28を運転
するとともに、めっき用電源をオンする。するとめっき
液Pが第1゜第2供給通路31.32からケーシング4
3内に供給され、めっきレジスト基板18の両表面に沿
って流動し、該基板18のパターン開口16から露出し
ている部分に第2Cuめっき層9が形成される。またこ
のとき、第1開閉弁35の開度を第2開閉弁36より大
きく設定する。これにより、ケーシング43内の第1め
っき室46の流速F1が第2めっき室47の流速F2よ
り高くなり、かつ第1めっき室46例の圧力が高くなる
。そのためめっき液の一部は第1めっき室46からスル
ーホール13内を通って第2めっき室47内に流動しく
矢印F3参照)、その結果、スルーホール13の第1C
uめっき層8上にも第2めっき1!9が確実に形成され
ることとなる。(第5図(d))。
(2) Next, the second Cu plating layer 9 is formed on the plating resist substrate by the plating apparatus 24 on the first day. In this case, first, the plating resist substrate 18 is mounted on the holding bracket 45 inside the casing 43, the circulation pump 28 is operated, and the plating power source is turned on. Then, the plating solution P is supplied to the casing 4 from the first and second supply passages 31 and 32.
The Cu plating layer 9 is supplied into the plating resist substrate 18 and flows along both surfaces of the plating resist substrate 18 to form a second Cu plating layer 9 on the portions of the substrate 18 exposed from the pattern openings 16. Further, at this time, the opening degree of the first on-off valve 35 is set to be larger than that of the second on-off valve 36. As a result, the flow rate F1 in the first plating chamber 46 in the casing 43 becomes higher than the flow rate F2 in the second plating chamber 47, and the pressure in the first plating chamber 46 becomes higher. Therefore, a part of the plating solution flows from the first plating chamber 46 through the through hole 13 into the second plating chamber 47 (see arrow F3).
The second plating 1!9 is also reliably formed on the u plating layer 8. (Figure 5(d)).

■ そして上記第1.第2Cuめっき層8.9が形成さ
れた上記基板を電解はんだめっきすることにより、第2
Cuめっき層9上に、後工程で該めっき1)9がエツチ
ングされるのを防止するためのはんだ1)10を形成し
く第5図18))、この基板をアルカリ液からなる剥離
液に浸漬し、上記めっきレジスト膜15を剥離除去し、
さらにエツチング液に浸漬する。すると、両表面に第1
.第2CUめっき層8.9及びはんだ層10からなる配
線回路部3が、スルーホール13の内周面に配線回路部
3と同様の構成の接続回路部4がそれぞれ形成される(
第5図ff))。
■ And the above 1. The second Cu plating layer 8.9 is formed by electrolytic solder plating on the substrate on which the second Cu plating layer 8.9 is formed.
To form a solder 1) 10 on the Cu plating layer 9 in order to prevent the plating 1) 9 from being etched in a later process, the substrate is immersed in a stripping solution consisting of an alkaline solution. Then, the plating resist film 15 is peeled off and removed.
Furthermore, it is immersed in an etching solution. Then, the first
.. A wiring circuit section 3 consisting of a second CU plating layer 8.9 and a solder layer 10 is formed on the inner peripheral surface of the through hole 13, and a connection circuit section 4 having the same configuration as the wiring circuit section 3 is formed (
Figure 5ff)).

■ 最後に上記はんだ層10が溶融して第1゜第2Cu
めっき層8,9を覆うように該基板全体を加熱しく第5
図(沿)、接続用ランド部5部分を除いてソルダレジス
ト6を圧着形成する(第5図(h))。このようにして
、第2図に示すプリント配線基板1が製造される。
■ Finally, the solder layer 10 is melted to form the first and second Cu layers.
The entire substrate is heated to cover the plating layers 8 and 9.
As shown in the figure (along side), solder resist 6 is crimped and formed except for the connection land portion 5 (FIG. 5(h)). In this way, the printed wiring board 1 shown in FIG. 2 is manufactured.

第1図tag、 (blは、上述の方法で製造された本
実施例のプリント配線基板1のスルーホール13におけ
る、第2Cuめっき層9のめっき粒子の状態をを示す電
子顕微鏡写真である。また第8図(a)。
FIG. 1 (tag and bl) are electron micrographs showing the state of the plating particles of the second Cu plating layer 9 in the through holes 13 of the printed wiring board 1 of this example manufactured by the method described above. Figure 8(a).

世)は、上記第2Cuめっき層9部分を、めっき液を静
止させて行う通常の電気めっきによって形成した場合の
、該めっき層9の電子顕微鏡写真であり、第9図(a)
、 (biは、第1.第2Cuめっき層を無電解めっき
によって連続して形成した場合の、該めっき層の電子顕
微鏡写真である。
Figure 9(a) is an electron micrograph of the second Cu plated layer 9 when the second Cu plated layer 9 is formed by ordinary electroplating with the plating solution stationary.
, (bi is an electron micrograph of the first and second Cu plating layers formed successively by electroless plating.

これらの写真からも明らかなように、本実施例方法で形
成しためっき膜のめっき粒子は、3〜10μmの粒子径
を有するのに対し、静止めっき液による場合は、倍率を
1000倍(第8図(al) 、5000倍(第8図(
b))にしてもめっき粒子はほとんど認められず、また
、無電解めっきによる場合は、25μm以上の大きなめ
っき粒子により形成されていることがわかる。
As is clear from these photographs, the plating particles of the plating film formed by the method of this example have a particle size of 3 to 10 μm, whereas when using a static plating solution, the magnification was 1000 times (8th Figure (al), 5000x (Figure 8 (
Even in b)), hardly any plated particles were observed, and in the case of electroless plating, it was found that the plated particles were formed by large particles of 25 μm or more.

次に本発明方法に係るめっき膜のはんだ付は性の向上効
果を確認するために行った実験例について説明する。
Next, an example of an experiment conducted in order to confirm the effect of improving soldering properties of a plated film according to the method of the present invention will be described.

裏鋏斑上 本実験例は、スルーホールに電子部品の端子を0000
この状態ではんだ沿面上を移動させるフローはんだ付け
において、はんだがスルーホール内周面と端子との隙間
を上昇する、いわゆるはんだ上り性を調べるためのもの
である。このはんだ上り性は、下記条件による本発明方
法でめっき形成されたCuめっき箔を、所定の前処理を
施した後、第6図に示すように、260℃のはんだ浴層
に15鰭の深さまで浸漬し、一定時間後静かに引き上げ
、付着したはんだ層の長さAを計測することによって調
査した。また、比較のために、静止めっき浴によってめ
っき形成されたCuめっき箔(厚さ35μm)について
も同様に調査した。
In this experiment example, the terminal of an electronic component is inserted into the through hole.
In flow soldering in which the solder moves along the solder surface in this state, the purpose is to examine the so-called solder climbing property in which the solder rises in the gap between the inner peripheral surface of the through hole and the terminal. This solderability is determined by subjecting Cu-plated foil plated using the method of the present invention under the following conditions to a depth of 15 fins in a solder bath layer at 260°C, as shown in Figure 6, after subjecting it to a prescribed pretreatment. The test was conducted by dipping the solder layer in the same position, gently pulling it out after a certain period of time, and measuring the length A of the adhered solder layer. For comparison, a Cu-plated foil (thickness: 35 μm) plated using a static plating bath was also investigated in the same manner.

本発明に係るめっき条件: Cu5Qn 300 g/
 1 、HtSOa 50g/ ’ =残部純水の浴組
成を存するめっき浴を50℃に保持し、これを流動させ
ながら、電流密度20A/dII”でステンレス板上に
電気めっきを行い、このめっき膜を剥離して上記めっき
箔を得た。得られためっき箔は、引張強度32kg/ 
tm”、伸び14%。
Plating conditions according to the present invention: Cu5Qn 300 g/
1. A plating bath containing 50 g/' of HtSOa = remaining pure water was maintained at 50°C, and while flowing, electroplating was performed on a stainless steel plate at a current density of 20 A/dII'', and this plating film was The above plated foil was obtained by peeling.The plated foil obtained had a tensile strength of 32 kg/
tm”, elongation 14%.

厚さ55μmであった。The thickness was 55 μm.

上記はんだ上り性の実験結果を第1表に示し、同表中、
高速めっきは本発明方法を示す、同表からも明らかなよ
うに、本発明方法によるめっき箔では、前処理無し及び
トリクレンで拭いただけの場合は、付着量は充分でない
ものの、トリクレン。
The experimental results of the soldering properties mentioned above are shown in Table 1, and in the same table,
High-speed plating shows the method of the present invention.As is clear from the same table, with the plated foil according to the method of the present invention, when no pretreatment or just wiping with trichlene, the amount of adhesion is not sufficient, but the amount of plating is not sufficient.

フラックスによって前処理した場合は、上記浸漬濶さ全
長に渡ってはんだが付着しており、比較例のものより大
幅に向上している。
When pre-treated with flux, solder adhered to the entire length of the immersion length, which was significantly improved compared to the comparative example.

2放1 本実験は、電子部品を基板上に実装した場合の密着力を
調べるためのものであり、第7図に示すように、本発明
方法によって形成されためっき膜同士又は本発明方法に
よるめっき膜と静止浴によるめっき膜とを2×7鶴の面
積に渡って当接させて仮り止めし、この当接部をはんだ
浴中に浸種し、しかる後画者を50fiZ分の引張速度
で引き剥がし、両者が分離したときの引張荷重を計測し
た。
2 Release 1 This experiment was conducted to examine the adhesion strength when electronic components are mounted on a substrate, and as shown in Fig. The plated film and the plated film formed by the static bath were brought into contact and temporarily fixed over an area of 2 x 7 cranes, this contact part was immersed in the solder bath, and then the painter was applied at a tensile speed of 50 fiZ. The tensile load was measured when the two were separated.

また、比較のために上記静止浴によるめっき膜同士につ
いても同様に計測した。
In addition, for comparison, measurements were made in the same manner for the plating films formed in the above-mentioned static bath.

結果を第2表に示す、同表からも明らかなように、静止
浴めっき膜同士の分離荷重12.6kgに対し、少なく
とも一方のめっき膜が本発明方法による場合(表中、高
速と記す)は、26〜27kgになっており、本発明方
法によるめっき膜では、はんだが両めっき膜間に充分に
浸透し、その結果はんだ付は性が大幅に向上しているこ
とがわかる。
The results are shown in Table 2. As is clear from the table, when at least one of the plating films was formed by the method of the present invention (denoted as high speed in the table), for a separation load of 12.6 kg between the static bath plating films. is 26 to 27 kg, and it can be seen that in the plating film according to the method of the present invention, the solder sufficiently penetrates between the two plating films, and as a result, the soldering properties are greatly improved.

なお、上記実施例では、ベース基板の両面に配線パター
ンが形成され、かつスルーホールが形成されたプリント
配線基板について説明したが、本発明は、基板の一面の
みに配線パターンを形成する場合にも勿論適用できる。
In the above embodiment, a printed wiring board in which a wiring pattern is formed on both sides of the base board and a through hole is formed, but the present invention can also be applied to a case where a wiring pattern is formed only on one side of the board. Of course it can be applied.

〔発明の効果〕 以上のように本願特定発明に係るプリント配線基板によ
れば、配線パターンを主として直径3〜10μmのめっ
き粒子で構成したので、はんだの浸透性が向上してはん
だ付は性を大幅に向上できる効果があり、また、本願関
連発明に係るプリント配線基板の製造方法によれば、め
っき液を流動させながら電気めっきを行うようにしたの
で、上記めっき粒子径3〜10μmを実現できる効果が
ある。
[Effects of the Invention] As described above, according to the printed wiring board according to the specified invention, since the wiring pattern is mainly composed of plating particles with a diameter of 3 to 10 μm, the solder permeability is improved and soldering becomes easier. According to the method for manufacturing a printed wiring board according to the related invention of the present application, since electroplating is performed while the plating solution is flowing, the above-mentioned plating particle size of 3 to 10 μm can be achieved. effective.

第1表 第2表Table 1 Table 2

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(81,(blは、本発明に係る配線パターンの
粒子構造を示す顕微鏡写真、第2図は本発明の一実施例
によるプリント配線基板の斜視図、第3図及び第4図は
本発明方法を実施するためのめっき装置の断面図、全体
構成図、第5図+a)ないし第5図中)は本発明方法の
一実施例を説明するための工程図、第6図及び第7図は
その実験方法を説明するための構成図、第8図fat、
 (bl、第9図(δ)、山)は従来のめっき方法で形
成された配線パターンの粒子構造を示す顕微鏡写真であ
る。 図において、1はプリント配線基板、2はベース基板、
3,4は配線回路部、接続回路部(配線パターン)、4
4は電極、Pはめっき液である。 特許出願人  ヤマハ発動機株式会社 代理人    弁理士 下 市  努 第1図 トーー〜@xi000 10別n 第1図 z、um 第2図 第3図 第5図 第6図 第7図 を 第8図 ’l+l#B 第9図
Figure 1 (81, (bl) is a micrograph showing the grain structure of the wiring pattern according to the present invention, Figure 2 is a perspective view of a printed wiring board according to an embodiment of the present invention, Figures 3 and 4 are A sectional view and an overall configuration diagram of a plating apparatus for carrying out the method of the present invention, FIG. 5+a) to FIG. Figure 7 is a block diagram for explaining the experimental method, Figure 8 is a diagram showing the structure of the experiment.
(bl, FIG. 9(δ), mountain) is a micrograph showing the grain structure of a wiring pattern formed by a conventional plating method. In the figure, 1 is a printed wiring board, 2 is a base board,
3 and 4 are wiring circuit section, connection circuit section (wiring pattern), 4
4 is an electrode, and P is a plating solution. Patent Applicant Yamaha Motor Co., Ltd. Agent Patent Attorney Tsutomu Shimo Ichi Figure 1 To ~ @xi000 10 different n Figure 1 z, um Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 to Figure 8 'l+l#B Figure 9

Claims (2)

【特許請求の範囲】[Claims] (1)ベース基板上にめっき膜からなる配線パターンを
形成したプリント配線基板において、上記配線パターン
が、基板面と平行な面内における粒子径3〜10μmを
有するめっき粒子により主として構成されていることを
特徴とするプリント配線基板。
(1) In a printed wiring board in which a wiring pattern made of a plating film is formed on a base substrate, the wiring pattern is mainly composed of plating particles having a particle diameter of 3 to 10 μm in a plane parallel to the substrate surface. A printed wiring board featuring:
(2)ベース基板上に、基板面と平行な面内における粒
子径3〜10μmを有するめっき粒子により主として構
成された配線パターンを形成するプリント配線基板の製
造方法であって、上記ベース基板を電極と対向するよう
にめっき液に浸漬するとともに、めっき液をベース基板
と電極との間を流動させながら電気めっきを行うことを
特徴とするプリント配線基板の製造方法。
(2) A method for manufacturing a printed wiring board, in which a wiring pattern mainly composed of plating particles having a particle diameter of 3 to 10 μm in a plane parallel to the substrate surface is formed on a base substrate, the base substrate being used as an electrode. A method for producing a printed wiring board, characterized by electroplating the base substrate and electrodes while immersing the substrate in a plating solution so as to face the base substrate and flowing the plating solution between the base substrate and the electrodes.
JP63081109A 1988-03-31 1988-03-31 Printed wiring board and method of manufacturing the same Expired - Fee Related JP2655870B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63081109A JP2655870B2 (en) 1988-03-31 1988-03-31 Printed wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63081109A JP2655870B2 (en) 1988-03-31 1988-03-31 Printed wiring board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH01253294A true JPH01253294A (en) 1989-10-09
JP2655870B2 JP2655870B2 (en) 1997-09-24

Family

ID=13737213

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2655870B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773769A (en) * 1993-09-03 1995-03-17 Ngk Spark Plug Co Ltd External connecting terminal for semi-conductor package and manufacture thereof
JP2011256444A (en) * 2010-06-10 2011-12-22 Sumitomo Bakelite Co Ltd Substrate treating method and substrate treating apparatus
JP2014516121A (en) * 2011-06-09 2014-07-07 ユニヴェルシテ・ドゥ・レンヌ・1 Processing method of felt element percolation by electrodeposition

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60133788A (en) * 1983-12-21 1985-07-16 富士通株式会社 Method of plating printed board
JPS62275750A (en) * 1986-02-21 1987-11-30 株式会社メイコー Manufacture of copper-lined laminated board
JPS62276894A (en) * 1986-02-21 1987-12-01 株式会社メイコー Manufacture of conductor circuit board with through hole

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60133788A (en) * 1983-12-21 1985-07-16 富士通株式会社 Method of plating printed board
JPS62275750A (en) * 1986-02-21 1987-11-30 株式会社メイコー Manufacture of copper-lined laminated board
JPS62276894A (en) * 1986-02-21 1987-12-01 株式会社メイコー Manufacture of conductor circuit board with through hole
JPS62276893A (en) * 1986-02-21 1987-12-01 株式会社メイコー Manufacture of conductor circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773769A (en) * 1993-09-03 1995-03-17 Ngk Spark Plug Co Ltd External connecting terminal for semi-conductor package and manufacture thereof
JP2011256444A (en) * 2010-06-10 2011-12-22 Sumitomo Bakelite Co Ltd Substrate treating method and substrate treating apparatus
JP2014516121A (en) * 2011-06-09 2014-07-07 ユニヴェルシテ・ドゥ・レンヌ・1 Processing method of felt element percolation by electrodeposition

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