JPH0125162B2 - - Google Patents

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Publication number
JPH0125162B2
JPH0125162B2 JP58058630A JP5863083A JPH0125162B2 JP H0125162 B2 JPH0125162 B2 JP H0125162B2 JP 58058630 A JP58058630 A JP 58058630A JP 5863083 A JP5863083 A JP 5863083A JP H0125162 B2 JPH0125162 B2 JP H0125162B2
Authority
JP
Japan
Prior art keywords
layer
formula
wiring
wiring structure
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58058630A
Other languages
Japanese (ja)
Other versions
JPS59186204A (en
Inventor
Kazunari Takemoto
Haruhiko Matsuyama
Fusaji Shoji
Ataru Yokono
Shunichiro Kuwazuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5863083A priority Critical patent/JPS59186204A/en
Publication of JPS59186204A publication Critical patent/JPS59186204A/en
Publication of JPH0125162B2 publication Critical patent/JPH0125162B2/ja
Granted legal-status Critical Current

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  • Organic Insulating Materials (AREA)
  • Magnetic Heads (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔発明の利用分野〕 本発明は薄膜磁気ヘツドや半導体装置等の電子
部品用の配線構造体の成形方法に関するものにし
て、特に、この配線構造体の絶縁層を平坦にする
成形方法に関するものである。 〔発明の背景〕 近年、薄膜プロセスによつて成形される電子部
品いおいてはパターンの微細化が進むとともに、
何層にも積層してパターンを成形する多層化の要
求がある。この要求に対処するためには下地の凹
凸を平坦化する技術が必要である。この要求に対
して従来から絶縁体層に有機高分子化合物を用い
る方法が知られている。例えば縮合型ポリイミド
は半導体素子の多層配線用の層間絶縁膜として使
われている。これは縮合型ポリイミドが優れた
種々の性質(例えば、加工性、耐熱性、電気的特
性、機械的性質)を持つているためである。 ところが最近になつて、さらに高精度な平坦化
が磁気ヘツドの分野で要求されるようになつた。
また、半導体の分野でも2層以上多層化する場合
や微細化がさらに進むと平坦化に対する要求が非
常に厳しいものとなる。 このような要求に対しては前記した縮合型ポリ
イミドではもはや対処できなくなつてきた。すな
わち第1図に示すように、基板1上に配線2を形
成し、この配線2の上に縮合型ポリイミドを塗
布、硬化してポリイミド絶縁体層3を形成して配
線構造体を成形した場合、基板1上に形成された
配線2の段差によつて、この配線2を被覆するポ
リイミド絶縁体層3は配線2の上と、配線2の間
の基板1の上とで同じ高さにならず、ポリイミド
絶縁体層3の表面にうねりを生ずるという欠点が
あつた。 このため、この絶縁体層の上に例えば磁性膜を
形成すると磁性膜自体もうねりを生じ、磁気特性
が低下するという問題点があつた。また、例えば
半導体装置の微細な多層配線を行う場合、フオト
リソグラフイー技術を適用する際の大きな問題点
となつていた。すなわち、フオトリソグラフイー
は一般にフオトレジストをスピンコートし、露
光、現像してエツチングレジストのパターンを得
るのであるが、段差の凹部ではフオトレジストは
厚く、凸部では逆に薄くなり均一な露光条件が得
られないため、同一線幅のレジストパターンが必
要な場合でも不要に狭い部分や逆に不要に幅広い
部分が生じ、多層の微細パターンの形成は非常に
困難であつた。 〔発明の目的〕 本発明の目的は上記した従来技術の欠点を解決
し、平坦な絶縁体層を得ることができる配線構造
体の成形方法を提供せんとするものである。 〔発明の概要〕 上記の目的を達成するために、本発明者等は配
線構造体の絶縁材料の流動性について多数の実験
と種々の検討を行つた結果、絶縁材料として下記
の一般式〔A〕または〔B〕に示す付加重合型イ
ミドオリゴマを用いて塗布、硬化すると平坦な絶
縁体層が得られることを見いだすに至つた。 (ただし、R1
[Field of Application of the Invention] The present invention relates to a method for molding a wiring structure for electronic components such as a thin film magnetic head or a semiconductor device, and particularly relates to a molding method for flattening an insulating layer of this wiring structure. be. [Background of the Invention] In recent years, the patterns of electronic components molded by thin film processes have become increasingly finer.
There is a demand for multi-layered materials in which multiple layers are laminated to form a pattern. In order to meet this demand, a technique for flattening the unevenness of the underlying material is required. To meet this requirement, a method of using an organic polymer compound for the insulating layer has been known. For example, condensed polyimide is used as an interlayer insulating film for multilayer wiring of semiconductor devices. This is because condensed polyimides have various excellent properties (for example, processability, heat resistance, electrical properties, and mechanical properties). However, recently, even more precise planarization has been required in the field of magnetic heads.
Furthermore, in the field of semiconductors, when there are more than two layers or when miniaturization progresses, the requirements for planarization become extremely strict. The above-mentioned condensed polyimides are no longer able to meet such demands. That is, as shown in FIG. 1, a wiring structure is formed by forming a wiring 2 on a substrate 1, applying condensed polyimide on the wiring 2, and curing it to form a polyimide insulating layer 3. , due to the level difference in the wiring 2 formed on the substrate 1, the polyimide insulating layer 3 covering the wiring 2 is not at the same height on the wiring 2 and on the substrate 1 between the wiring 2. First, there was a drawback in that the surface of the polyimide insulating layer 3 was undulated. For this reason, when a magnetic film, for example, is formed on this insulating layer, the magnetic film itself also undulates, resulting in a problem that the magnetic properties deteriorate. Further, when applying the photolithography technique, for example, when performing fine multilayer wiring of a semiconductor device, it has become a big problem. In other words, photolithography generally spin-coats photoresist, exposes it, and develops it to obtain an etching resist pattern. However, the photoresist is thicker in the concave parts of the step and thinner in the convex parts, making it difficult to achieve uniform exposure conditions. Therefore, even when resist patterns with the same line width are required, unnecessarily narrow portions or unnecessarily wide portions occur, making it extremely difficult to form multilayer fine patterns. [Object of the Invention] An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a method for forming a wiring structure that can obtain a flat insulating layer. [Summary of the Invention] In order to achieve the above object, the present inventors conducted numerous experiments and various studies regarding the fluidity of the insulating material of the wiring structure, and as a result, the following general formula [A It has been found that a flat insulating layer can be obtained by coating and curing the addition polymerizable imide oligomer shown in [] or [B]. (However, R 1 is

【式】n =1〜10) (ただし、R2[Formula] n = 1 to 10) (However, R 2 is

【式】ま たは[Formula] Ma Taha

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例につき、さらに詳細に説
明する。 実施例 1 第2図を参照して、単一層の導体パターンを平
坦化した配線構造体について説明する。 基板1の全面に約2μmの層厚さの導体層を蒸
着により堆積し(スパツタリングによつて堆積し
ても同じ効果を得た)、フオトエツチング技法を
用いて線幅8μm、線間隔4μmの配線2の導体パ
ターンを形成した(この配線パターンはめつき技
法を用いて行つても同じ効果を得た)。次に、下
記一般式〔A〕に示す数平均分子量が約1500のオ
リゴマをN−メチル−2−ピロリドンに溶解して
40重量%の溶液にして、回転塗布、次いで200℃
で30分間、さらにN2雰囲気中350℃で30分間熱処
理して、層厚さ4μmの絶縁体層4を形成した。
このように形成した絶縁体層の上面のうねり高さ
は0.15μm以下という良好な平坦面を有していた。
これは絶縁体層を形成する前の配線による表面凹
凸の7.5%以下の値である。 (ただし、R1
Hereinafter, the present invention will be explained in more detail with reference to Examples. Example 1 Referring to FIG. 2, a wiring structure in which a single-layer conductor pattern is planarized will be described. A conductor layer with a thickness of about 2 μm was deposited on the entire surface of the substrate 1 by vapor deposition (the same effect was obtained even if deposited by sputtering), and wiring with a line width of 8 μm and a line spacing of 4 μm was formed using a photoetching technique. 2 conductor patterns were formed (the same effect was obtained even if this wiring pattern fitting technique was used). Next, an oligomer having a number average molecular weight of about 1500 shown in the following general formula [A] is dissolved in N-methyl-2-pyrrolidone.
40% by weight solution, spin coating, then 200℃
Heat treatment was performed for 30 minutes at 350° C. in an N 2 atmosphere for 30 minutes to form an insulator layer 4 having a thickness of 4 μm.
The upper surface of the insulator layer thus formed had a good flat surface with a waviness height of 0.15 μm or less.
This value is 7.5% or less of the surface unevenness caused by the wiring before forming the insulator layer. (However, R 1 is

【式】n =1〜10) 実施例 2 本実施例においては、複数層の導体パターンを
平坦化した配線構造体を成形した例について説明
する。 実施例1と全く同様にして、第2図に示す単一
層の配線構造体を成形した。次に絶縁体層4上
に、ここには図示しないが、実施例1と同様にし
て配線2のパターンを形成し、次いで絶縁体層4
を形成して2層の配線構造体を成形した。このよ
うにして形成した上部の絶縁体層の上面のうねり
高さは0.2μm以下であつた。また、上部の導体を
蒸着(あるいはスパツタリング)した後の表面に
ふくれやクラツクは認められず、蒸着(あるいは
スパツタリング)プロセスに十分耐えられること
を確認した。 実施例 3 実施例1と同様にして、単一層の導体パターン
を平坦化した配線構造体を成形した。ただし、絶
縁体層は下記一般式〔B1〕に示す数平均分子量
が約1300のオリゴマを用いて形成した。すなわ
ち、オリゴマをN−メチル−2−ピロリドンに溶
解して45重量%の溶液にして、回転塗布、次いで
200℃で30分間、さらに、N2雰囲気中、350℃で
30分間熱処理して層厚さ4μmの絶縁体層を形成
した。このようにして形成した絶縁体層の上面の
うねり高さは0.2μm以下であつた。 (ただし、R2
[Formula] n = 1 to 10) Example 2 In this example, an example will be described in which a wiring structure is formed by flattening a plurality of layers of conductor patterns. In exactly the same manner as in Example 1, a single layer wiring structure shown in FIG. 2 was molded. Next, although not shown here, a pattern of wiring 2 is formed on the insulating layer 4 in the same manner as in Example 1, and then the pattern of the wiring 2 is formed on the insulating layer 4.
was formed to form a two-layer wiring structure. The height of waviness on the upper surface of the upper insulating layer thus formed was 0.2 μm or less. Furthermore, no blisters or cracks were observed on the surface after the upper conductor was vapor-deposited (or sputtered), confirming that it could sufficiently withstand the vapor-deposition (or sputtering) process. Example 3 In the same manner as in Example 1, a wiring structure with a flattened single-layer conductor pattern was molded. However, the insulating layer was formed using an oligomer having a number average molecular weight of about 1300 as represented by the following general formula [B 1 ]. That is, the oligomer was dissolved in N-methyl-2-pyrrolidone to make a 45% solution by weight, spin coated, and then
200°C for 30 min, then 350°C in N2 atmosphere.
A heat treatment was performed for 30 minutes to form an insulating layer with a thickness of 4 μm. The height of waviness on the upper surface of the insulator layer thus formed was 0.2 μm or less. (However, R 2 is

【式】 n=1〜10) 実施例 4 実施例1と同様にして、単一層の導体パターン
を平坦化した配線構造体を成形した。ただし、絶
縁体層は下記の一般式〔B2〕に示す数平均分子
量が約2000のオリゴマを用いて形成した。すなわ
ち、オリゴマをN,N−ジメチルアセトアミドに
溶解して40重量%の溶液にして、回転塗布、次い
で200℃で30分間、さらにN2雰囲気中、350℃で
30分間熱処理して層厚さ4μmの絶縁体層を形成
した。このようにして形成した絶縁体層の上面の
うねり高さは0.15μm以下であつた。 (ただし、R2
[Formula] n=1 to 10) Example 4 In the same manner as in Example 1, a wiring structure having a flattened single-layer conductor pattern was molded. However, the insulating layer was formed using an oligomer having a number average molecular weight of about 2000 as represented by the following general formula [B 2 ]. Briefly, the oligomer was dissolved in N, N -dimethylacetamide to give a 40 wt.
A heat treatment was performed for 30 minutes to form an insulating layer with a thickness of 4 μm. The height of waviness on the upper surface of the insulating layer thus formed was 0.15 μm or less. (However, R 2 is

〔発明の効果〕〔Effect of the invention〕

以上詳述した通り、本発明の方法によれば、絶
縁体層を高精度に平坦化することができるので、
微細なパターンを形成するフオトリソグラフイー
の操作が有利になるとともに、何層にも積層した
立体配線構造体の製造が可能になつた。特に、薄
膜磁気ヘツドを構成した場合に、上部磁性体層に
不要な凹凸を作らないので磁気回路的に有効であ
り、優れた効果を奏する。
As detailed above, according to the method of the present invention, the insulator layer can be planarized with high precision.
The operation of photolithography to form fine patterns has become advantageous, and it has become possible to manufacture three-dimensional wiring structures with multiple layers. Particularly, when a thin film magnetic head is constructed, it is effective in terms of the magnetic circuit because unnecessary irregularities are not created in the upper magnetic layer, and an excellent effect is produced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の単層の導体を有する配線構造
体の断面図である。第2図は本発明の一実施例の
単層の導体を有する配線構造体の断面図である。
第3図は本発明の他の実施例の薄膜磁気ヘツドの
例の複数層の導体を有する配線構造体の断面図で
ある。 1……基板、2……配線、3……絶縁体層(従
来例)、4……絶縁体層、5……セラミツク基板、
6……下地膜、7……下部磁性体層、8……無機
絶縁膜、9……第1層導体コイル、10……第1
絶縁体層、11……第2層導体コイル、12……
第2絶縁体層、13……上部磁性体層。
FIG. 1 is a sectional view of a conventional wiring structure having a single layer conductor. FIG. 2 is a sectional view of a wiring structure having a single layer conductor according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a wiring structure having multiple layers of conductors as an example of a thin film magnetic head according to another embodiment of the present invention. 1...Substrate, 2...Wiring, 3...Insulator layer (conventional example), 4...Insulator layer, 5...Ceramic substrate,
6... Base film, 7... Lower magnetic layer, 8... Inorganic insulating film, 9... First layer conductor coil, 10... First layer
Insulator layer, 11... Second layer conductor coil, 12...
Second insulator layer, 13...upper magnetic layer.

Claims (1)

【特許請求の範囲】 1 基板上に所定のパターンを有する導体層を形
成し、次いで前記導体層上に所定のパターンを有
する絶縁体層を形成して成形する配線構造体にお
いて、下記〔A〕または〔B〕なる一般式で表わ
される化合物を用いて前記絶縁体層を形成するこ
とを特徴とする配線構造体の成形方法。 (ただし、R1は【式】n =1〜10) (ただし、R2は【式】ま たは【式】n=1〜10) 2 基板上に所定のパターンを有する導体層を形
成し、前記導体層上に所定のパターンを有する絶
縁体層を形成し、さらに前記絶縁体層上に所定の
パターンを有する導体層および絶縁体層を繰り返
し積層し、複数層の導体層を形成して成形する配
線構造体において、下記〔A〕または〔B〕なる
一般式で表わされる化合物を用いて前記絶縁体層
を形成することを特徴とする配線構造体の成形方
法。 (ただし、R1は【式】n =1〜10) (ただし、R2は【式】ま たは【式】n=1〜10)
[Scope of Claims] 1. A wiring structure in which a conductor layer having a predetermined pattern is formed on a substrate, and then an insulator layer having a predetermined pattern is formed on the conductor layer and then molded, the following [A] Alternatively, a method for forming a wiring structure, characterized in that the insulating layer is formed using a compound represented by the general formula [B]. (However, R 1 is [Formula] n = 1 to 10) (However, R 2 is [Formula] or [Formula] n = 1 to 10) 2. Form a conductor layer with a predetermined pattern on the substrate, and form an insulator layer with a predetermined pattern on the conductor layer. Further, in a wiring structure in which a conductor layer and an insulator layer having a predetermined pattern are repeatedly laminated on the insulator layer to form a plurality of conductor layers, the following general [A] or [B] may be used. A method for forming a wiring structure, comprising forming the insulating layer using a compound represented by the formula. (However, R 1 is [Formula] n = 1 to 10) (However, R 2 is [Formula] or [Formula] n = 1 to 10)
JP5863083A 1983-04-05 1983-04-05 Method of forming wiring structure Granted JPS59186204A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5863083A JPS59186204A (en) 1983-04-05 1983-04-05 Method of forming wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5863083A JPS59186204A (en) 1983-04-05 1983-04-05 Method of forming wiring structure

Publications (2)

Publication Number Publication Date
JPS59186204A JPS59186204A (en) 1984-10-23
JPH0125162B2 true JPH0125162B2 (en) 1989-05-16

Family

ID=13089901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5863083A Granted JPS59186204A (en) 1983-04-05 1983-04-05 Method of forming wiring structure

Country Status (1)

Country Link
JP (1) JPS59186204A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5690834A (en) * 1979-12-26 1981-07-23 Fujitsu Ltd Coating resin
JPS5693113A (en) * 1979-12-27 1981-07-28 Fujitsu Ltd Thin-film magnetic head
JPS56151757A (en) * 1980-04-28 1981-11-24 Nippon Carbide Ind Co Ltd Polyimide resin molded article

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5690834A (en) * 1979-12-26 1981-07-23 Fujitsu Ltd Coating resin
JPS5693113A (en) * 1979-12-27 1981-07-28 Fujitsu Ltd Thin-film magnetic head
JPS56151757A (en) * 1980-04-28 1981-11-24 Nippon Carbide Ind Co Ltd Polyimide resin molded article

Also Published As

Publication number Publication date
JPS59186204A (en) 1984-10-23

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