JPH01250768A - Phase difference detecting circuit - Google Patents
Phase difference detecting circuitInfo
- Publication number
- JPH01250768A JPH01250768A JP63075914A JP7591488A JPH01250768A JP H01250768 A JPH01250768 A JP H01250768A JP 63075914 A JP63075914 A JP 63075914A JP 7591488 A JP7591488 A JP 7591488A JP H01250768 A JPH01250768 A JP H01250768A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- signals
- output
- phase difference
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 7
- 239000002131 composite material Substances 0.000 claims abstract 3
- 230000003321 amplification Effects 0.000 abstract 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measuring Phase Differences (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は2つの入力信号の位相差を検出するための位相
差検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase difference detection circuit for detecting a phase difference between two input signals.
従来、2つの入力信号の位相差を検出する回路として、
ダブルバランスミキサ(2重平衡変調器)が用いられて
いる。この2重平衡変調器は、2つの平衡変調器を対称
に接続し、1つの信号を各平衡変調器に入力する一方、
他の1つの信号を異なる位相で各平衡変調器に入力させ
、結果として2つの信号の差を出力させ、これから位相
差を検出する。Conventionally, as a circuit for detecting the phase difference between two input signals,
A double balanced mixer (double balanced modulator) is used. This double balanced modulator connects two balanced modulators symmetrically and inputs one signal to each balanced modulator, while
One other signal is input to each balanced modulator at a different phase, resulting in the output of the difference between the two signals, from which the phase difference is detected.
上述した従来の回路は、2つの信号の位相を直接比較す
る2重平衡変調器を用いているが、この2重平衡変調器
は比較的に複雑な回路構成となっている。The conventional circuit described above uses a double-balanced modulator that directly compares the phases of two signals, but this double-balanced modulator has a relatively complicated circuit configuration.
本発明は簡易な回路構成の位相差検出回路を提供するこ
とを目的としている。An object of the present invention is to provide a phase difference detection circuit with a simple circuit configuration.
本発明の位相差検出回路は、2つの入力信号を逆相及び
同相にて合成する四端子ハイブリッドと、このハイブリ
ッドから出力される逆相及び同相の各合成信号を夫々検
波する2つのレベル検波器と、これらレベル検波器の各
出力電圧を減算増幅する差動増幅器とで構成される。The phase difference detection circuit of the present invention includes a four-terminal hybrid that combines two input signals in opposite phase and in phase, and two level detectors that respectively detect the combined signals of opposite phase and in-phase output from this hybrid. and a differential amplifier that subtracts and amplifies each output voltage of these level detectors.
上述した構成では、四端子ハイブリッドで逆相。 In the configuration described above, it is a four-terminal hybrid with opposite phases.
同相に合成された2つの信号の出力のレベルを差動増幅
器において減算増幅することにより、2つの信号の位相
差に応じた出力11圧を得ることができ、2重平衡変調
器を用いたものと同じ検出が実現される。By subtracting and amplifying the output levels of two signals combined in the same phase in a differential amplifier, an output of 11 voltages can be obtained according to the phase difference between the two signals, and a double-balanced modulator is used. The same detection is achieved.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の回路図である。図において
1.2は2つの異なる信号の入力端子であり、各入力端
子1. 2はこれらの入力信号を逆相及び同相で合成す
る四端子ハイブリッド3に接続される。この四端子ハイ
ブリッド3の逆相出力端3A、同相出力端3Bには夫々
の信号を検波するレベル検波器4.5を接続し、更に各
レベル検波器4,5は夫々側検波信号を減算増幅する差
動増幅器6に接続し、出力端子7から検出電圧を出力す
るように構成している。FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, 1.2 are input terminals for two different signals, and each input terminal 1.2 is an input terminal for two different signals. 2 is connected to a four-terminal hybrid 3 which combines these input signals in anti-phase and in-phase. A level detector 4.5 for detecting each signal is connected to the negative phase output terminal 3A and the in-phase output terminal 3B of this four-terminal hybrid 3, and each level detector 4, 5 subtracts and amplifies the detected signal on each side. The output terminal 7 is connected to a differential amplifier 6 that outputs a detected voltage from an output terminal 7.
この回路では、入力端子1.2の2つの入力信号は、四
端子ハイブリッド3において夫々逆相。In this circuit, the two input signals at the input terminals 1 and 2 have opposite phases in the four-terminal hybrid 3.
同相で合成され、逆相合成信号が逆相出力端3Aに、同
相合成信号が同相出力端3Bに夫々出力される。そして
、各信号はレベル検波器4.5により検波され、直流電
圧として出力される。これら出力電圧A、 B (第1
図の点A、Bの電圧)は、2つの入力信号の位相差によ
って第2図のような特性となる。The signals are combined in the same phase, and the negative phase combined signal is output to the negative phase output terminal 3A, and the in-phase combined signal is output to the common phase output terminal 3B. Each signal is then detected by a level detector 4.5 and output as a DC voltage. These output voltages A, B (first
The voltages at points A and B in the figure) have characteristics as shown in FIG. 2 due to the phase difference between the two input signals.
しかる上で、これら電圧A、Bを差動増幅器6により減
算増幅することにより、出力電圧C(第1図の点Cの電
圧)は第3図に示すようになる。Then, by subtracting and amplifying these voltages A and B using the differential amplifier 6, the output voltage C (voltage at point C in FIG. 1) becomes as shown in FIG.
これにより、2つの信号の位相差に応じて所定の関係を
有する出力電圧となり、2つの信号の位相差を検出する
ことができる。これは、2重平衡変調器を用いた位相差
検出出力と同じである。As a result, the output voltages have a predetermined relationship depending on the phase difference between the two signals, and the phase difference between the two signals can be detected. This is the same as the phase difference detection output using a double balanced modulator.
以上説明したように本発明は、四端子ハイブリッドで逆
相、同相に合成された2つの信号の出力のレベルを減算
増幅することにより、2重平衡変調器を用いた場合と同
様に2つの信号の位相差に応じた出力電圧を得ることが
でき、回路の簡略化を達成できる。As explained above, the present invention subtracts and amplifies the output levels of two signals that are synthesized in phase and in phase using a four-terminal hybrid. It is possible to obtain an output voltage according to the phase difference between the two, and the circuit can be simplified.
第1図は本発明の一実施例の回路図、第2図は第1図の
A、B点の各検波電圧を示す図、第3図は第1図の0点
の出力電圧を示す図である。
1.2・・・信号入力端子、3・・・四端子ハイブリッ
ド、3A・・・逆相出力端子、3B・・・同相出力端子
、4゜5・・・レベル検波器、6・・・差動増幅器、7
・・・出力端子。
第1図
第2図
Xカイt!イ江J目ノ1
第3図FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the detected voltages at points A and B in FIG. 1, and FIG. 3 is a diagram showing the output voltage at point 0 in FIG. 1. It is. 1.2...Signal input terminal, 3...Four terminal hybrid, 3A...Negative phase output terminal, 3B...In-phase output terminal, 4゜5...Level detector, 6...Difference dynamic amplifier, 7
...Output terminal. Figure 1 Figure 2 Ie J Eye No. 1 Figure 3
Claims (1)
ハイブリッドと、このハイブリッドから出力される逆相
及び同相の各合成信号を夫々検波する2つのレベル検波
器と、これらレベル検波器の各出力電圧を減算増幅する
差動増幅器とを備えたことを特徴とする位相差検出回路
。1. A four-terminal hybrid that combines two input signals in antiphase and in-phase, two level detectors that respectively detect the anti-phase and in-phase composite signals output from this hybrid, and these level detectors. A phase difference detection circuit comprising: a differential amplifier that subtracts and amplifies each output voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63075914A JPH01250768A (en) | 1988-03-31 | 1988-03-31 | Phase difference detecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63075914A JPH01250768A (en) | 1988-03-31 | 1988-03-31 | Phase difference detecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01250768A true JPH01250768A (en) | 1989-10-05 |
Family
ID=13590069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63075914A Pending JPH01250768A (en) | 1988-03-31 | 1988-03-31 | Phase difference detecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01250768A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107560A1 (en) * | 2003-05-27 | 2004-12-09 | Philips Intellectual Property & Standards Gmbh | Phase detector and method of phase detection |
-
1988
- 1988-03-31 JP JP63075914A patent/JPH01250768A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107560A1 (en) * | 2003-05-27 | 2004-12-09 | Philips Intellectual Property & Standards Gmbh | Phase detector and method of phase detection |
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