JP2604132Y2 - Signal strength detection circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit used for a communication receiver, and more particularly to a signal strength detection circuit for detecting a signal strength of a received signal.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional signal strength detection circuit (RSS).
I: Received Signal Indicator). In the figure, 11a to 11d are limiter amplifiers, 1
2a to 12d are detection circuits, 13 is an output circuit, 14 is an input terminal, and 15 is an output terminal.

As shown in FIG. 1, a plurality of limiter amplifiers are connected in series to an input terminal 14 to amplify a received signal and send the signal to the next-stage limiter amplifier via terminals 16a to 16c. A detection circuit is provided for each output stage of the limiter amplifier, and a detection current is obtained by comparing with a reference voltage. The detection current is converted into a voltage by an output circuit, smoothed, and the signal strength of the received signal is detected.

The number of stages of the plurality of limiter amplifiers is usually about 4 to 10 in many cases, and FIG. 3 shows a configuration in the case of four stages.

FIG. 2 is a circuit diagram of a conventional signal strength detection circuit. In the figure, 1 and 2 are constant current sources, 5 is a reference voltage source, 11 is a limiter amplifier, 12 is a detection circuit, and 13 is an output circuit. FIG. 2 shows a configuration of a basic circuit including a limiter amplifier, a detection circuit, and an output circuit of the block diagram shown in FIG. 3, and in practice, a plurality of limiter amplifiers,
The detection circuit will be used as an additional combination as needed.

[0006] The emitter of the differential amplifier constituting the circuit Q1, Q2 are connected to each other and connected to the constant current source 1. The bases of the transistors Q1 and Q2 are connected to the input terminal 14, and the collectors are resistors R1 and R2, respectively.
It is connected to the power supply via R2. Further, the collector of the transistor Q2 is connected via the terminal 17 to the transistor Q2.
3 connected to the base. The emitter of the transistor Q3 is connected to the emitter of the transistor Q4 and to the constant current source 2. The collector of the transistor Q4 is connected to the power supply, and the base is connected to the reference voltage source 5.

The collector of the transistor Q3 is connected to the base and collector of the transistor Q10 and the transistor Q11.
Connected to the base. Transistors Q10, Q1
1 is a current mirror 10 connected by a current mirror
Is composed. The collector of the transistor Q11 is connected to the output terminal 15, and the resistor R4 and the capacitor C
One end is connected, and the other end is grounded.

[0008] Transistors Q1, Q2, resistors R1, R
2. A limiter amplifier 11 is constituted by the constant current source 1, and the signal applied from the input terminal 14 is transmitted to the transistors Q1 and Q2.
, And sends the output signal to the next-stage limiter amplifier via the terminal 16.

In FIG. 2, one of the output signals is inputted from a collector of a transistor Q2 to a detection circuit 12 comprising transistors Q3 and Q4, a constant current source 2, and a reference voltage source 5. The detection circuit 12 compares the input signal with the voltage set by the reference voltage source 5 and obtains a collector current from the collector of the transistor Q3. This collector current is output to the output circuit 13 as a detection output.

In an output circuit 13 comprising a current mirror 10 composed of transistors Q10 and Q11, a resistor R4 and a capacitor C1, a detection current, which is a detection output from the detection circuit 12, is converted into a voltage and subjected to a smoothing process. Signal strength (RSSI) of the received signal.

[0011]

However, the above circuit configuration has the following problems. As the output amplitude of the limiter amplifier 11 increases, the collector current of the transistor Q3 increases, and the transistor Q3 outputs a detection current proportional to the output amplitude in the active region. However, when the output amplitude of the limiter amplifier increases because the forward voltage of Q10 is generated, the transistor Q3 operates in the saturation region.

Therefore, when the output amplitude of the limiter amplifier becomes large, the collector-emitter current VCE of the transistor Q3 cannot be secured, the drawn current capacity is not constant, and even if the same signal input is applied as shown in FIG. In addition, the RSSI output of each semiconductor integrated circuit greatly varies.

An object of the present invention is to provide a signal strength detection circuit for solving the above-mentioned problems and obtaining a stable RSSI output with respect to the signal strength of a received signal.

[0014]

In order to achieve the above object, the present invention provides a plurality of limiter amplifiers for amplifying an input signal.
And the output signals of the plurality of limiter amplifiers are compared with a reference voltage.
A plurality of detection circuits for outputting a detection current;
Output circuit that converts the detection current of the detection circuit to voltage and smoothes it
The signal strength detection circuit that detects the signal strength.
And the first transistor (Q3) and the second transistor
(Q4), first constant current source (2), reference voltage source (5)
And the first transistor (Q3) is
Input the signal output from the mixer amplifier to the base and
Ground the emitter through the constant current source (2) and power the collector.
And the second transistor (Q4) is connected to a base.
Grounded via the reference voltage source (5), and the emitter connected to the first
Ground through the constant current source (2) of
A detection circuit connected to the third transistor (Q6);
A fourth transistor (Q7), a second constant current source (3),
And the third transistor (Q6) and the third transistor (Q6)
Connect the emitter of the fourth transistor (Q4) to the power supply
Connecting the base to each other,
The collector of the fourth transistor (Q7) is connected to the second transistor (Q7).
Reference current source circuit (6) grounded via constant current source (3)
And the third transistor of the reference current source circuit (6).
From the reference current which is the collector current of (Q6),
The bias current to the collector current of the transistor (Q4)
Subtraction is performed by the circuit (7), and the subtracted current is converted into a voltage.
And an output circuit for smoothing.
It is.

[0015]

With this configuration, the voltage between the collector and the emitter of the detection transistor of the detection circuit can be ensured. When a signal is input, the detection transistor of the detection circuit is controlled according to the output amplitude of the limiter amplifier. The collector current decreases, and the operation is performed so that the reduced difference current becomes the RSSI output.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 2 denote the same or corresponding components, 3 and 4 denote constant current sources, 6 denotes a reference voltage source circuit,
Reference numeral 7 denotes a bias power supply circuit.

The structure of the limiter amplifier 11 is the same as the conventional one. The transistor Q which is the output of the limiter amplifier 11
2 is connected via a terminal 17 to the base of the transistor Q3 of the detection circuit. Transistor Q
The collector of the transistor 3 is connected to the power supply, the emitter is connected to the emitter of the transistor Q4, and is connected to the constant current source 2. The base of the transistor Q4 is connected to the reference voltage source 5, and the collector is connected via a terminal 18 to the emitter of the transistor Q5 and the collector of the transistor Q6.

The emitters of the transistors Q6 and Q7 are connected to a power supply, the bases are connected to each other, and are connected to the collector of the transistor Q7 and the constant current source 3. The transistors Q6 and Q7 and the constant current source 3 constitute a reference current source circuit 6 .

The anode of the diode D1 is connected to the power supply, the cathode is connected to the constant current source 4 via the resistor R3, and the collector and the base of the transistor Q8 and the transistor Q9 are connected to the collector of the transistor Q5.
The base is connected. The emitters of the transistors Q8 and Q9 are grounded. A current mirror 9 is formed by the transistors Q8 and Q9, and a diode D1 and a resistor R
3, constant current source 4, transistor Q5, current mirror 9
Constitute the bias power supply circuit 7.

The collector of transistor Q9 is connected to the base and collector of transistor Q10 and transistor Q1.
1 base. Transistors Q10, Q
Reference numeral 11 denotes a current mirror connection, and constitutes a current mirror 10. The output terminal 15 is connected to the collector of the transistor Q11, one end of the resistor R4 and one end of the capacitor C1 are connected, and the other end is grounded.

Next, the operation of this circuit will be described. The signal applied to the input terminal 14 is amplified by the limiter amplifier 11, and the amplified output signal is input to the base of the transistor Q 3 of the detection circuit 12 via the terminal 17.

The reference voltage source 5 is set so that the transistor Q3 is not turned on when there is no signal. Further, the current values of the constant current source 2 and the constant current source 3 are set equal.

Therefore, in the detection circuit 12, according to the output amplitude of the limiter amplifier 11, the transistor Q3 enters the active region from the cutoff region, and the transistor Q4 changes from the active region to the cutoff region. Then, a detection current corresponding to the output amplitude of the limiter amplifier can be obtained from the collector of the transistor Q4.

A reference current is generated by a reference current source circuit 6 comprising a current mirror 8 and a constant current source 3, and this reference current is output from the collector of a transistor Q6.

The detection current obtained by the detection circuit 12 is subtracted by the bias power supply circuit 7 from the reference current of the reference current source circuit 6. The subtracted current appears at the collector of the transistor Q 5, is outputted from the collector of the transistor Q9 through a current mirror 9. This output current is an output current representing the signal strength.

The output current is current mirror 10, resistor R
4. The voltage is converted to a voltage by the capacitor C1, and the voltage is subjected to a smoothing process to obtain an RSSI output.

The RSSI output is zero when there is no signal,
As the input signal increases, it increases until the limiter amplifier saturates, indicating signal strength. This RSSI
The output can be used to improve the interference characteristics when a strong input signal is applied to the receiver.

[0028]

As described above, since a stable current can be supplied by the reference current source circuit and the collector-emitter voltage VCE of the detection transistor can be secured, the saturation characteristics of the detection circuit and the output circuit can be improved. There is an advantage that the influence of the fluctuation due to the voltage drop is eliminated, and a stable RSSI output can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional signal strength detection circuit.

FIG. 3 is a block diagram of a conventional signal strength detection circuit.

FIG. 4 is a graph showing characteristics of an RSSI output with respect to an input signal.

[Description of sign]

 3, 4, constant current source 5, reference voltage source 6, reference current source circuit 7, bias power supply circuit 11, limiter amplifier 12, detection circuit 13, output circuit

Claims (1)

(57) [Scope of request for utility model registration] 1. A plurality of limiter amplifiers for amplifying an input signal, a plurality of detection circuits for comparing output signals of the plurality of limiter amplifiers with a reference voltage and outputting a detection current, and a detection current for the plurality of detection circuits. Is converted into a voltage and an output circuit for smoothing the voltage, a signal intensity detection circuit for detecting a signal intensity, a first transistor (Q3) and a second transistor (Q
4), a first constant current source (2) and a reference voltage source (5).
And the first transistor (Q3) includes a limiter
Input the signal output from the amplifier to the base,
Is grounded via the constant current source (2), and the collector is connected to the power supply.
Subsequently, the second transistor (Q4) is based on a base.
Grounded via the quasi-voltage source (5) and connect the emitter to the first constant current
Ground through the flow source (2) and connect the collector to the output circuit
Detection circuit, a third transistor (Q6), and a fourth transistor (Q
7) a second constant current source (3);
The transistor (Q6) and the fourth transistor (Q
4) Connect the emitter to the power supply and connect the bases to each other
And the base and the fourth transistor (Q
7) is connected via the second constant current source (3).
A grounded reference current source circuit (6) and the third transistor (Q) of the reference current source circuit (6).
From the reference current which is the collector current of 6), the second transistor
Bias power supply circuit for collector current of transistor (Q4)
Subtract by (7) and convert the subtracted current to voltage
And a smoothing output circuit.