JPS6121855Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a level detection circuit, and is intended to provide a level detection circuit that is particularly suitable for integration into an IC (integrated circuit) and has good linearity.

A level detection circuit that detects AM signals is used to obtain meter drive signals and AGC (automatic gain control) signals. Conventionally, as shown in Figure 1,
A level detection circuit that has an input transistor 1 and a detection transistor 2 and is configured in a direct connection type is known, but such a circuit has poor linearity because it is not possible to apply a base bias to the detection transistor 2. It has the following disadvantages.

Further, a level detection circuit as shown in FIG. 2 is conventionally known. The circuit in Figure 2 consists of input transistor 3
and a detection stage 4 consisting of detection diodes 4a and 4b and a detection amplification transistor 4c , and a capacitor 5 is connected between the input transistor 3 and the detection stage 4 .
Since the base bias of the detection stage 4 is supplied by the diode 6, there is no problem in terms of linearity, but since the input of the detection stage 4 is capacitor-coupled, it is difficult to integrate it into an IC. It has the disadvantage of being

The present invention has been developed in view of the various points mentioned above, and will be described below based on embodiments with reference to the drawings. Fig. 3 shows an embodiment of the present invention.
8 is an input terminal to which an AM signal is applied; 8 is an input transistor whose base is connected to the input terminal 7;
9 is the collector of the input transistor 8 and the power supply 1
11 is a first detection transistor whose base is connected to the collector of the input transistor 8 through a diode 12, and 13 is an emitter connected to the collector of the input transistor 8 through a resistor 14.
A second detection transistor whose emitter is connected to the output terminal 15 of the detection transistor 11; 16 and 17 are connected to the second detection transistor 1;
Diode for biasing the base of 3, 18
is a smoothing capacitor. The first detection transistor 11 is made of an NPN transistor, the second detection transistor 13 is made of a PNP transistor, and the collector-emitter paths of both transistors 11 and 13 are connected in series.

Now, input terminal 7 is connected to AM as shown in Figure 4a.
If a wave input signal is applied, the input signal is amplified by the input transistor 8, level-detected by the diode 12 and the first and second detection transistors 11 and 13, and the fourth signal is output to the output terminal 15.
A detected output signal as shown in FIG. b is obtained. Since the collector of the input transistor 8 is connected to the LC tuning circuit 9, the input signal to be detected is applied between the anode of the diode 12 and the base of the second detection transistor 13, and the input signal to be detected is applied between the anode of the diode 12 and the base of the second detection transistor 13. The signal is detected by the current flow between the anode and cathode of the diode 12 connected in series and between the base and emitter of the first and second detection transistors 11 and 13.
A detected output signal is generated at the collector of the detector.
Note that although the diode 12 is inserted in order to obtain the effect described later, there is no problem in the detection operation itself even if the diode 12 is omitted.

Therefore, with the circuit configuration of the present invention, the collector of the input transistor 8 and the base of the first detection transistor 11 are DC-coupled, and the emitter of the first detection transistor 11 and the emitter of the second detection transistor 13 are DC-coupled. Therefore, there is no need for a coupling capacitor at all, and it has the advantage of being easy to integrate into an IC.

Furthermore, with the circuit configuration of the present invention, all stages can be DC-coupled and a DC bias can be applied, so there is an advantage that a level detection circuit with excellent linearity can be provided.

Furthermore, since a sufficient DC bias can be applied to the base of the second detection transistor 13, it is possible to detect a low level input signal, and it is especially suitable for level detection of a low level output signal of a radio frequency amplifier. It is suitable.

The diode 12 inserted between the collector of the input transistor 8 and the base of the first detection transistor 11 is for preventing the first detection transistor 11 from being saturated when the input signal is large. By inserting the diode 12,
This has the advantage that the range of use of the level detection circuit can be expanded.

As described above, the level detection circuit according to the present invention has many advantages not found in the prior art, and is particularly suitable for use in integrated circuits.

[Brief explanation of the drawing]

Figures 1 and 2 are circuit diagrams showing conventional level detection circuits, Figure 3 is a circuit diagram showing an embodiment of the level detection circuit according to the present invention, and Figure 4a is the input of the circuit in Figure 3. FIG. 4b is a waveform diagram of the input signal applied to the terminal, and FIG. 4b is a waveform diagram of the output signal obtained at the output terminal. Explanation of main figure numbers, 8... Input transistor, 1
1...First detection transistor, 12...Diode, 13...Second detection transistor.

Claims (1)

[Claims for Utility Model Registration] (1) A pair of detection transistors with opposite polarities, whose emitters are commonly connected and whose collector-emitter paths are connected in series, and an input to the base of one of the pair of transistors. A level detection circuit comprising means for applying a signal, means for biasing the base of the other transistor of the pair of transistors, and means for obtaining a detection output signal from the collector of the other transistor. (2) A utility model registration claim characterized in that the means for applying the input signal includes an input transistor and a diode, and the one transistor and the input transistor are DC-coupled by the diode. The level detection circuit according to item 1.