JPS6236338Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a limiter circuit that operates stably with high gain, and particularly provides a limiter circuit suitable for use in an integrated digital proportional radio control receiver. The limiter circuit used in various FM receivers amplifies the intermediate frequency FM wave obtained by the frequency conversion circuit to a certain amplitude and inputs this FM wave to the quadrature detection circuit.

Figure 1 is a block diagram of a conventional digital proportional radio control receiver.High-frequency FM waves are converted to an intermediate frequency by a frequency conversion circuit 1 and applied to a limiter circuit 2, where the frequency reaches a certain amplitude. amplified. Thereafter, the pulses are detected by a quadruple layer detection circuit 3 to obtain a pulse train constituting a channel, and a decoder circuit 4 applies an output for each channel to a digital servo mechanism.

However, limiter circuit 2 has intermediate frequency FM.
High frequency components such as FM waves before being converted to other intermediate frequencies and the output of the crystal oscillator built into the same chip enter regardless of whether they are FM waves or AM waves, so if the gain is increased, oscillation will occur. It is naturally limited because it causes problems and deteriorates the signal-to-noise ratio. Such unstable operation is particularly likely to occur in the radio control receiver whose circuit configuration is simplified or integrated.

This invention deals with these frequencies higher than the intermediate frequency.
This provides a limiter circuit that operates stably by eliminating the effects of FM waves and AM waves.

This invention is a limiter circuit in which the main part is formed by connecting multiple stages of differential amplifier circuits for amplifying intermediate frequency FM waves. They are characterized in that they are connected to each other via.

The present invention will be explained below with reference to FIG. 2, which shows a circuit diagram of a limiter circuit in a digital proportional type radio control receiver that is an embodiment of the present invention.
In Figure 2, T ₁ to T ₂₈ are all NPN transistors, R ₁ to R ₂₈ are resistors, D and D' are diodes, C ₁ and C ₂ are capacitors, E ₁ and E ₂ are batteries,
P ₁ and P ₂ are an input end and an output end, respectively.

One end of the input terminal P ₁ is connected to the base of the transistor T ₁₃ , and the other to the base of the transistor T ₁₄ . The emitters of transistors T ₁₃ and T ₁₄ are connected to each other and to the collector of transistor T ₁ . The emitter of transistor T ₁ is resistor R ₁
The base is connected to the anode of battery E ₂ through resistor R ₁₃ and resistor ₁₄ . The collectors of transistors T ₁₃ and T ₁₄ are connected to the anode of battery E ₁ via resistors R ₁₇ and R ₁₈ , which are load resistances, respectively. Batteries E ₂ and E ₁ are connected in series, and the cathode of battery E ₂ is grounded. Further, the collectors of transistors T ₁₃ and T ₁₄ are connected to the bases of transistors T ₁₅ and T ₁₆ , respectively. The emitters of transistors T ₁₅ and T ₁₆ whose collectors are respectively connected to the anode of battery E ₁ are connected to battery E ₂ through resistors R ₁₃ and R ₁₄ at their bases.
and the collectors of transistors T ₂ and T ₃ whose emitters are grounded via resistors R ₂ and R ₃ , respectively. Transistor T ₁ and resistor
R ₁ , transistor T ₂ and resistor R ₂ , transistor T ₃
and resistor R ₃ respectively constitute a constant current circuit. Therefore, transistors T ₁₃ and T ₁₄ , resistors R ₁₇ and R ₁₈ , transistor T ₁ and resistor R ₁ constitute one differential amplifier circuit, and transistors T ₁₅ and T ₁₆ and the transistor
1 by T ₂ , resistor R ₂ , transistor T ₃ , and resistor R ₃
Two level shift circuits are configured.

In the limiter circuit of FIG. 2, such circuit connections are made one after another up to the fourth stage, each consisting of one differential amplifier circuit and one level shift circuit. A resistor R ₂₅ is connected between the emitter of the transistor T ₂₇ and the collector of the transistor T ₁₁ in the fourth stage level shift circuit, and the emitter of the transistor ₂₈ and the transistor
A resistor R ₂₆ is connected between the collector of T ₁₂ . One of the output terminals _P2 is connected to the collector of the transistor _T12 , and the other is connected to the collector of the transistor _T11 . From the output terminal P ₂ to the input terminal P ₁ there are resistors R ₂₇ , R ₁₅ ,
The direct current is negatively fed back by resistors R ₂₈ and R ₁₆ and capacitors C ₁ and C ₂ , each of which has one end connected between the two resistors and the other end grounded. The voltage of the battery E ₂ divided by the resistor R ₁₄ and the diode D' is applied to the base of the transistor forming the constant current circuit.

_The feature of this invention is that FM waves and AM waves with frequencies higher than the intermediate frequency are removed during amplification _. are connected to each other via a diode D that functions as a capacitive element using junction capacitance, and are short-circuited for high frequencies. In the limiter circuit configured in this way, the intermediate frequency FM wave input from the input terminal _P1 is sequentially amplified by the four-stage differential amplifier circuit while the operating point is level-shifted by the level shift circuit. During the amplification process, the frequency higher than the intermediate frequency input from the input terminal _P1 is
Not only FM waves and AM waves, but also those that enter the entire limiter circuit due to electromagnetic coupling are amplified. However, since the collectors of transistor _T17 and transistor _T18 , which are the output terminals of the second stage differential amplifier circuit, are connected to each other via diode D, the FM wave at the intermediate frequency is amplified, but the frequency is lower than the intermediate frequency. High frequency FM and AM waves will be canceled out.

Therefore, from the output terminal _P2 , only the intermediate frequency FM wave amplified to a certain amplitude is applied to the next quadrature detection circuit.

In the limiter circuit of this invention, unnecessary high frequencies higher than the intermediate frequency are removed without being amplified, so even if the overall gain is increased, oscillation phenomena and deterioration of the SN ratio caused by these high frequencies will not occur. does not occur. The gain of a conventional limiter circuit is as follows when a crystal oscillator is built into the same chip.
The limit was 60 dB, but it is easy to increase it above this, and it is also possible to improve the SN ratio of the entire receiver. In conventional receivers, when the input signal to the frequency conversion circuit is 20 dB, the SN ratio of the output of the quadrature detection circuit is about 5 dB, but by just using the limiter circuit of this invention, the SN ratio is about the same with an input signal of 10 dB. is obtained.

In the above embodiment, the output end of the second-stage differential amplifier circuit is connected via a diode to short-circuit the high frequency, but other differential amplifier circuits may be configured similarly if necessary. You can also do it. It goes without saying that the diode connection can be replaced by a capacitor with a small capacity.

Furthermore, in the embodiment of the present invention, a limiter circuit with a low power supply voltage used in a radio control receiver was explained, so a level shift circuit was used in each stage, but the use of a level shift circuit is not the gist of the present invention. It is clear that the present invention can be applied to general limiter circuits that do not use such a circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional digital proportional radio control receiver for explaining the present invention, and FIG. 2 is a circuit diagram of a limiter circuit showing an embodiment of the present invention. _T1 ... _T28 : NPN transistor, _R1 ... _R28 :
Resistor, C ₁ , C ₂ : Capacitor, D, D': Diode, E ₁ , E ₂ : Battery, P ₁ : Input end, P ₂ : Output end.

Claims (1)

[Claims for Utility Model Registration] (1) In a limiter circuit whose main part is constructed by connecting multiple stages of differential amplifier circuits via level shift circuits to amplify FM waves converted to an intermediate frequency, A limiter circuit characterized in that output terminals of at least one differential amplifier circuit in a preceding stage of the limiter circuit are connected to each other via an element that functions as a capacitor. (2) Utility model registration claim 1, in which the output terminals of the second-stage differential amplifier circuit of the differential amplifier circuit connected in multiple stages are connected to each other via an element that functions as a capacitor. The limiter circuit described.