JPH01246639A - Comparison error detection control circuit - Google Patents

Abstract

PURPOSE:To correctly detect error by using a microprogram and an error detection start control circuit and starting comparison after termination of initialization of the internal state of a dual system. CONSTITUTION:Data on an internal bus 43 is set to an internal bus register 1, and parity of the output is generated by a parity generating part 2. Internal bus parity generated by the other arithmetic processing device in the same manner is inputted from an external terminal 13 and is compared with said parity by a parity comparing part 3. Since comparison is always performed, comparison error occurs when the internal state is not initialized yet just after system rise. For the purpose of preventing this error, an initializing microprogram is started after system rise and an error detection start instruction is stored in a register 4 after initialization and is decoded by a decoding part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to reporting of comparison errors in a duplicate system of arithmetic processing units in a computer system.

[Conventional technology]

In a conventional dual arithmetic processing unit system for increasing system reliability, errors are detected by comparing arithmetic results by comparing internal buses connecting registers and arithmetic units. As shown in FIG. 4, the method for comparing the internal buses is the exclusive OR of each bit of the data input from the external EPU 41 and the data on the internal bus 43 stored in the internal bus register 42. Negation is taken at gate 19, and if there are bits with different values, it is reported to error register 8 via AND gate 20.

[Problem to be solved by the invention]

In the above-mentioned comparison of internal bus data, since it is constantly compared immediately after system startup, there are some registers inside the arithmetic processing unit that have not been initialized, and these are output to the internal bus. However, there is a drawback in that when the internal bus parity comparison error is detected and reported to the error register.

[Means to solve the problem]

The internal bus parity comparison detection control circuit of the present invention includes a parity generation circuit for comparing only the data parity of the internal bus, a parity conveyor section for comparing the parity of internal bus data of an external arithmetic processing unit, and an error detection control circuit. A register that stores microinstructions for microprogram control, a decoder that decodes the microinstructions, and an error that generates a control signal when the decoding results in an instruction that starts internal bus parity comparison. It has a detection start control section, a means for reporting an internal bus parity comparison error result to an error register based on the control signal thereof, and an error register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The data on the internal bus 43 is set in the internal bus register 1,
The parity generation unit 2 generates the parity of the output. Similarly, the internal bus parity generated by the other arithmetic processing unit is inputted from the external terminal 13 and compared and checked by the parity conveyor section 3. Here, errors in the duplex system only need to be detected on one side of the device, so if we decide to detect it on the slave side, as shown in the specific example of the parity conveyor section in Figure 2, the slave side of the duplex system A signal S indicating that

EXN which is the result of the conveyor of parity corresponding to S'
The output of OR gate 14 is controlled through AND gate 7. Furthermore, since the slave side does not output comparison data parity to the master side, the output driver 12 is disabled.

Since the comparison is constant, immediately after starting the system,
If internal initialization is not performed, a comparison error will occur.

In this embodiment, in order to prevent this, microprogram control is performed to control the start of comparison error detection. After the system is started up, the initialization microprogram is started, and after the initialization of the system's internal registers is completed, the microinstruction to start error detection is stored in register 4 in Figure 1, and is decoded by the microinstruction decoder. Ru.

Next, FIG. 3 shows a specific example of the error detection start control section and the process up to setting the error register.

F/F-17 is instructed to start comparison error detection.
It is used to hold the signal generated by the microinstruction decoding unit 5 from then on, and is cleared when the system is reset. If the output of the parity conveyor section is 1', the AND gate 7 sets 1' in the error register 18 and reports an error, but at that time, if the output of the F/F 17 is 0, that is, it is a microinstruction error. If the detection start command has not been issued, the error report is invalidated.

〔Effect of the invention〕

As explained above, the present invention uses a microprogram and an error detection start control circuit when comparing internal states in a duplex system of arithmetic processing units, so that the comparison can be made after the initialization of the internal states is completed. This has the effect of correctly detecting errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a specific example of the internal bus parity conveyor section, FIG. 3 is a circuit diagram of a specific example from the microinstruction storage register to the error register, and FIG. FIG. 4 shows a comparison error detection circuit of a conventional duplex system. 1... Internal bus register, 2... Parity generation section,
3... Internal bus parity conveyor unit, 4... Micro instruction storage register, 5... Micro instruction decoding unit, 6... Comparison error detection start control unit, 7... AN
D gate, 8...Error register (18...D-F/F of internal bus parity comparison error-corresponding bit), 9.
...Register group connected internally, 10...ALU, 1
2... Output driver, 13... External connection terminal, 14
... EXNOR gate, 15 ... Jump tag (input of AND gate 7 in Figure 3), 16 ... OR gate, 17 ... With mask reset to hold control signal -
Flip-flop, 19...EXNOR gate, 20
...AND gate.

Claims (1)

[Claims] In a data processing apparatus in which two data processing apparatuses are provided and the same processing is executed simultaneously to perform an operation check, a register for storing data on an internal bus of the data processing apparatus, a parity generation unit thereof, and the parity generation unit are provided. An internal bus parity conveyor unit that compares the output with the internal bus parity of the other data processing device, a microinstruction storage register, a microinstruction decode unit, and a microinstruction decode unit that enables error detection of the internal bus parity comparison of the decoded instructions. A comparison error detection control comprising: means for generating a control signal for starting a comparison when an instruction is issued to cause a comparison error; means for controlling reporting of a comparison error; and an error register for receiving the error report. circuit.