JPH01243617A - Clock phase adjustment circuit - Google Patents

Abstract

PURPOSE:To obtain a clock having an optional phase difference by constituting the title circuit by means of a delay circuit which can adjust a delay time from an external part and a clock generation circuit which generates a pulse signal based on an output from the delay circuit. CONSTITUTION:The title circuit consists of the delay circuit 2 which has structure that can adjust the value of a circuit element 25 deciding an output pulse width from the external part, and which generates and outputs the pulse signal 200 with the pulse width decided by the operation of the circuit element 25 from an input clock 100, and the clock generation circuit 4 which generates the clock having the prescribed phase difference from the input clock 100 based on the output pulse 200. Thus, the clock having the optional phase difference can be obtained, and its difference accepted on the order of seconds can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock phase adjustment circuit that changes the phase of an input clock, and particularly to obtaining a clock adjusted to a desired phase from an input clock. The present invention relates to a clock phase adjustment circuit capable of

[Conventional technology]

Conventional clock phase adjustment circuits of this type are used, for example, in digital communication equipment that uses a self-synchronization method that transmits data by including a clock component in the data, and after extracting the clock from the received data, This circuit adjusts the phase between the clock and the clock.

Such a clock phase adjustment circuit is configured to physically adjust the phase of a data signal and a clock using a delay element such as a delay line. According to such a clock phase adjustment circuit,
A clock adjusted to a desired phase can be obtained from the input clock.

[Problem to be solved by the invention]

However, since the conventional clock phase adjustment circuit described above uses a delay element, the delay time is 10XIO.
-'C seconds (= n S ) E degree & t (7) is the limit. Furthermore, the clock phase adjustment circuit described above has the drawback that the phase difference is determined by the amount of delay of the delay element described above, and the delay time is fixed.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a clock phase adjustment circuit that can obtain clocks with a desired phase difference.

[Means to solve the problem]

In order to achieve the above object, the clock phase adjustment circuit of the present invention has a structure in which the value of a circuit element that determines the output pulse width can be externally adjusted in the clock phase adjustment circuit that changes the phase of an input clock. and a delay circuit that forms and outputs a pulse signal with a predetermined pulse width from the input clock by the action of the circuit elements described above, and a delay circuit that generates a predetermined phase difference between the input pulses based on the output pulse from the delay circuit. It is constructed from a clock forming circuit that forms a clock having a .

In such a clock phase adjustment circuit of the present invention, when the values of the circuit elements described above in the delay circuit are adjusted externally so as to have the required phase difference, the delay circuit outputs a value according to the value of the circuit element. A phase difference pulse is output.

This pulse is taken into the clock forming circuit described above, and this clock forming circuit forms a clock having a predetermined phase difference from the input pulse described above. Thereby, the clock phase adjustment circuit of the present invention can obtain a clock having an arbitrary phase difference, and the phase difference can also be obtained as a metal dust.

〔Example〕

Next: The present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the clock phase adjustment circuit of the present invention, and FIG. 2 is a time chart shown for explaining the operation of the embodiment.

The embodiment shown in FIG. 1 is composed of a delay circuit 2 and a clock forming circuit 4. The delay circuit 2 includes a one-shot multi-by-break 20 and a capacitor 21. which is a circuit element 25 that can determine the output pulse width. It is constructed by attaching a resistor 22, and is configured to form and output a pulse signal 200 with a predetermined pulse width from the input clock 100 by the action of circuit elements (capacitor 21, resistor 22). The values of the capacitor 21 and the resistor 22, which are circuit elements that can determine the output pulse width, can be adjusted from the outside. The delay circuit 2 is configured so that this output pulse is supplied to the clock forming circuit 4. The clock forming circuit 4 generates a clock 30 having a predetermined phase difference from the input clock 100 based on the pulse signal 200.
It has a circuit configuration that can form 0, and is configured as follows.

The one-shot multi-byte break 40 that takes in the input clock 100 is configured by installing a capacitor 41 and a resistor 42, which are circuit elements that can determine the output pulse width.
, resistor 42) to form and output a pulse signal 400 having a predetermined pulse width. a capacitor 41, which is a circuit element that can determine the output pulse width;
The value of the resistor 42 can be adjusted externally, and the value of the resistor 42 is normally adjusted by the capacitor 21. It is set to the same value as the resistor 22. The pulse signal 200 from the delay circuit 2 is input to an input terminal C of a frequency dividing circuit 430 that divides the pulse signal into two. The pulse signal 400 from the one-shot multi-by-break 40 is inputted to an input terminal C of a frequency dividing circuit 440 that divides the pulse signal into two. The pulse signal 410 from the output terminal Q of the frequency dividing circuit 43 and the pulse signal 420 from the output terminal Q of the frequency dividing circuit 44 are supplied to an exclusive OR circuit 45.

A clock 300 having a predetermined phase difference is obtained from the output terminal of this exclusive OR circuit 45.

Note that the reference numeral 500 is a power supply start-up reset pulse.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

First, a power-up reset pulse 500 as shown in FIG. 2(a) is input to the clock forming circuit 4 to initialize the frequency dividing circuit 1443 and the frequency dividing circuit 44 of the clock forming circuit 40.

Next, the input clock 100 as shown in FIG.
is input.

In the delay circuit 2, the input clock 100 is given to the one-shot multi-by-break 20, and the input clock 1
It starts operating at the rising edge of 00, outputs a pulse signal 200 with a pulse width as shown in FIG.

On the other hand, in the clock forming circuit 4, the pulse signal 200: Well, the frequency dividing circuit 43 which operates at the rising edge of the pulse signal 200 is activated as shown in FIG.
), the frequency is divided into two. Similarly, the input clock 100 input to the clock forming circuit 4 is applied to the one-shot multi-by-break circuit 40, which operates at the falling edge of the input clock 100, and its capacitor 41 and resistor 4.
A pulse signal 400 having a pulse width as shown in FIG. 2(d) determined in step 2 is output. The frequency of this pulse signal 400 is divided into two by a frequency divider circuit 44 which operates at the rising edge of the pulse signal. The signals 410 and 420, each frequency-divided in this way, are
When input to the exclusive OR circuit 45, it is output as a clock 300 having a predetermined phase difference as shown in FIG. 2(g).

As a result, the clock 300 is a pulse signal having the same width as the input clock 100 and has a predetermined phase difference with respect to the input clock 100. This pulse width is determined by CIX and RIX of capacitor 21 and resistor 22.
and C2X and R2X of the capacitor 41 and resistor 42, which has a phase difference equal to the pulse width.

Note that the above embodiment is configured using the delay circuit 2 and the clock forming circuit 4 on the assumption that the input clock 100 and the clock 300 have the same pulse width. However, the invention is not limited to this embodiment, and if it is sufficient to simply provide a predetermined phase difference between the input clock 100 and the clock 300, the clock forming circuit 4 may use the pulse signal 200 as it is, for example, as shown in FIG. 2(C). The pulse signal may be output using the rising edge of the pulse signal 200, or the one-shot multi-by-break 40, the frequency divider circuit 43, the frequency divider circuit 44, and the exclusive OR circuit 45 may be omitted and a predetermined Even if a one-shot multi-vibrator that can output a pulse width is newly installed, a pulse signal of 200 mm is input to this one-shot multi-vibrator, and a constant pulse output is obtained from the rising edge of the pulse signal. The same effect as in the embodiment can be achieved.

〔Effect of the invention〕

As explained above, the present invention consists of a delay circuit whose delay time can be adjusted externally and a clock forming circuit which forms a pulse signal based on the output from this delay circuit. You can get a clock with
This has the effect that a phase difference up to that of gold dust can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart shown to explain the operation of the embodiment. 2...Delay circuit, 4...Clock forming circuit, 25...Circuit element, 100...Input clock, 300...Clock.

Claims (1)

[Claims] A clock phase adjustment circuit that changes the phase of an input clock has a structure in which the value of a circuit element that determines the output pulse width can be adjusted from the outside, and the pulse width determined from the input clock by the action of the circuit element. A clock phase adjustment comprising: a delay circuit that forms and outputs a pulse signal; and a clock formation circuit that forms a clock having a predetermined phase difference from the input pulse based on the output pulse from the delay circuit. circuit.