JPH09200005A - Duty correction circuit and integrated circuit element including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a duty correction circuit without a problem caused in a conventional circuit such as the occurrence of dispersion in an output clock duty due to dispersion in the capacitance of a capacitor. SOLUTION: This circuit is provided with a clock generating circuit 10 outputting clock (h) whose duty is variable, and a control circuit 20 controlling the clock generating circuit 10. The clock generating circuit 10 uses a leading edge phase of an input clock (a) for a leading edge phase of the generated output clock (h) and uses a trailing edge phase controlled by the control circuit 20. The control circuit 20 generates a control signal (b) relating to the trailing edge phase of the clock generating circuit 10 by delaying the input clock (a) with 1st and 2nd variable delay circuit 21, 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention automatically corrects the duty of an LSI (Large Scale Integrated Circuit) input clock and supplies a clock having a constant duty to a circuit using the clock. To a duty correction circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of duty correction circuit is
For example, it is disclosed in Japanese Patent Laid-Open No. 4-297120. The duty correction circuit described in this publication includes a first variable delay circuit that adjusts the phase of the rising edge of the input clock signal and a first variable delay circuit that adjusts the phase of the falling edge of the output clock signal of the first variable delay circuit. The second variable delay circuit and the control circuit for monitoring the duty of the clock signal output from the second variable delay circuit and adjusting the delay values of the first and second variable delay circuits. The control circuit includes a duty deterioration detection unit including an integrator (inverter and capacitor), a high trip inverter, and a low trip inverter, and an up / down generator that generates control signals for the first and second variable delay circuits from the duty deterioration information. It is composed of a down counter and an up / down control pulse generation circuit.

The duty correction circuit automatically adjusts the duty in the following manner. The output clock signal has no duty deterioration (stable circuit state)
In, the integrator output potential is between the threshold values of the high trip inverter and the low trip inverter, and the up / down counter and the first and second variable delay circuits do not operate.

When a clock signal with a low duty is input, the output potential of the integrator rises, and when it reaches the threshold potential of the high trip inverter, the up / down counter is counted up. Along with this, the second variable delay circuit operates to increase the delay added to the falling edge and increase the duty.

On the other hand, in the case of a clock signal with a large duty, the integrator output potential drops, and when it reaches the threshold potential of the low trip inverter, the up / down counter is counted down. Accordingly, the first variable delay circuit increases the delay added to the rising edge,
Operates to reduce the duty.

[0006]

The conventional duty correction circuit as described above has a problem that the usable process is limited when the capacitor of the integrator in the control circuit is formed inside the LSI. Especially CM
It cannot be configured in a device by a digital process like the OS gate array.

Further, there is a problem that the power consumption of the inverter for charging and discharging the capacitor of the integrator is large.

Further, since analog processing is used to detect the deterioration of duty, there is a fluctuation in the capacitance value of the capacitor caused by variations in the characteristics of the manufactured LSI elements and a fluctuation in the threshold value of the high trip inverter and the low trip inverter. As a result, there is a problem in that the output clock duty after adjustment varies.

An object of the present invention is to provide a duty correction circuit in which variations in output clock duty do not occur.

Another object of the present invention is to provide a duty correction circuit whose power consumption may be small.

Still another object of the present invention is to provide a duty correction circuit which can be constructed in an integrated circuit device as a whole.

Another object of the present invention is to provide an integrated circuit device including the above duty correction circuit.

[0013]

According to the present invention, in a duty correction circuit for correcting the duty of an input clock to a predetermined value, a clock generation circuit for outputting the duty of a clock signal in a variable manner, and the clock generation circuit The clock generation circuit uses the rising edge phase of the input clock signal as the rising edge phase of the output clock signal to be generated, while the falling edge phase is controlled by the control circuit. The control circuit receives a control signal regarding a falling edge phase of the clock generation circuit,
A duty correction circuit characterized by being generated by delaying an input clock signal by a delay circuit.

Also according to the invention, the control circuit is
Two variable delay circuits provided in series for two clock cycles, and
Both frequency division circuits, a phase comparator, and an up / down counter, and both phases of an input signal and a clock signal to which a delay of one clock cycle is added by the variable delay circuit provided in series with the two. It is possible to obtain the duty correction circuit including a phase synchronization circuit that adjusts the two variable delay circuits provided in series so as to synchronize with each other.

The present invention further provides an integrated circuit device including the duty correction circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A duty correction circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a duty correction circuit according to an embodiment of the present invention. FIG. 2 shows FIG.
5 is an operation waveform diagram of the present duty correction circuit shown in FIG.

Referring to FIGS. 1 and 2, the duty correction circuit of the present invention includes a clock generation circuit 10 for outputting a clock signal with variable duty, and a clock generation circuit 10.
And a control circuit 20 for controlling the.

The clock generation circuit 10 receives the input clock a input from the clock input terminal as a first D flip-flop.
The signal f divided by 2 by the flop circuit (DFF) 11
And a signal g delayed by the second D flip-flop circuit (DFF) 12 using the timing from the control circuit 20 after being divided by 2 by the first D flip-flop circuit 11 A clock is generated by the exclusive OR circuit 13 and is output from the clock output terminal.

The duty of the output clock h is the second D
It is variable by adjusting the clock input phase of the flip-flop circuit 12 (the output b of the first variable delay circuit 21 described later).

Referring to FIG. 2, the first variable delay circuit 2
The phase of the output b of 1 is a phase delayed by 1/2 cycle with respect to the input clock a in order to generate a clock with a duty of 50%.

The control circuit 20 includes two first and second variable delay circuits 21 and 22 provided in series having a delay amount of about one cycle of the input clock a and first and second n delay circuits. The first and second variable delay circuits 21 and 22 provided in series with the input clock “a” are provided for each clock cycle and are provided with the frequency divider circuits 23 and 24, the phase comparison circuit 25, and the up / down counter 26. It is configured by a phase synchronization circuit that adjusts the first and second variable delay circuits 21 and 22 so that both phases are synchronized with the delayed clock signal (output c of the second variable delay circuit 22). ing.

In the present invention, in order to lock the delay amounts of the first and second variable delay circuits 21 and 22 provided in series with two delays of exactly one cycle of the input clock a,
Instead of directly comparing the phase of the input clock a with the output c of the second variable delay circuit 22, a phase comparison of the signals d and e divided by n by the first and second n divider circuits 23 and 24 is performed. I do. As a result of the phase comparison by the phase comparator 25,
When the signal e leads the signal d in phase, the up / down counter 26 counts up, and
And the delay amounts of the second variable delay circuits 21 and 22 are increased. On the other hand, when the phase of the signal e is behind that of the signal d, the up / down counter 26 counts down, and the delay amounts of the first and second variable delay circuits 21 and 22 are reduced. The control circuit 20 achieves phase synchronization by repeating this operation, and the manufactured L
Even if the characteristic of each SI element varies, the power supply fluctuates during use, the temperature fluctuates, or the like, the delay amounts of the first and second variable delay circuits 21 and 22 are always set to 1 of the input clock a.
It is possible to keep the number of cycles.

When the control signals of the first and second variable delay circuits 21 and 22 are made common as in this embodiment, the output b of the first variable delay circuit 21 corresponds to the input clock a. And a phase delayed by 1/2 cycle is maintained, and the output b of the first variable delay circuit 21 is used as the clock input of the second D flip-flop circuit 1212 of the clock generation circuit 10, so that the duty is 50. You can get a clock that is automatically corrected to a percentage.

The duty can be set to an arbitrary value by changing the ratio of the delay amounts of the first and second variable delay circuits 21 and 22 provided in series.

[0026]

The duty correction circuit according to the present invention has a clock generation circuit that outputs the clock signal with variable duty, and a control circuit that controls the clock generation circuit. The clock generation circuit generates an output clock. The rising edge phase of the input clock signal is used as the rising edge phase of the signal, while the falling edge phase is controlled by the control circuit, and the control circuit controls the falling edge phase of the clock generation circuit. The signal is generated by delaying the input clock signal with a delay circuit, so automatic duty correction is performed by digital processing, so passive elements such as capacitors are no longer needed, and gate threshold adjustment is not required. Is.

Therefore, the adjusted output clock duty varies due to the variation in the capacitance value of the capacitor caused by the variation in the characteristics of each manufactured LSI element and the variation in the threshold value of the high trip inverter and the low trip inverter. There is no problem seen in the past. Moreover, power consumption may be small. Further, the entire circuit can be constructed within an integrated circuit device. In addition, the integrated circuit device including the duty correction circuit has a low manufacturing cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a duty correction circuit according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the duty correction circuit shown in FIG.

[Description of Reference Signs] 10 clock generation circuit 11 first D flip-flop circuit 12 second D flip-flop circuit 13 exclusive OR circuit 20 control circuit 21 first variable delay circuit 22 second variable delay circuit 23 first n-divider circuit 24 second n-divider circuit 25 phase comparator 26 up / down counter

Claims (3)

[Claims] 1. A duty correction circuit for correcting the duty of an input clock to a predetermined value, and a clock generation circuit for variably outputting the duty of a clock signal,
A control circuit for controlling the clock generation circuit, wherein the clock generation circuit uses the rising edge phase of the input clock signal as the rising edge phase of the output clock signal to be generated, while the falling edge phase is controlled by the control circuit. The control circuit is controlled by a circuit, and the control circuit generates a control signal relating to a falling edge phase of the clock generation circuit by delaying an input clock signal by a delay circuit. Duty correction circuit. 2. The control circuit has two clock cycles.
A variable delay circuit provided in series with each other, two frequency divider circuits, a phase comparator, and an up / down counter are provided, and an input signal and two variable delay circuits provided in series are provided for one clock cycle. 2. The duty correction circuit according to claim 1, wherein the duty correction circuit is configured by a phase synchronization circuit that adjusts the two variable delay circuits provided in series so that both phases of the clock signal to which the delay is added are synchronized. 3. An integrated circuit device including the duty correction circuit according to claim 1.