JPH01242294A - Semiconductor memory apparatus - Google Patents

Abstract

PURPOSE:To reduce the density of pattern wiring and a pattern length, by separately arranging memory signal driving parts to both ends of a memory IC and wiring the memory terminals of the memory IC serially and connecting both terminals thereof to each memory signal driving parts. CONSTITUTION:The address buffer IC 7 and damping resistor 14 on the side of a port 1 and the address buffer IC 8 and damping resistor 15 on the side of a port 2 are arranged to both ends of a memory array part 2, and the mem ory address signal bus 5 from the port 1 and the memory address signal bus 6 from the port 2 are separated to perform wiring. Therefore, the pattern wiring density and wiring length of this part are reduced. By arranging memory address buffer circuits 19, 20 and damping resistors 23, 24 to both ends of a memory IC, the memory signal wiring 25 of the memory IC part can be connected seri ally with respect to the memory IC and the memory signal wiring of the mem ory IC part also becomes easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory board, and particularly to a technique effective for a memory signal driving method of a dual port memory board.

[Conventional technology]

Conventionally, in the case of a memory board of the Puar port type, memory signals such as memory address and memory data signals from each port were switched by a multiplexer circuit or a dedicated LSI and supplied to the memory IC through a damping resistor. For example, a dual-port RA that allows hardware to determine for each shared resource which microcontroller has exclusive rights to shared memory between two microcontrollers.
Regarding M, there is Japanese Patent Application No. 61-144871.

[Problem to be solved by the invention]

In the above conventional technology, memory signals such as a memory address signal, memory data signal, and memory control signal from each port are switched to one of the memory signals from each port in the switching circuit section, and then wired to the memory IC. was. In this case, memory signals from each port are concentrated in this switching circuit section, which results in an increase in pattern density and pattern wiring in this section, causing signal noise and crosstalk. is.

An object of the present invention is to reduce the density and pattern length of wiring patterns for these memory signals.

[Failure to solve the problem]

The above purposes are memory IC and memory address signals.

Note the driver IC and diving resistance that drive memory signals such as memory data signals and memory control signals.
This is accomplished by serially wiring the memory signal terminals of the memory ICs placed separately at both ends of the IC block and sandwiched between the memory signal drive circuits, and connecting both ends of the memory ICs to each memory signal drive circuit.

[Effect]

According to the above means, the memory signal from each port is
Each memory I located at both ends of the memory block
Since they are connected to the C drive circuit in a distributed manner, it is possible to prevent the wiring patterns from concentrating. Furthermore, with this means, the memory IC wiring within the memory block is wired to the memory signal drive circuits placed at both ends of the memory block, so each memory IC section can be wired serially, and the wiring of the memory IC section is also easy. Become.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is an overall configuration diagram of a memory board using the present invention.

The configuration shown in Figure 1 is a dual port memory board■
, memory array section equipped with many memory ICs ■, port 1 signal input/output terminal ■, port 2 signal input/output terminal ■, memory address signal bus from port 1 ■, memory address signal bus from port 2 ■, port A tri-state 17 address buffer IC ■ that drives the memory array section by the address bus ■ from port 1, a tri-state address buffer IC ■ that drives the memory array section by the address bus ■ from port 2, A conflict determination circuit 0.0 determines which access is to be selected from the memory access request signal 2 from port 2, the memory access request signal from port 2, and the memory access request signal from port 1 and port 2. Port 1 memory selection signal ■ output from conflict determination circuit 0, port 2 memory selection signal 0. Damping resistor 0.0 for the memory address signal output from the address buffer IC on the port 1 side. Similarly, it is a damping resistor [phase] for the memory address signal output from the address buffer IC on the port 2 side.

Next, the operation of the present invention will be explained with reference to FIG.

First, port 1. The memory access request signal (2), [phase] from port 2 is input to the alignment determination circuit (2), which determines which port is to be allowed access. If the port 1 side is enabled, the port 1 memory selection signal @ becomes valid, and as a result, the port 1 memory address buffer I
The output of C■ changes from the tri-state state to the output valid state, and the information on the memory address signal line from port 1 is output to the memory array section ■ through damping resistor 0. On the other hand, if access on the port 2 side is permitted in the conflict determination circuit @, the port 2 memory selection signal 0 becomes valid, and as a result, the port 2 memory address buffer IC
(2) changes from the tri-state state to the output valid state, and information on the memory address signal line from port 2 is output to the memory array section (2) through the damping resistor [phase].
.

According to this embodiment, the address buffer IC on the port 1 side
■ and damping resistor 0, address buffer IC on the port 2 side, and damping resistor [phase] are arranged at both ends of the memory array section, separating the port 1 memory address signal bus ■ and the port 2 memory address signal path ■ This has the effect of reducing the pattern wiring density and wiring length in this portion.

FIG. 2 is a wiring pattern diagram of the memory IC in the memory array section.

The configuration in the figure is based on the memory IC included in the memory array section (■).
Section O, port 1 memory address signal 0° Port 2 memory address signal [phase], tri-state address buffer circuit [phase] for driving the memory IC with address signal O from port 1, similarly port 2 side tri-state State type address buffer circuit [phase], port 1 memory selection signal ■, port 2 memory selection signal @, damping resistor for port 1 @.

These are the damping resistor for port 2 @ and the memory signal wiring (■) of the memory IC section.

In the same figure, memory address buffer circuit 0'
By placing damping resistors @ and ■ at both ends of the memory IC, the memory signal wiring [phase] of the memory IC section can be serially connected to the memory IC, and the memory IC section memory signal This has the effect of making wiring easier.

〔Effect of the invention〕

According to the present invention, it is possible to separate and wire the pattern of memory signals from each port for each port,
Compared to conventional methods where memory signals for each port were concentrated in one part, the density of pattern wiring can be reduced to about half.

Furthermore, the pattern of the memory signal in the memory IC section is such that the memory signal driver section is arranged at both ends of the memory IC, so it can be connected serially to the memory IC.
C part pattern wiring becomes easy.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a memory board using the present invention, and FIG. 2 is an arrangement pattern diagram of memory ICs in a memory array section. 1... Dual port memory board, 2... Memory array section, 3, 4... Signal input/output terminal, 5.6...
Address bus, 7, 8... Tri-state address buffer IC, 11... Conflict determination circuit, 19.20.
...Tri-state address buffer circuit.

Claims (1)

[Claims] 1. In a dual-port memory board, a driver IC for serially wiring the memory signal terminals of the common memory block within the memory block and driving it.
and a damping resistor arranged at both ends of a memory block for each port.