JPH0337733A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To individually test a microcomputer core and a logic circuit part by providing first and second peripheral circuits, first to third signal lines, and a control means. CONSTITUTION:In the test mode of a microcomputer core 2, an input/output circuit 62 is coupled to a port DM1 of the microcomputer 2 by switching circuit 61 and an input/output circuit 72 is coupled to a port DM2 of the microcomputer core 2 by a switching circuit 71. Signals are inputted to and are outputted from the microcomputer core 2 through a signal line LM and a signal line LI. In the test mode of a random logic circuit 3, input/output circuits 62 and 72 are coupled to ports DR2 and DR1 of the random logic circuit 3 by switching circuits 61 and 71 respectively. Signals are inputted to and outputted from the random logic circuit 3 through signal lines LI and LR. Thus, the microcomputer core 2 and the logic circuit part 3 are individually tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an ASIC (integrated circuit for specific applications) using a microcomputer core.

[Prior Art] In recent years, as electronic devices have become more sophisticated, smaller, and cheaper, there has been a growing demand for developing LSIs including microcomputers for each application product. Furthermore, it is required to develop such LSIs quickly and reliably.

An example of a technique for developing an ASIC using a microcomputer as its core is shown in FIG. 16.

This technology uses 20 CPU (central processing unit) cores.
1. ROM (read only memory) 202, RAM
(Random access memory) 203, I/F circuit (interface circuit) 204, timer 205, I10 port (input/output capo)) 206, and bus 207;
A logic circuit 209 specific to the user's system is incorporated into the chip microcomputer 208, and these are integrated on the chip. As shown in Figure 16,
Logic circuit 209 is connected to bus 207 within microcomputer 208 .

Further, as another method for developing an ASIC having a microcomputer as its core (hereinafter referred to as a microcomputer core ASIC), there is an example of a technique shown in FIG. 17. In this technique, a microcomputer chip 301 and a logic circuit chip 302 are placed on a chip 303, and new pads 304 necessary to integrate them into one chip are provided. And microcomputer chip 30
Pad 305 on 1, Pad 3 on logic circuit 302
06 and the newly provided pad 304 to form a single chip.

According to these techniques, a general-purpose microcomputer and a user-specific logic circuit are integrated into one chip, making it easy to downsize the system and reduce costs.

[Problems to be Solved by the Invention] However, in the technology shown in FIG.
In order to incorporate this, layout changes and additions are required, and the entire microcomputer chip 20g is remodeled. Therefore, it takes time for chip development, comprehensive timing verification, test program development, and debugging. In addition, chip development requires
Engineers who are familiar with microcomputer patterns, circuit configurations, timing, testing methods, etc. are required.

Furthermore, test programs, software development/debugging tools, etc. that have already been developed for microcomputer chips cannot be used. Therefore, new test programs, software development/debugging tools, etc. must be developed.

On the other hand, in the technique shown in FIG. 17, multiple chips are integrated into one chip by wiring between them, so pads 3 are placed on each chip 301 and 302.
05, 306, input/output circuits 307, 308, etc. Therefore, pads, driver circuits, etc. are duplicated, resulting in waste and increasing chip size. Also,
Since the microcomputer chip 301 and the logic circuit chip 3.2 cannot be electrically separated, test programs, software development/debugging tools, etc. that have already been developed for microcomputer chips or logic circuit chips are used. Can not do it. Therefore, new test programs, software development/debugging tools, etc. must be developed.

An object of the present invention is to provide a semiconductor integrated circuit device that can realize a microcomputer core ASIC in a short time with less development effort and cost.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on a chip, which includes a microcomputer core including a central processing unit and a storage device, and a microcomputer a logic circuit section controlled by the core, a first peripheral circuit, a second peripheral circuit, a first signal line,
It includes a second signal line, a third signal line, and control means.

the first peripheral circuit includes a pad and driver means;
Manually output or output signals to the microcomputer core or logic circuit section. The second peripheral circuit includes pads and driver means, and outputs or outputs signals to the microcomputer core or logic circuit section. The first signal line is connected to the microcomputer core. The second signal line is connected to the logic circuit section. The third signal line is connected between the microcomputer core and the logic circuit section. The control means selectively couples the first signal line or the third signal line to the first peripheral circuit, and selectively couples the second signal line or the third signal line to the second peripheral circuit. combine.

[Function] During normal operation, the control means causes the first signal line to
and the second signal line is coupled to the second peripheral circuit, signals are input/output to and from the microcomputer core via the first peripheral circuit and the first signal line, Signals are input to and output from the logic circuit section via the second peripheral circuit and the second signal line.

During testing of the microcomputer core, the first signal line is coupled to the first peripheral circuit and the third signal line is coupled to the first peripheral circuit by the control means.
When the signal line is coupled to the second peripheral circuit, the signal is input/output to and from the microcomputer core via the first peripheral circuit and the first signal line, and Signals are input to and output from the microcomputer core through the signal lines.

When testing the logic circuit section, the third signal line is coupled to the first peripheral circuit and the second signal line is coupled to the second peripheral circuit by the control means.
when coupled to the first peripheral circuit and the third peripheral circuit.
A signal is output to the logic circuit section via the signal line, and a signal is output to the logic circuit section via the second peripheral circuit and the second signal line.

In this manner, during testing, signals can be output to the microcomputer core or the logic circuit section via the signal line connected between the microcomputer core and the logic circuit section.

According to this invention, the microcomputer core and logic circuit section can be tested individually, so test programs and software development/debugging tools that have already been developed for general-purpose microcomputers and logic circuits can be used. can do.

Further, the pads and driver means are not included in the microcomputer core and the logic circuit section, and the pads and driver means are not included in the first and second
Since the chip is included in the peripheral circuit of the chip, the chip size is smaller than the conventional example. Furthermore, - the logic circuit section can be designed according to specifications without changing or adding to the layout of the microcomputer core.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. A microcomputer core (or microcomputer unit core; hereinafter referred to as microcomputer core) 2 and a random logic circuit 3 are provided on a semiconductor chip 1 . A common common terminal circuit 4, a selection common terminal circuit 5, a dedicated terminal circuit 6 for the microcomputer core, a dedicated terminal circuit 7 for the random logic circuit, and selection dedicated terminal circuits 6a and 7a are provided on the periphery of the semiconductor chip 1. It is being Further, a mode setting signal generation circuit 8 and a mode signal input circuit 9 are provided on the semiconductor chip 1.

As shown in FIG. 2, the microcomputer core 2 is a CPU core 2
1, ROM 22, RAM 23, I/F circuit 24, timer 25, I10 board 26, and bus 27, but does not include input/output circuits such as human output drivers and pads.

The random logic circuit 3 is a logic circuit composed of various gates, counters, flip-flops, etc., and is designed according to specifications for a specific application.

Next, referring to FIG. 3, the common terminal circuit 4 is normally coupled to the microcomputer core 2 and the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The selective common terminal circuit 5 is normally fixedly coupled to either the microcomputer core 2 or the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The dedicated terminal circuit 6 is fixedly coupled only to the microcomputer core 2, and the dedicated terminal circuit 7 is fixedly coupled only to the random logic circuit 3. Microcomputer core 2
and the random logic circuit 3 are mutually coupled by a signal line LI.

The selection-only terminal circuit 6a is connected to the microcomputer core 2 and the signal line L.
The selection-only terminal circuit 7a is coupled to the random logic circuit 3 and the signal line LI.

The mode signal input circuit 9 is configured to operate the semiconductor integrated circuit device in a normal mode and a test mode of the microcomputer core 2 (hereinafter referred to as M
A mode signal for setting the random logic circuit 3 to a test mode (hereinafter referred to as an R/L test mode) is provided. In response to the output of the mode signal input circuit 9, the mode setting signal generation circuit 8 outputs the common terminal circuit 4 and the selected common terminal circuit 5.
Give a mode setting signal to.

FIG. 4 is a block diagram showing the configurations of the common terminal circuit 4 and the selective common terminal circuit 5. As shown in FIG. Common shared terminal circuit 4
consists of a switching circuit 41 and an input/output circuit 42, and the selection common terminal circuit 5 similarly consists of a switching circuit 51 and an input/output circuit 52. The switching circuit 41 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal line LR. Similarly, the switching circuit 51 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal IJLR. Furthermore, a mode setting signal is applied to the switching circuit 41 and the switching circuit 51 from the mode setting signal generation circuit 8 via the signal line LC.

5A, 5B, and 5C are schematic diagrams for explaining the functions of the common terminal circuit 4. FIG.

In the normal mode, the input/output circuit 42 is coupled to the microcomputer core 2 and the random logic circuit 3 by the switching circuit 41, as shown in FIG. 5A.

In the MCU test mode, as shown in FIG. 5B, the input/output circuit 42 is switched to the microcomputer core 2 by the switching circuit 41.
is combined with In R/L test mode, the 5th C
As shown in the figure, an input/output circuit 42 is coupled to the random logic circuit 3 by a switching circuit 41.

FIG. 6 is a schematic diagram for explaining the function of the selection common terminal circuit 5. In the normal mode, as shown in FIG. 6, the input/output circuit 52 is fixedly coupled to either the microcomputer core 2 or the random logic circuit 3 by the changeover switch 51.

Which of the microcomputer core 2 and the random logic circuit 3 it is coupled to is determined by the specifications of the semiconductor integrated circuit device.

In the MCU test mode, as in the case of the common terminal circuit 4, the input/output circuit 52 is coupled to the microcomputer core 2 by the switching circuit 51. Also in the R/L test mode, the input/output circuit 52 is coupled to the random logic circuit 3 by the switching circuit 51, as in the case of the common terminal circuit 4.

FIG. 7 is a diagram showing the configuration of mode setting signal generation circuit 8 and mode signal input circuit 9. Mode signal input circuit 9
includes pads 91.92 and input buffers 93.94. Mode setting signal generating circuit 8 is supplied with mode signal φ0 via pad 91 and input buffer 93, and mode signal φ1 via pad 92 and manual buffer 94. The mode setting signal generation circuit 8 is
Mode setting signal TN based on mode signal φO1φ1,
Generates TM and TR. The mode setting signal TN is active in the normal mode, the mode setting signal TM is active in the MCU test mode, and the mode setting signal TR is active in the R/L test mode.

FIG. 8 is a diagram showing the configuration of the signal lines in detail.

The signal line LM consists of a data line for transmitting output data DOM, a data line for transmitting manual data DIM, and a control line for transmitting control signal CM. This signal line LM is connected to the I10 port 26 (second
(see figure).

The signal line LR includes a data line for transmitting output data DOR, a data line for transmitting input data DIR, and a control line for transmitting control signal CR. Further, the signal line LC includes three signal lines for transmitting mode setting signals TN, TM, and TR.

FIG. 9 is a diagram showing the configuration of the common shared terminal circuit 4. The input/output circuit 42 includes a pad 43 and an output driver 44.

In the normal mode, the mode setting signal TN becomes active. Thereby, the switching circuit 41 controls the control signals CM, C
one of R and output data DOM.

One side of DOR is provided to output driver 44. The output driver 44 outputs output data to the pad 43 in response to the control signal.

In the MCU test mode, the mode setting signal TM becomes active. Thereby, the switching circuit 41 receives the control signal C.
M and output data DOM are provided to the output driver 44. The output driver 44 outputs output data DOM to the pad 43 in response to the control signal CM.

In the R/L test mode, the mode setting signal TR becomes active. Thereby, the switching circuit 41 receives the control signal C.
R and output data DOR are provided to the output driver 44. The output driver 44 outputs output data DOR to the pad 43 in response to the control signal CR.

Further, input data DIM is inputted from the pad 43 to the microcomputer core 2, and input data DIR is inputted from the pad 43 to the random logic circuit 3.

The configuration of the selection common terminal circuit 5 is also similar to the configuration shown in FIG. However, in the selection common terminal circuit 5, the output data DOM is output in the normal mode.

Predetermined output data of the DOR is always output.

FIG. 10 is a diagram showing the configuration of the dedicated terminal circuit 6. Dedicated terminal circuit 6 includes a pad 61 and an output driver 62. The output driver 62 is provided with a control signal CM and output data DOM. In addition, human data DIM is manually input from the pad 61 .

The configuration of the dedicated terminal circuit 7 is also similar to the configuration of the dedicated terminal circuit 6.

FIG. 11 is a schematic diagram showing the configuration of the selection-only terminal circuits 6a and 7a, and FIG. 12 is a diagram showing a truth table for explaining their operations.

The selection-only terminal circuit 6a includes a switching circuit 61 and an input/output circuit 62. The selection-only terminal circuit 7a includes a switching circuit 71 and an input/output circuit 72. Signal line LM is microcomputer core 2
The signal line LR is connected to the boat DR1 of the random logic circuit 3, and the signal line Ll is connected to the boat DM2 of the microcomputer core 2 and the random logic circuit 3.
is connected between the boats DR2 and DR2.

The switching circuit 61 selectively couples the input/output circuit 62 to the signal line LM or the signal line Ll. The switching circuit 71 selectively couples the input/output circuit 72 to the signal line LR or the signal line Ll.

FIG. 12 shows that the switching circuits 61, 71 are set to boat DMI, DM2, . This indicates which of DRI and DR2 is to be selected. As shown in the figure, in normal mode,
The switching circuit 61 couples the input/output circuit 62 to the boat DMI of the microcomputer core 2 , and the switching circuit 71 couples the input/output circuit 72 to the boat DRI of the random logic circuit 3 .

In the MCU test mode, the input/output circuit 62 is coupled to the boat DM1 of the microcomputer core 2 by the switching circuit 61,
The input/output circuit 72 is coupled to the port DM2 of the microcomputer core 2 by the switching circuit 71.

As a result, signals are input and output to and from the microcomputer core 2 via the signal line LM and the signal line Ll.

In the R/L test mode, the switching circuit 61 couples the input/output circuit 62 to the port DR2 of the random logic circuit 3, and the switching circuit 71 couples the input/output circuit 72 to the port DR1 of the random logic circuit 3. As a result, a signal is outputted to the random logic circuit 3 via the signal line Ll and the signal line LR.

FIG. 13 is a diagram showing a detailed configuration of the selection-only terminal circuits 6a and 7a, and FIG. 14 is a diagram showing a truth table for explaining the operation of the circuit of FIG. 13.

In FIG. 13, pad PM and output driver G1
constitutes an input/output circuit 62, and pad PR and output driver G2 constitute an input/output circuit 72. Further, selectors 5ELL to 5EL7 constitute a switching circuit 61.71.

The switching signal generation circuit 65 generates mode setting signals TN, TM,
In response to TR, switching signals 81-S7 are generated. Selectors SELI~5EL7 each receive switch signals 81~
It is switched in response to S7.

Figure 14 shows selectors 5ELI to 5EL7 depending on the mode.
represents which of the respective terminals A and B is selected. As shown in the figure, selectors 5ELI, 5EL2, 5EL4 to 5EL7 are switched to the terminal A side in the normal mode. When port DM2 is an output port and boat DR2 is a human-powered boat, selector 5EL
3 is switched to the A side. As a result, the output driver G
1 is the control signal CM from the boat DMI of microcomputer core 2.
I and output data DOMI are applied, and a control signal CRI and output data DOR1 are applied from port DR1 of random logic circuit 3 to output driver G2.

On the other hand, output data DOM2 from port DM2 of microcomputer core 2 is input to boat DR2 of random logic circuit 3 as human input data DIR2.

Conversely, boat) DM2 is a human-powered boat, and boat DR2 is a human-powered boat.
When is the output port, the selector 5EL3 is switched to the terminal B side. In this case, the output data DOR2 from the boat DR2 of the random logic circuit 3 is inputted to the boat DM2 of the microcomputer core 2 as human data DIM2.

In MCU test mode, selector 5ELI.

5EL3 and 5EL6 are switched to the terminal A side, and selectors 5EL2, 5EL4, and 5EL7 are switched to the terminal B side. The selector 5EL5 may be switched to either terminal A or terminal B.

As a result, output driver G1 receives control signal CMI and output data DOM from boat DMI of microcomputer core 2.
is applied to the output driver G2, and a control signal CM is supplied from the port DM2 of the microcomputer core 2 to the output driver G2.

2 and output data DOM2 are given.

In R/L test mode, selector 5ELI.

5EL3, 5EL5.5EL6 are switched to the terminal B side, and selectors 5EL2.5EL7 are switched to the terminal A side. The selector 5EL4 may be switched to either terminal A or terminal B.

As a result, the output driver G1 is given the control signal CR2 and the output data DOR2 from the boat DR2 of the random logic circuit 3, and the output driver G2 is given the control signal CRI and the output data DOR1 from the boat DRI of the random logic circuit 3. .

Next, the operation of the semiconductor integrated circuit device of this embodiment will be explained.

In the normal mode, the common terminal circuit 4 is commonly used by the microcomputer core 2 and the random logic circuit 3, and signals are input and output to and from the microcomputer core 2 and the random logic circuit 3 via the common terminal circuit 4. Ru. Further, signals are input/output to the microcomputer core 2 via the dedicated terminal circuit 6 and the selection-only terminal circuit 6a, and signals are input to/out of the random logic circuit 3 via the dedicated terminal circuit 7 and the selection-only terminal circuit 7a. Output. When the selective common terminal circuit 5 is coupled to the microcomputer core 2, a signal is outputted to the microcomputer core 2 via the selective common terminal circuit 5. Conversely, when the selection common terminal circuit 5 is coupled to the random logic circuit 3, a signal is outputted to the random logic circuit 3 via the selection common terminal circuit 5.

In the MCU test mode, the common shared terminal circuit 4 and the selected shared terminal circuit 5 are coupled only to the microcomputer core 2. Also, a selection-only terminal circuit 6a.

7a is coupled to the microcomputer core 2. In this case, a test signal is outputted to the microcomputer core 2 via the common terminal circuit 4, the selective common terminal circuit 5, the dedicated terminal circuit 6, or the selective terminal circuits 6a and 7a.

In the R/L test mode, the common terminal circuit 4 and the selection terminal circuit 5 are coupled only to the random logic circuit 3. Also, the selection-only terminal circuits 6a and 7a are coupled to the random logic circuit 3. In this case, "common"
(Surrounding terminal circuit 4, selection common terminal circuit 5, dedicated terminal circuit 7
Alternatively, a test signal is outputted to the random logic circuit 3 via the selection-only terminal circuits 6a and 7a.

As mentioned above, even if the configuration has internal wiring that does not require terminals in normal mode, such as the signal line Ll between port DM2 of microcomputer core 2 and port DR2 of random logic circuit 3, the number of terminals can be reduced. Both the MCU test and the R/L test can be performed without any increase. in this way,
Since each of the microcomputer core 2 and random logic circuit 3 can be tested individually, test programs and software development/debugging tools that have already been developed for general-purpose microcomputers and logic circuits can be used. .

Additionally, pads and drivers are not included in the microcomputer core 2 and the random logic circuit 8, but are included in the common shared terminal circuit 4, selection shared terminal circuit 5, dedicated terminal circuit 6.7, and selection dedicated terminal circuits 6a and 7a. This reduces the chip size.

Furthermore, the configuration of the random logic circuit 3 can be designed according to specifications without changing or adding to the layout of the microcomputer core 2.

Next, an example of use of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.

Normally, arithmetic processing is performed in the microcomputer core 2,
The random logic circuit 3 performs high-speed processing that cannot be processed by the microcomputer core 2.

For example, if the random logic circuit 3 is designed to be a general-purpose bus controller, the dedicated terminal circuit 7
Alternatively, a plurality of personal computers 101 and disk devices 10 are connected to the selection-only terminal circuit 7a via the bus 100.
6 etc. will be connected.

Furthermore, the random logic circuit 3 is configured to control a specific control target 102.
If it is designed to be a dedicated controller for
The controlled object 102 is connected to the dedicated terminal circuit 7 or the selection dedicated terminal circuit 7a.

For example, an external memory 103 is connected to the common terminal circuit 4. For example, the selection common terminal circuit 5 includes a CPU 10.
4 is connected, and a disk controller 105, for example, is connected to the dedicated terminal circuit 6 or the selection dedicated terminal circuit 6a. The selective common terminal circuit 5 can also be coupled to the random logic circuit 3 according to the user's order.

As mentioned above, according to this embodiment, the microcomputer core ASC
I can be realized at low cost and in a short period of time with little development effort.

[Effects of the Invention] As described above, according to the present invention, test programs and software development/debugging tools that have already been developed for microcomputers or logic circuits can be used. Moreover, it is possible to input and output test signals to and from the microcomputer core or the logic circuit section via the signal line connected between the microcomputer core and the logic circuit section without increasing the number of terminals.

In addition, the chip size is reduced, and the logic circuit section can be easily designed according to the user's requirements even if one is not familiar with microcomputer patterns, circuit configurations, timing, testing methods, and the like.

Therefore, it is possible to realize an ASIC using a microcomputer in a short period of time and with less development effort and cost.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a functional block diagram showing the configuration of the same embodiment. FIG. 3 is a schematic diagram for explaining the features of the main parts of the embodiment. FIG. 4 is a block diagram showing the configuration of the common shared terminal circuit and the selected shared terminal circuit. 5A, 5B, and 5C are schematic diagrams for explaining the functions of the common shared terminal circuit, with FIG. 5A showing the normal mode, FIG. 5B showing the MCU test mode, and FIG. Figure 5C is a diagram showing the R/L test mode. FIG. 6 is a schematic diagram for explaining the function of the selective common terminal circuit. FIG. 7 is a diagram showing the configuration of a mode setting signal generation circuit and a mode signal input circuit. FIG. 8 is a diagram showing a specific configuration of signal lines. FIG. 9 is a diagram showing the configuration of the common shared terminal circuit. FIG. 10 is a diagram showing the configuration of the dedicated terminal circuit. 11th
The figure is a diagram showing the configuration of a selection-only terminal circuit. FIG. 12 is a diagram for explaining the operation of the selection-only terminal circuit of FIG. 11. FIG. 13 is a diagram showing a detailed configuration of the selection-only terminal circuit of ¥511. FIG. 14 is a diagram for explaining the operation of the selection-only terminal circuit of FIG. 13. FIG. 15 is a diagram for explaining an example of use of the embodiment. Figure 16 shows a conventional microcomputer core ASIC.
It is a top view showing an example. FIG. 17 is a functional block diagram showing another example of a conventional microcomputer core ASIC. In the figure, 1 is a semiconductor chip, 2 is a microcomputer core, 3 is a random logic circuit, 4 is a common shared terminal circuit, 5 is a selection shared terminal circuit, 6.7 is a dedicated terminal circuit, and 6a and 7a are selection only terminal circuits. , 8 is a mode setting signal generation circuit, and 9 is a mode signal input circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device formed on a chip, comprising: a microcomputer core including a central processing unit and a storage device; a logic circuit section controlled by the microcomputer core; pads and drivers. a first peripheral circuit for inputting or outputting a signal to or from the microcomputer core or the logic circuit unit; and a first peripheral circuit for inputting or outputting a signal to the microcomputer core or the logic circuit unit; a second peripheral circuit for inputting or outputting, a first signal line connected to the microcomputer core, a second signal line connected to the logic circuit section, the microcomputer core and the logic circuit section. selectively coupling a third signal line connected therebetween and the first signal line or the third signal line to the first peripheral circuit;
A semiconductor integrated circuit device, comprising control means for selectively coupling the second signal line or the third signal line to the second peripheral circuit.