JPH01241848A - Ic device - Google Patents

Ic device

Info

Publication number
JPH01241848A
JPH01241848A JP63070059A JP7005988A JPH01241848A JP H01241848 A JPH01241848 A JP H01241848A JP 63070059 A JP63070059 A JP 63070059A JP 7005988 A JP7005988 A JP 7005988A JP H01241848 A JPH01241848 A JP H01241848A
Authority
JP
Japan
Prior art keywords
chip
package
noise
ferrite
magnetic material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63070059A
Other languages
Japanese (ja)
Inventor
Satoshi Asanuma
智 浅沼
Kenji Sunochi
須之内 建史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63070059A priority Critical patent/JPH01241848A/en
Publication of JPH01241848A publication Critical patent/JPH01241848A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To attenuate radiation noise from an IC chip by a shielding effect, by sealing the chip with a package formed of a magnetic material and by making it operate as an inductor against conduction noise transferred through the leads of the IC to attenuate the noise. CONSTITUTION:A package 20 formed fo an upper package section 21 and a lower package section 22 is formed of a magnetic material made of ferrite or the like. Since the lead pins 13 of an IC chip 12 are surrounded with ferrite, they operate as inductors against a high frequency signal and a conduction noise. Since the IC 12 of an IC chip 11 is enclosed wholly with a magnetic material, its radiation noise is shielded. Thus, the IC package is composed of ferrite thereby to remove or suppress all the conduction noise, radiation noise by the mounted IC package itself.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路(以下Integrated cl
r −ault −I C−という。)チップに対する
電磁妨害ノイズを低減させるために磁性材料により形成
するようにして電磁妨害対策を施したIC装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to integrated circuits (hereinafter referred to as integrated circuits).
It is called r-ault-IC-. ) The present invention relates to an IC device which is made of a magnetic material to reduce electromagnetic interference noise to the chip and which takes measures against electromagnetic interference.

従来の技術 一般に、半導体等の材料を中心に用いて、アナログ、デ
ィジタル又は両者を混成した各揮電気回路を集積化して
構成したIC装置が多用されている。このIC装置は、
基板(ウェハ)上に各種回路を形成した後、ICチップ
に細かく切断して構成している。IC装置の機能そのも
のは、この121\ 。
2. Description of the Related Art In general, IC devices are often used, which are constructed by integrating analog, digital, or a combination of both volatile electrical circuits mainly using materials such as semiconductors. This IC device is
Various circuits are formed on a substrate (wafer) and then cut into small pieces to form IC chips. The function of the IC device itself is this 121\.

Cチップにより達成し得るが、実用上の便宜からこのI
Cチップをプラスチック、セラミック等のパッケージに
より包込むことによって実装してIC装置としている。
This can be achieved with a C chip, but for practical convenience, this I
An IC device is produced by packaging a C chip in a package made of plastic, ceramic, or the like.

このIC装置は、やはりその用途9機能に応じて、幾つ
かの種類に分けられる。
This IC device can be divided into several types depending on its intended use9 function.

例えば、パッケージの両側にリードが2列に並んで設け
られている所謂D I P (dual−In−11n
apackage)や、パッケージの片側にリードが1
列だけ設けられている所謂S I P (single
−In −目ne package)等種々のものが実
用化されている。
For example, a so-called DIP (dual-In-11n) has leads arranged in two rows on both sides of the package.
apackage) or one lead on one side of the package.
The so-called S I P (single
-In -Package) and various other products have been put into practical use.

現在、上記ICチップやリードを実装しておくパッケー
ジは、プラスチック或はセラミック等の材料により形成
されている。ところで、通常のプラスチック、セラミッ
ク等には電磁機器より発生するノイズ等の電磁妨害波を
防止する作用はない。
At present, packages in which the above-mentioned IC chips and leads are mounted are made of materials such as plastic or ceramic. By the way, ordinary plastics, ceramics, etc. do not have the effect of preventing electromagnetic interference waves such as noise generated from electromagnetic equipment.

この電磁妨害波は、上記ICのリードピンより輻射され
る伝導ノイズや上記10チツプより輻射されるノイズ等
よりなっている。この輻射という概念はIcリードピン
又はチップを中心にして1点から回りに向かって、ノイ
ズ等が放射されることをいう。そこで、ICチップ又は
リード等から放射される前記電磁妨害波は、フェライト
ビーズ等を用いて、その輻射・放射等を防止・除去して
いる。
This electromagnetic interference consists of conduction noise radiated from the lead pins of the IC, noise radiated from the 10 chips, and the like. The concept of radiation refers to the fact that noise and the like are radiated from one point around the Ic lead pin or chip. Therefore, the electromagnetic interference waves emitted from IC chips, leads, etc. are prevented and removed using ferrite beads and the like.

第6図は従来の電磁妨害波の防止対策の一例を示す等価
回路図であり、同図において、1はIC装置、2は、I
C装置1を構成するICチップ、3は、IC装置1内に
設けられ、ICチップ2とリードとの間に設けられたフ
ェライトビーズである。このフェライトビーズ3により
高周波ノイズに対するインピーダンスを持たせ、リード
ピンから放射される電磁妨害波を防止している。
FIG. 6 is an equivalent circuit diagram showing an example of conventional electromagnetic interference prevention measures. In the figure, 1 is an IC device, 2 is an I
The IC chip 3 constituting the C device 1 is a ferrite bead provided within the IC device 1 and between the IC chip 2 and the leads. The ferrite beads 3 provide impedance against high frequency noise and prevent electromagnetic interference waves radiated from the lead pins.

また、上記フェライトビーズを用いる以外にも第7図に
示すようにICチップ2とIC装置1の出力端子等の間
に、CR回路より成る低域通過フィルタ(LPF)5を
介挿し伝導ノイズを減衰させる方法もある。
In addition to using the above-mentioned ferrite beads, a low-pass filter (LPF) 5 made of a CR circuit is inserted between the IC chip 2 and the output terminal of the IC device 1 as shown in FIG. There are also ways to attenuate it.

さらに、上述した電磁妨害波の輻射に基づく輻射ノイズ
に対しては第8図に示すように、IC全体を板金等によ
りシールドすることで輻射ノイズを減衰させている。第
8図においてICチップ(図示せず)を実装したIC装
置1の上部側より、板金等により成るシールドケース6
をかぶせて、このシールドケース6を接地している。尚
、符号7はIC装置1のパンケージの両側より突出する
リードピンであり、符号8はシールドケース6の下端に
複数設けられた固定用の爪である。
Furthermore, as shown in FIG. 8, the radiation noise due to the radiation of the electromagnetic interference waves described above is attenuated by shielding the entire IC with a sheet metal or the like. In FIG. 8, a shield case 6 made of sheet metal or the like is viewed from the upper side of the IC device 1 on which an IC chip (not shown) is mounted.
This shield case 6 is grounded by covering it. Note that the reference numeral 7 is a lead pin protruding from both sides of the pan cage of the IC device 1, and the reference numeral 8 is a plurality of fixing claws provided at the lower end of the shield case 6.

発明が解決しようとする課題 しかしながら、従来のIC装置によれば、ICチップに
リードピンを接続し、通常のプラスチックまたはセラミ
ックからなるパッケージ内にこれらICチップを実装し
ただけでは電磁妨害波の抑制又は除去は行ない得ないと
いう問題があった。
Problems to be Solved by the Invention However, according to conventional IC devices, electromagnetic interference cannot be suppressed or eliminated simply by connecting lead pins to IC chips and mounting these IC chips in a package made of ordinary plastic or ceramic. The problem was that it could not be done.

また、ICチップの各ピンから放出される伝導ノイズを
抑えるためには、ICチップからの信号線にフェライト
ビーズ等を取り付けたりCR回路等より成るLPFを設
けたりしなければならず、さらにICパッケージからの
輻射ノイズを抑えるためには、ICC10ケージ全体を
シールドしなけ5 /・ 7 ればならず、ICパッケージ以外の対策部品が必要とな
るという問題もあった。
In addition, in order to suppress conduction noise emitted from each pin of the IC chip, it is necessary to attach ferrite beads or the like to the signal line from the IC chip, or to install an LPF consisting of a CR circuit, etc. In order to suppress the radiated noise from the ICC10 cage, the entire ICC10 cage must be shielded5/7, and there is also the problem that countermeasure components other than the IC package are required.

本発明は、このような従来の問題を解決するものであり
、ICチップの回路に変更を加えないでICチップ自身
またはリードピンから発生する電磁妨害波を低減させる
ことを目的とするものである。
The present invention is intended to solve such conventional problems, and aims to reduce electromagnetic interference waves generated from the IC chip itself or lead pins without making any changes to the circuit of the IC chip.

課題を解決するための手段 本発明は、上記目的を達成するために、ICパッケージ
そのものをフェライト等の磁性材料により構成し、この
磁性ICパッケージ内にICチップを実装するようにし
たものである。
Means for Solving the Problems In order to achieve the above object, the present invention is such that the IC package itself is made of a magnetic material such as ferrite, and the IC chip is mounted within this magnetic IC package.

作  用 本発明は上記のように構成することにより、磁性材料よ
り成るICパッケージが伝導ノイズに対してはインダク
タンス成分として作用し、輻射ノイズに対してはパッケ
ージそのものがシールド材として作用することになる。
Function: By configuring the present invention as described above, the IC package made of magnetic material acts as an inductance component against conducted noise, and the package itself acts as a shielding material against radiated noise. .

従って、伝導ノイズ及び輻射ノイズ共に減衰させること
ができ、電磁妨害波の低減または除去を行なうことがで
きる。
Therefore, both conduction noise and radiation noise can be attenuated, and electromagnetic interference waves can be reduced or eliminated.

61\ 7 実施例 以下、第1図乃至第5図を用いて、本発明の実施例につ
いて説明する。第1図は、本発明の一実施例を示す分解
斜視図であり、同図において、IC装置10は、上パッ
ケージ部21と下パッケージ部22との間にICチップ
12を挾んで接着等により一体化している。このICチ
ップ12の電極はボンディング用ワイヤ14を介してリ
ードピン13に接続されている。
61\7 Embodiments Hereinafter, embodiments of the present invention will be described using FIGS. 1 to 5. FIG. 1 is an exploded perspective view showing one embodiment of the present invention. In the figure, an IC device 10 is shown with an IC chip 12 sandwiched between an upper package part 21 and a lower package part 22 by adhesive or the like. It is integrated. The electrodes of this IC chip 12 are connected to lead pins 13 via bonding wires 14.

第2図において、前記上パッケージ部21の下面21a
側には前記ICチップ12等を収納し得る凹部23とこ
の凹部23より前記リードピン13の幅及び数に対応し
て形成された平行する複数の溝部24・・とが形成され
ている。下パッケージ部22の上面22aの周縁部は前
記ICチップ12等に対応して接着剤塗布面22aと成
っている。上パッケージ部21の下面21aの周縁部と
下パッケージ部22の上面22a(周縁部)とは、互い
に、密着可能な接合面となっており、これら上パッケー
ジ部21.下パッケージ部22より成7へ、ノ るパッケージ部20は、例えばフェライト等より成る磁
性材料により形成されている。
In FIG. 2, the lower surface 21a of the upper package part 21
A recess 23 capable of accommodating the IC chip 12 and the like, and a plurality of parallel grooves 24 formed from the recess 23 in correspondence with the width and number of the lead pins 13 are formed on the side. The peripheral edge of the upper surface 22a of the lower package portion 22 forms an adhesive-applied surface 22a corresponding to the IC chip 12 and the like. The peripheral edge of the lower surface 21a of the upper package part 21 and the upper surface 22a (peripheral edge) of the lower package part 22 are joint surfaces that can be brought into close contact with each other. The package part 20 extending from the lower package part 22 to the structure 7 is made of a magnetic material such as ferrite.

上記構成に基づ<ICパッケージの組み立て動作につい
て説明する。ICチップ12は、その電極と、先端側を
カットされる前のリードピン13とをワイヤ14により
ボンディングされる。このICチップ12等を図示しな
い接着剤を上面22aに塗布した下パッケージ部22上
に載置し、凹部23にも接着剤を塗布した上パ・ノケー
ジ部21を被せて上下より押さえ付けることによりIC
装置1oが一体化して完成される。この時、上下パンケ
ージ部21.22の接合面21a、22aは、予め平坦
に加工されているので、互いに面接触するようになって
いる。このようにして接合されたIC装置10は、所定
の工程によりリードピン13を下側に折り曲げた後、同
じ長さとなるようにカットさせることにより、第3図に
示すような完成されたIcパッケージ1oとなる。この
時、Icチップ11のリードピン13 は第4図に示す
ように、フェライトより成るパッケージ部2゜で囲まれ
ることになる。
Based on the above configuration, the assembly operation of the IC package will be explained. The electrodes of the IC chip 12 are bonded to the lead pins 13 whose tips have not yet been cut using wires 14 . By placing the IC chip 12 and the like on the lower package part 22 whose upper surface 22a is coated with an adhesive (not shown), and by covering the recessed part 23 with the upper package part 21 coated with adhesive and pressing it from above and below. IC
The device 1o is integrated and completed. At this time, the joint surfaces 21a and 22a of the upper and lower pancage parts 21, 22 are processed to be flat in advance, so that they come into surface contact with each other. The IC device 10 bonded in this way is assembled into a completed IC package 10 by bending the lead pins 13 downward in a predetermined process and cutting them to the same length. becomes. At this time, the lead pins 13 of the Ic chip 11 are surrounded by the package portion 2° made of ferrite, as shown in FIG.

次に、第5図を用いてこの実施例の電気的作用を説明す
る。上記のように、ICチップ12のリードピン13は
フェライトで囲まれているため、高周波信号及び伝導ノ
イズに対しては、インダクタとして作用することとなる
。またICチップ11のIC12は磁性体により全体を
包囲されているので輻射ノイズをシールドすることとな
る。
Next, the electrical operation of this embodiment will be explained using FIG. 5. As described above, since the lead pins 13 of the IC chip 12 are surrounded by ferrite, they act as an inductor against high frequency signals and conduction noise. Furthermore, since the IC 12 of the IC chip 11 is entirely surrounded by a magnetic material, radiation noise is shielded.

このように、ICパンケージをフェライトにより構成す
ることにより、伝導ノイズ、輻射ノイズの何れをも実装
されたICパッケージ自身により除去または抑制するこ
とができる。
By configuring the IC pancake with ferrite in this way, both conduction noise and radiation noise can be removed or suppressed by the mounted IC package itself.

発明の効果 本発明は上記実施例より明らかなように、下記に示す効
果を有する。
Effects of the Invention As is clear from the above examples, the present invention has the following effects.

ICパッケージを磁性材料で作ることにより、ICリー
ド及びチップが磁性材料で囲われる。そのため、 (1)ICのリード部を伝わる伝導ノイズに対し、イン
ダクタとして作用しノイズを減衰させること9−・−/
゛ ができる。
By making the IC package from magnetic material, the IC leads and chip are surrounded by magnetic material. Therefore, (1) To act as an inductor and attenuate the conduction noise transmitted through the IC leads9-・-/
゛ can be done.

(2)Icチップからの輻射ノイズはシールド作用によ
り減衰させることができる。
(2) Radiation noise from the Ic chip can be attenuated by shielding.

このように、Icチップの回路変更無しにICパッケー
ジの材質を磁性材料とすることで、電磁妨害波を低減す
ることができる。
In this way, electromagnetic interference waves can be reduced by using a magnetic material as the material of the IC package without changing the circuit of the IC chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る電磁妨害対策用1c装置の一実施
例を示す分解斜視図、第2図は、第1図のパンケージ部
を示す一部展開斜視図、第3図は、第1図のIc装置の
完成体を示す斜視図、第4図は、同じくパッケージ部に
よるシールド状態を示す平面図、第5図はこの発明の電
気的作用を説明する等価回路図、第6図はフェライトビ
ーズを用いた従来のIc装置を示す等価回路図、第7図
は、CR回路を用いた従来のIC装置を示す等価回路図
、第8図は、シールドケースを用いた従来のIC装置を
示す斜視図である。 10−=・I C装置、12−・−I Cチップ、13
・・・・・リードピン、2o ・・・磁性パッケージ部
、101\−ノ 21・・・・・上パッケージ部、22・・・・・下パッ
ケージ部、21a、22b・・・・・・接合面。 代理人の氏名 弁理士 中 尾 敏 男 はか1名C)
 Q l 、j O/ dQ℃ 1−11−1づ還−L−I塘勝
FIG. 1 is an exploded perspective view showing one embodiment of the electromagnetic interference countermeasure 1c device according to the present invention, FIG. 2 is a partially exploded perspective view showing the pan cage part of FIG. 1, and FIG. FIG. 4 is a plan view showing the shielded state of the Ic device shown in FIG. 4, FIG. 5 is an equivalent circuit diagram illustrating the electrical operation of the present invention, and FIG. Fig. 7 is an equivalent circuit diagram showing a conventional IC device using beads, Fig. 7 is an equivalent circuit diagram showing a conventional IC device using a CR circuit, and Fig. 8 is a conventional IC device using a shield case. FIG. 10-=・IC device, 12-・-IC chip, 13
...Lead pin, 2o...Magnetic package part, 101\-No21...Top package part, 22...Lower package part, 21a, 22b...Bonding surface . Name of agent: Patent attorney Toshio Nakao (1 person)
Q l , j O/ dQ℃ 1-11-1 zu return-L-I Tongsheng

Claims (1)

【特許請求の範囲】[Claims]  磁性材料で形成されたパッケージによりICチップを
密封したことを特徴とするIC装置。
An IC device characterized in that an IC chip is sealed in a package made of a magnetic material.
JP63070059A 1988-03-24 1988-03-24 Ic device Pending JPH01241848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63070059A JPH01241848A (en) 1988-03-24 1988-03-24 Ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63070059A JPH01241848A (en) 1988-03-24 1988-03-24 Ic device

Publications (1)

Publication Number Publication Date
JPH01241848A true JPH01241848A (en) 1989-09-26

Family

ID=13420597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63070059A Pending JPH01241848A (en) 1988-03-24 1988-03-24 Ic device

Country Status (1)

Country Link
JP (1) JPH01241848A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253062A (en) * 1990-03-01 1991-11-12 Mitsubishi Electric Corp Integrated circuit device
JPH0521448U (en) * 1991-08-27 1993-03-19 日本電気株式会社 Package
FR2684804A1 (en) * 1991-12-06 1993-06-11 Thomson Csf DEVICE FOR MOUNTING MICROFREQUENCY MONOLITHIC INTEGRATED CIRCUITS WITH VERY BROADBAND.
JPH062790U (en) * 1992-06-03 1994-01-14 株式会社日本アレフ Detection element
JPH0611396U (en) * 1992-07-15 1994-02-10 北川工業株式会社 IC shield cover
KR100327926B1 (en) * 1993-03-24 2002-06-20 블레이어 에프.모리슨 Integrated Circuit Packaging

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253062A (en) * 1990-03-01 1991-11-12 Mitsubishi Electric Corp Integrated circuit device
JPH0521448U (en) * 1991-08-27 1993-03-19 日本電気株式会社 Package
FR2684804A1 (en) * 1991-12-06 1993-06-11 Thomson Csf DEVICE FOR MOUNTING MICROFREQUENCY MONOLITHIC INTEGRATED CIRCUITS WITH VERY BROADBAND.
US5313693A (en) * 1991-12-06 1994-05-24 Thomson-Csf Device for the mounting of very wide-band microwave integrated circuits
JPH062790U (en) * 1992-06-03 1994-01-14 株式会社日本アレフ Detection element
JPH0611396U (en) * 1992-07-15 1994-02-10 北川工業株式会社 IC shield cover
KR100327926B1 (en) * 1993-03-24 2002-06-20 블레이어 에프.모리슨 Integrated Circuit Packaging

Similar Documents

Publication Publication Date Title
US5225709A (en) Package having a structure for stabilizing and/or impedance-matching a semiconductor IC device accommodated therein
JPH0480950A (en) Semiconductor integrated circuit device
US5949305A (en) Saw filter encapsulated in a ceramic package with capacitance incorporated therein
JP2600366B2 (en) Semiconductor chip mounting method
JPH01241848A (en) Ic device
US6046501A (en) RF-driven semiconductor device
EP0421343A2 (en) Semiconductor element package and semiconductor element package mounting distributing circuit basic plate
US5523641A (en) Surface acoustic wave device
KR100431182B1 (en) Surface acoustic wave device package and method
JPH0214554A (en) Ic package with shield and manufacture thereof
JPH01115145A (en) Resin sealed type integrated circuit
JP2970952B2 (en) Semiconductor device and manufacturing method thereof
JPH1174669A (en) Radio frequency shield electronic circuit board
JP2004023074A (en) Circuit board device and method for manufacturing the same
JPH04146695A (en) Radiation noise reduction method for package and ic package
JPH04263508A (en) Piezoelectric equipment enclosed in case
JPH06252327A (en) Semiconductor package and packaging method for same
JPS6221248A (en) High-speed ic package
JPS63272059A (en) Semiconductor device and module composed of board and semiconductor device mounted on it
JPS6020615A (en) Surface acoustic wave circuit block
JPS633441A (en) Package for integrated circuit
JPH03272159A (en) Ic package
JPH0277191A (en) Package
JPH06169047A (en) Semiconductor device
JPH0364071A (en) Integrated circuit device