JPH0277191A - Package - Google Patents

Package

Info

Publication number
JPH0277191A
JPH0277191A JP63230312A JP23031288A JPH0277191A JP H0277191 A JPH0277191 A JP H0277191A JP 63230312 A JP63230312 A JP 63230312A JP 23031288 A JP23031288 A JP 23031288A JP H0277191 A JPH0277191 A JP H0277191A
Authority
JP
Japan
Prior art keywords
recess
electronic component
cover
substrate
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63230312A
Other languages
Japanese (ja)
Inventor
Yukio Yamaguchi
幸雄 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63230312A priority Critical patent/JPH0277191A/en
Publication of JPH0277191A publication Critical patent/JPH0277191A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent a first electronic component from being touched and damaged by a cover when it is attached to a substrate by packaging the first electronic component in a recess provided in the substrate, attaching the cover so as to cover the recess and packaging a second electronic component on the surface of the substrate around the recess. CONSTITUTION:A substrate 1 is previously provided with a recess 2 deep enough to receive an electronic component completely. A first electronic component 3 such as LSI chip or the like is packaged in the recess 2 by soldering for example. A second electronic component 4 such as a leadless chip carrier or the like is packaged on the surface of the substrate around the recess 2. Since the first electronic component 2 has leads consisting of wire with a diameter of several tens micrometers, at least a cover 5 for mechanical protection is attached to the substrate 1 by means of an adhesive or the like so as to cover the recess 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子装置等に使用される電子部品を実装する
パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for mounting electronic components used in electronic devices and the like.

〔従来の技術〕[Conventional technology]

従来、この種のパッケージは、第３図に示すように、平
板の基板２１にＬＳＩチップなどの第１の電子部品２２
と、リードレスチップキャリア２３などの第２の電子部
品２３をはんだ付けなどにより取付け、さらに第１の電
子部品２２の保護のために枠２４．カバー２５が取付け
られている（例えば、棚橋俊夫等著、ｒＡｃＯｓシステ
ム２０００シリーズのハードウェアテクノロジ」、ｆＮ
ＥＣ技報Ｊ、１９８７年１１月、第４０巻、１１号、７
〜１８ページ）。Conventionally, in this type of package, as shown in FIG. 3, a first electronic component 22 such as an LSI chip is mounted on a flat substrate 21.
A second electronic component 23 such as a leadless chip carrier 23 is attached by soldering or the like, and a frame 24 . Cover 25 is attached (for example, "Hardware Technology of the rAcOs System 2000 Series" by Toshio Tanahashi et al., fN
EC Technical Report J, November 1987, Volume 40, No. 11, 7
~page 18).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のパッケージは、枠２４．カバー２５を後
付けするために、アセンブリ中に第１の電子部品２２に
触り、これをキズ付けやすい欠点があり、部品点数も多
い欠点がある。The conventional package described above has a frame 24. Since the cover 25 is attached later, the first electronic component 22 is easily touched and damaged during assembly, and the number of parts is also large.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のパッケージは、凹みを設けた基板と、前記凹み
内に実装された第１の電子部品と、前記凹みを覆うよう
に前記基板に取付けられるカバーと、前記基板の前記凹
みの周囲の面上に実装された第２の電子部品を含んで構
成される。The package of the present invention includes a substrate provided with a recess, a first electronic component mounted in the recess, a cover attached to the substrate so as to cover the recess, and a surface of the substrate around the recess. It is configured to include a second electronic component mounted thereon.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の一部を破断して示す斜視図
である。第２図は第１図のＸ−Ｘ断面図である。FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention. FIG. 2 is a sectional view taken along line XX in FIG. 1.

第１図及び第２図において、基板１には予め、電子部品
が沈み隠れる深さを有する凹み２が設け′ζあり、ＬＳ
Ｉチップなどの第１の電子部品３が凹み２の中に半田付
は等により実装される。基板１の凹み２の周囲の表面に
はり一ドレスチップキャリアなどの第２の電子部品４が
実装される。第１の電子部品３のリードは直径が数十μ
のワイヤーなどから成るため、少なくとも機械的保護の
ためにカバー５を凹み２を覆うように基板１に接着剤な
どで取付ける。In FIGS. 1 and 2, a substrate 1 is preliminarily provided with a recess 2 deep enough for the electronic components to sink therein, and the LS
A first electronic component 3 such as an I-chip is mounted in the recess 2 by soldering or the like. A second electronic component 4 such as a glue-less chip carrier is mounted on the surface of the substrate 1 around the recess 2 . The lead of the first electronic component 3 has a diameter of several tens of microns.
The cover 5 is attached to the substrate 1 with an adhesive or the like so as to cover the recess 2 at least for mechanical protection.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、基板に設けた凹み内に第
１の部品を設けることにより、部品が凹み内に沈み隠れ
るため基板にカバーを取り付ける時に誤まって第１の電
子部品に触ることが少なくなるという効果がある。また
、カバーを取り付けるだけで第１の部品の周囲にカバー
を設ける必要がなく、部品点数を少くできるという効果
がある。As explained above, in the present invention, by providing the first component in the recess provided in the board, the component sinks into the recess and is hidden, so that it is possible to accidentally touch the first electronic component when attaching the cover to the board. This has the effect of reducing Further, by simply attaching the cover, there is no need to provide a cover around the first component, which has the effect of reducing the number of components.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を一部を破断して示す斜視図
、第２図は第１図のＸ−Ｘ断面図、第３図は従来のパッ
ケージの断面図である。 １．２１・・・基板、２・・・凹み、３，２２・・・第
１の電子部品、４．２３・・・第２の電子部品、５，２
５・・・カバー、２４・・・枠。FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line XX in FIG. 1, and FIG. 3 is a sectional view of a conventional package. 1.21... Board, 2... Recess, 3, 22... First electronic component, 4.23... Second electronic component, 5, 2
5...Cover, 24...Frame.

Claims (1)

【特許請求の範囲】[Claims] 　凹みを設けた基板と、前記凹み内に実装された第１の
電子部品と、前記凹みを覆うように前記基板に取付けら
れるカバーと、前記基板の前記凹みの周囲の面上に実装
された第２の電子部品を含むことを特徴とするパッケー
ジ。a board provided with a recess; a first electronic component mounted in the recess; a cover attached to the board to cover the recess; and a first electronic component mounted on a surface of the board surrounding the recess. A package characterized by containing the electronic components of No. 2.
JP63230312A 1988-09-13 1988-09-13 Package Pending JPH0277191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63230312A JPH0277191A (en) 1988-09-13 1988-09-13 Package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63230312A JPH0277191A (en) 1988-09-13 1988-09-13 Package

Publications (1)

Publication Number Publication Date
JPH0277191A true JPH0277191A (en) 1990-03-16

Family

ID=16905861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63230312A Pending JPH0277191A (en) 1988-09-13 1988-09-13 Package

Country Status (1)

Country Link
JP (1) JPH0277191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148800A (en) * 1994-11-16 1996-06-07 Nec Corp Mounting structure of circuit part
CN117641714A (en) * 2023-12-13 2024-03-01 同扬光电（江苏）有限公司 Flexible circuit board with device protection function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148800A (en) * 1994-11-16 1996-06-07 Nec Corp Mounting structure of circuit part
CN117641714A (en) * 2023-12-13 2024-03-01 同扬光电（江苏）有限公司 Flexible circuit board with device protection function

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