JP3511656B2 - Manufacturing method of leadless chip carrier - Google Patents

Description

Detailed Description of the Invention

[0001]

INDUSTRIAL APPLICABILITY The present invention can seal an electronic component and a bonding wire with a resin with a simple structure without using a resin sealing frame which is necessary for mounting an electronic component. a method of manufacturing a leadless chip carrier.

[0002]

2. Description of the Related Art Conventionally, as a leadless chip carrier, for example, as shown in FIG. 16, an insulating substrate 91, a mounting recess 90 for mounting electronic components, an electronic circuit 55, a side circuit 56, and a connecting pad. Some have 57 and 57. The upper surface 15 of the insulating substrate 91 is provided with a mounting recess 90 and an electronic circuit 55, the side surface 16 thereof is provided with a side circuit 56, and the lower surface 17 thereof is provided with a connection pad 57. The connection pad 57 is bonded onto the external element by soldering or the like. The bottom surface 13 of the mounting recess 90 has a pad 53 for mounting the electronic component 3. Around the mounting recess 90, a bonding pad 50 connected to the electronic circuit 55 is formed. The electronic component 3 is connected to the bonding pad 50 by the bonding wire 30, and is also electrically connected to an external element via the electronic circuit 55, the side circuit 56, and the connection pad 57.

The mounting recess 90 has a sealing resin 6 for covering the electronic component 3 and the bonding wire 30.
It is sealed by. The sealing resin 6 has a mounting recess 90.
It is sealed by a resin sealing frame 99 provided around the. The resin sealing frame 99 is attached to the insulating substrate 9 by the adhesive 81.
It is fixed to the upper surface 15 of 1.

[0004]

However, in the above-mentioned conventional leadless chip carrier, since the resin sealing frame 99 is provided around the mounting recess 90, the structure of the leadless chip carrier becomes complicated. In addition, the resin sealing frame 9
A great deal of labor and cost are also required for processing 9 and adhering it to the insulating substrate 91. Further, when the resin sealing frame 99 is adhered, the components in the adhesive 81 pass through the sealing resin 6 to the bonding wire 30 and the electronic component 3 during long-term use of the leadless chip carrier. May reach and corrode them. Further, in recent years, high-density mounting is required.

In view of the above conventional problems, the present invention is capable of resin-sealing an electronic component and a bonding wire with a simple structure without providing a resin-sealing frame, and leads to high-density mounting. method of manufacturing a less chip carrier is intended to provide.

[0006]

According to the present invention, an insulating substrate is pierced for cutting.
A hole is formed in the insulating substrate, and
Mounting recess for mounting electronic components having a sloped wall facing toward
And the upper end of the mounting recess is
It is located higher than the top edge of the electronic components installed inside
Next, the entire surface of the insulating substrate including the inside of the through hole
A metal plating film is applied to the
Forming a strike film, and then patterning on the upper surface of the insulating substrate.
A top film for forming is arranged, and the top film is filled.
Parallel light is radiated from above the chamber, and then the upper surface fill
The upper surface of the insulating substrate, and then the insulating substrate.
After etching the plate, the bottom of the mounting recess is
Mounting pad and slope circuit on the slope wall of the mounting recess.
, The electronic circuit on the upper surface of the insulating substrate and the side surface of the insulating substrate.
Is a side circuit, and a pad for connection on the lower surface of the insulating substrate.
And then the insulating substrate along the through hole.
Characterized by cutting into individual pieces or frames
A method of manufacturing a leadless chip carrier .

This will be described in detail below. First, for the insulating substrate
Punch through holes for singulation using a mold or the like. The through hole
Is, for example, a slit having a long hole, and is a leadless stitch described later.
It is formed at a position corresponding to the side surface of the up carrier. the above
Insulating substrate is leadless chip by forming the through hole
Individual piece constituting the carrier and support for supporting the individual piece
Divided into divisions.

Next, on the upper surface side of the insulating substrate, the sloped surface is formed.
The mounting recess having a wall is formed by counterboring, etc.
To do. Next, panel plating is applied to the entire surface of the insulating substrate.
Then, a metal plating film is formed. At this time, the insulating substrate
A metal plating film is also formed in the through hole. Next, the above penetration
The entire surface of the insulating substrate, including the inside of the holes, is coated with a photosensitive etchant.
Forming a coating resist film, and the entire surface of the metal plating film
To cover. The etching resist film is, for example, electrodeposited.
It is formed by a wet method such as a coating method.

Next, the following pattern is formed on the upper surface of the insulating substrate.
A top film for forming the. The upper surface
The rum has a light-shielding part that blocks light, and other parts transmit light.
Is configured to. The light-shielding part is an insulating substrate
A putter having the same shape as the pattern formed on the upper surface side
It has an extension part and an extension part. The extension is a side circuit
Extending from the pattern part so as to cover the through hole in which
It is set up. A pattern formed on the upper surface side of the insulating substrate.
The over emissions, electronic circuits formed on the upper surface of the insulating substrate, mounting
On the bottom surface of the slope circuit formed on the slope wall of the recess
It refers to a bonding pad or the like that is formed.

Next, a parallel light is illuminated from above the insulating substrate.
Shoot. At this time, the pattern part of the upper surface film is used.
A shadow of light is created on the upper surface side of the edge substrate, and the upper surface fill
Due to the extended portion of the light, a shadow of light is also created on the inner wall of the through hole.
That portion becomes an unexposed portion that is not exposed.

Next, the exposed portion of the etching resist film
Apply developer to the minute. As a result, the above etching resist
The unexposed part of the coating film remains as it is, and the other exposed part remains
The metal plating film is exposed by being removed. Next, the metal
The exposed part of the film is removed by etching. By this
Pattern is formed on the upper surface of the insulating substrate and on the inner wall of the through hole.
Is made. After that, the etchant remaining on the surface of the above pattern is
The coating resist film is removed. This allows the insulating substrate
On the upper surface side, electronic circuits, slope circuits, and bonding pads
And side circuits are formed on the inner walls of the through holes.

Next, on the lower surface of the insulating substrate, for example, the above
A pattern such as an electronic circuit was formed on the upper surface of the insulating substrate of
The method is used to form connection pads. The above insulation
When placing the top film on the top surface of the substrate, the insulating substrate
Place a similar bottom film on the bottom of the
Parallel light from above and below the insulating substrate.
It is preferable to shoot. As a result, the upper surface side of the insulating substrate
And the side surface as well as the lower surface at the same time.
Can be made.

Next, along the through hole, a dicing saw
-The individual parts of the insulating substrate are separated into individual pieces. In addition,
This cutting for singulation may be performed even after the above resin sealing.
Good. As a result, the leadless tip key according to the present invention is
You can get the aria. After that, the leadless tip carrier
In the mounting recess of a.
Sealing, etc.

There is no contact with the electronic circuit on the upper surface of the insulating substrate.
Continuation pads may be provided, or the lower surface of the insulating substrate may be
Electronic circuitry may be provided. These connection pads and electronic
The circuit uses the top film for pattern formation, etc.
Formed at the same time as other patterns when irradiating parallel light
can do.

Method for manufacturing the leadless chip carrier
As a leadless chip carrier manufactured by
For example, mounting recesses for mounting electronic components on the insulating substrate
For leadless chip carrier
The sidewall of the recess extends from the bottom of the mounting recess to the outside of the top.
The bottom surface of the mounting recess is a
The upper surface of the insulating substrate has an electronic circuit.
The bottom surface of the insulating board has a pad for connection.
The side is the side that connects between the electronic circuit and the connection pad.
And a sloped wall of the mounting recess has a surface circuit.
There is a slope circuit that connects the swing pad and the electronic circuit.
And the upper end of the mounting recess is the mounting recess.
Be sure that it is higher than the top edge of the electronic components installed in the unit.
There is a leadless chip carrier that is characterized by.

Most of the above leadless chip carriers
Also noteworthy is the mounting of electronic components on the top surface of the insulating substrate.
And a side wall of the mounting recess.
Is composed of a sloped wall that extends outward from the bottom of the
It is that. In the leadless chip carrier above
The mounting recess is opened on the upper surface of the insulating substrate .
On the bottom of it, electronic components are mounted.

The side wall of the mounting recess is the bottom of the mounting recess.
Consists of a sloped wall that extends from the surface to the outside of the upper end of the mounting recess
Has been done. Even if the sloped wall is formed as a flat surface,
Good, it may be formed as a concave or convex curved surface
Yes. The upper end of the mounting recess is mounted in the mounting recess.
Higher than the top of electronic components and bonding wires
In position.

A slope circuit is provided on the slope wall.
It The slope circuit is a bonnet provided on the bottom of the mounting recess.
Pad and the electronic circuit provided on the top surface of the insulating substrate.
Electrically connected to the road. The electronic circuit is an insulating substrate
Side circuits provided on the side of the
It is electrically connected to the connected connection pad. Connection above
Pads are used for external devices such as motherboard by soldering.
For electrical connection on top.

Further , the connection pad is under the insulating substrate.
It is preferable to provide it not only on the surface but also on the upper surface of the insulating substrate.
Yes. Others, such as solder, should be placed on the connection pads on the top surface.
It is possible to stack and fix the leadless chip carriers of
When multiple leadless chip carriers are integrally laminated,
You can get a stacked leadless chip carrier
It

An electronic circuit is provided on the upper surface of the insulating substrate.
However, an electronic circuit should be provided on the bottom surface of the insulating substrate.
You can Also, electronic components are emitted from the bottom surface of the insulating substrate.
A heat dissipation layer that dissipates heat may be provided. Insulating board
Shall be electrically connected to the inside or top and bottom of the insulating substrate.
A through hole for the purpose may be provided.

Electronic parts are mounted on the bottom surface of the mounting recess.
When mounted, the electronic component and the bonding pad
Are connected to each other by a bonding wire. Change
In the mounting recess without the resin sealing frame
Is the entire electronic component and bonding pad described above.
It is resin-sealed so as to cover it.

[0022]

[Operation and effect] The leadless chip carrier of the present invention
In the manufacturing method, for pattern formation on the upper surface of the insulating substrate
Place the top film of the, and irradiate parallel light from above
ing. Therefore, the pattern on the upper surface side of the insulating substrate (above
With electronic circuit, slope circuit, bonding pad) formation
In addition, the side circuit of the insulating substrate can be formed at the same time,
Easy to manufacture.

Since parallel light is used, the insulating substrate
Even if there is a gap between the upper surface of the
The film pattern is accurately projected onto the sloped wall.
Therefore, the slope circuit can be formed accurately.
The wall surface of the mounting recess is composed of the above sloped wall.
Therefore, it is easy to form by counterboring.

The leadless obtained by the above method
In the chip carrier, the upper end of the mounting recess is
Higher than the tops of electronic components and bonding wires
It is in the table. In addition, the mounting recess has a sealing resin up to the top.
Can be sealed by. Therefore, electronic components and bondins
The wire is completely covered with the sealing resin.

Therefore, the resin sealing frame that has been conventionally required
Without using a can seal the mounting recess, electrostatic therein
Protect the child parts and bonding wires from corrosion.
You can That is, in the present invention, the tree is placed on the insulating substrate.
Since the oil sealing frame is not adhered, the bond component may
The swing wires and electronic components will not corrode. Well
In addition, since a resin sealing frame is not attached, the structure should be simple.
You can In addition, the bonding wire is a concave for mounting.
Since it is inside the unit, it will not be broken and will not
It is possible to secure electrical connection with the bonding pad.
Wear.

The wall surface of the mounting recess has a mounting recess.
The sloped wall that extends from the bottom of the
It is composed of Therefore, the wall surface of the mounting recess is also slanted.
A surface circuit can be formed and the slope wall can be effectively used.
be able to. In addition, the side surface of the insulating substrate
A side circuit is provided.

In this way, the upper and lower surfaces of the insulating substrate, and
Not only on the side surface but also on the bottom surface of the mounting recess and the sloped wall.
Can be formed on all sides of the insulating substrate.
It can be used for turn formation. Therefore,
-High density packaging of dress chip carriers can be achieved.
Wear.

As described above, according to the present invention, electronic parts and bonding wires can be resin-sealed with a simple structure without providing a resin sealing frame, and high-density mounting can be achieved. ， Leadless chip carrier
It is possible to provide a method of manufacturing.

[0029]

EXAMPLES Example 1 Production of a leadless chip carrier according to an example of the present invention .
The manufacturing method will be described with reference to FIGS. In this example
Leadless chip carrier 100 to be obtained
As shown in FIGS. 1 and 2, the insulating substrate 1 is provided with a mounting recess 10 for mounting electronic components. The side wall of the mounting recess 10 is formed by a sloped wall 11 that spreads in a planar manner from the bottom surface 13 thereof to the outside of the upper end. In addition, the mounting recess 10
The bottom surface 13 of the bonding pad 50 and the pad 53.
have. The upper end 111 of the mounting recess 10 is higher than the upper ends of the electronic component 3 and the bonding wire 30.

The upper surface 15 of the insulating substrate 1 has an electronic circuit 55,
The lower surface 17 has a connection pad 57 and a heat dissipation layer 58. The side surface 16 of the insulating substrate 1 has a side surface circuit 56 that connects the electronic circuit 55 and the connection pad 57.
The sloped wall 11 of the mounting recess 10 has the bonding pad 5
It has a slope circuit 51 connecting 0 and the electronic circuit 55.

In the leadless chip carrier 100 of this example, the electronic component 3 is mounted on the pad 53 in the mounting recess 10. The bonding wire 50 connects the bonding pad 50 and the electronic component 3. In addition, the electronic component 3 and the bonding wire 30 are provided in the mounting recess 10 without providing a resin sealing frame.
The encapsulating resin 6 is encapsulated so as to cover the whole of the.

Next, the leadless chip carrier 10
The manufacturing method of 0 will be described with reference to FIGS.
First, as shown in FIGS. 3 and 4, in the insulating substrate 1, elongated through holes 160 for cutting are formed in four directions along the dimension line 165 of the leadless chip carrier. As a result, the individual piece portion 19 for producing the leadless chip carrier is inside the through hole 160 and the individual piece portion 19 is outside thereof.
A support portion 191 for supporting the is formed.

Next, as shown in FIG. 5, the individual mounting portion 19 of the insulating substrate 1 is provided with a mounting recess 10 for mounting electronic components by counterboring. The mounting recess 10 has a bottom 13
Has a flat sloped wall 11 that spreads from the top to the outside. The mounting recess 10 is formed such that the upper end 111 thereof is located higher than the upper ends of the electronic component and the bonding wire when mounted in the mounting recess 10. Next, as shown in FIG. 6, the entire surface of the insulating substrate 1 is panel-plated to form a metal plating film 5. At this time, the metal plating film 5 is also formed inside the through hole 160.

Next, as shown in FIG.
The etching resist film 7 is formed on the entire surface of the insulating substrate 1 including the 0 by a wet method. Further, as shown in FIGS. 7 and 8, an upper surface film 21 and a lower surface film 22 for pattern formation are arranged on the upper surface 15 and the lower surface 17 of the insulating substrate 1, respectively. Top film 21, bottom film 22
Have light-shielding portions 210 and 220 for shielding the pattern forming portions of the insulating substrate 1, respectively.
The portions other than 220 are transparent portions 213 and 223 which are transparent.

The light-shielding portions 210 and 220 have pattern portions 211 and 221 having the same shape as the patterns formed on the upper surface 151 and the lower surface 17 of the insulating substrate 1, and side surface pattern forming portions in the through holes 160 of the insulating substrate 1. It has extended portions 212 and 222 for covering.

Next, the insulating substrate 1 is irradiated with parallel light 8 from both the upper and lower sides thereof. At this time, as shown in FIGS. 7 and 8, the parallel light 8 is shielded by the light shields 210 and 220, and light shadows 81 are formed on the upper surface 151 and the lower surface of the insulating substrate 1, and on the inner wall of the through hole 160. Also forms a shadow 82 of light, and the portions of these shadows 81 and 82 are not exposed, but only the portions corresponding to the transparent portions 213 and 223 of the insulating substrate 1 are exposed.

Next, the insulating substrate 1 to the top film 21,
The lower surface film 22 is removed. Next, a developing solution is applied to the exposed portion of the etching resist film 7. As a result, the unexposed portion of the etching resist film remains as it is, and the other exposed portion is removed to expose the metal plating film 5. Then, the exposed portion of the metal plating film is removed by etching. As a result, as shown in FIG. 9, the etching resist film 7 and the metal plating film 5 in the exposed portion are removed from the insulating substrate 1.

Next, only the etching resist film 7 remaining on the insulating substrate 1 is removed. As a result, as shown in FIG. 10, the electronic circuit 55 is formed on the upper surface 15 of the insulating substrate 1, and the connection pads 57 and the heat dissipation layer 58 are formed on the lower surface 17. In addition, the side circuit 56 is formed on the inner wall of the through hole 160,
A slope circuit 51 is formed on the slope wall 11 of the mounting recess 10, and a bonding pad 50 and a pad 53 are formed on the bottom surface 13. Next, the insulating substrate 1 is cut by a dicing saw along the through holes 160 and the dimension lines 165 shown in FIG. 10 to separate the individual pieces 19 into individual pieces. As a result,
The leadless chip carrier 100 shown in FIG. 2 is obtained.

Next, the re-obtained by the manufacturing method of this example
The function and effect of the dress chip carrier 100 will be described. In the leadless chip carrier 100 of this example, as shown in FIGS. 1 and 2, the upper end 1 of the mounting recess 10 is
11 is at a position higher than the upper ends of the electronic component 3 and the bonding wire 30. Further, the mounting recess 10 is sealed with the sealing resin 6 up to the upper end 111 thereof.

Therefore, the electronic component 3 and the bonding wire 30 are completely covered with the sealing resin 6. Therefore, the mounting recess 10 can be sealed without using a resin sealing frame, and the electronic component 3 and the bonding wire 30 therein can be protected from corrosion. That is, in this example, since the resin sealing frame is not bonded onto the insulating substrate 1, the bonding wire 30 and the electronic component 3 are not corroded by the component of the adhesive.

Further, since the resin sealing frame is not attached, the structure can be simplified. In addition, since the bonding wire 30 is in the mounting recess 10, it is possible to secure electrical connection with the electronic component 3 or the bonding pad 50 without breaking.

The wall surface of the mounting recess 10 is formed by a sloped wall 11 extending from the bottom surface 13 of the mounting recess 10 to the outside of the upper part of the mounting recess 10. Therefore, the slope circuit 51 can be formed on the wall surface of the mounting recess 10 and the slope wall 11 can be effectively used. Further, a side surface circuit 56 is also provided on the side surface 16 of the insulating substrate 1.

As described above, not only the upper surface 15, the lower surface 17, and the side surface 16 of the insulating substrate 1, but also the bottom surface 13 and the sloped wall 11 of the mounting recess 10 can be patterned, and all the surfaces of the insulating substrate can be formed. Can be utilized for pattern formation. Therefore, high density mounting of the leadless chip carrier 100 can be achieved.

Next, in the manufacturing method of this example, as shown in FIG.
As shown in FIG. 8, the upper surface 15 and the lower surface 17 of the insulating substrate 1 are
Top film 21 and bottom film 2 for pattern formation
2 are arranged respectively, and the parallel light 8 is emitted from above and below. Therefore, the upper surface 151 and the lower surface 17 of the insulating substrate 1 are patterned, and the side surface 16 of the insulating substrate 1 is formed.
Since the pattern is formed at the same time, it is easy to manufacture.

Further, since the wall surface of the mounting recess 10 is composed of the above-mentioned sloped wall 11, it can be subjected to counterboring or the like.
Easy to form. Further, since the parallel light 8 is used, even if there is a gap between the upper surface 15 of the insulating substrate 1 and the sloped wall 11 and the bottom surface 13, the pattern of the upper surface film 21 is accurately projected onto the sloped wall 11. . Therefore, the slope circuit 51 can be accurately formed.

Example 2 Leadless chip carrier 100 obtained in this example
11 is a slope wall 11 of the mounting recess 10 as shown in FIG.
0 is a curved surface curved in a concave shape. Others are the same as those in the first embodiment. In this example, since the slope wall 110 is a curved surface, stress can be relaxed. Other than that, the same effects as those of the first embodiment can be obtained.

Example 3 Leadless chip carrier 100 obtained in this example
As shown in FIG. 12, an electronic circuit 59 is provided on the lower surface 17 of the insulating substrate 1. The electronic circuit 59 includes a heat dissipation layer 5
It is formed around eight. Others are the same as in the first embodiment. In this example, since the electronic circuit 59 is also provided on the lower surface 17 of the insulating substrate 1, higher density mounting can be achieved. Other than that, the same effects as those of the first embodiment can be obtained.

Example 4 Leadless chip carrier 101 obtained in this example
Is the upper surface 1 of the insulating substrate 1 as shown in FIGS.
5 to the electronic circuit 55 formed, the connection pad 57
1 is provided. As shown in FIG. 15, the leadless chip carrier 100 shown in the first embodiment is laminated and fixed on the connection pad 571 by using solder 4 or the like. These two leadless chip carriers 100,1
Reference numeral 01 constitutes a laminated leadless chip carrier 102. Others are the same as in the first embodiment. Also in this example, the same effect as that of the first embodiment can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a leadless chip carrier according to a first embodiment.

FIG. 2 is a perspective view of the leadless chip carrier according to the first embodiment.

FIG. 3 is a cross-sectional view of an insulating substrate having a through hole in the method for manufacturing a leadless chip carrier according to the first embodiment.

FIG. 4 is a plan view of FIG.

FIG. 5 is a cross-sectional view of an insulating substrate in which a mounting recess is formed in the leadless chip carrier manufacturing method according to the first embodiment.

FIG. 6 is a cross-sectional view of an insulating substrate provided with a metal plating film in the method for manufacturing a leadless chip carrier according to the first embodiment.

FIG. 7 is a cross-sectional view of an insulating substrate during parallel light irradiation in the method for manufacturing a leadless chip carrier according to the first embodiment.

FIG. 8 is a perspective view of an essential part of the insulating substrate during parallel light irradiation in the method for manufacturing a leadless chip carrier according to the first embodiment.

FIG. 9 is a cross-sectional view of an insulating substrate after etching in the method for manufacturing a leadless chip carrier according to the first embodiment.

FIG. 10 is a cross-sectional view showing a cutting position of the insulating substrate in the leadless chip carrier manufacturing method according to the first embodiment.

11 is a sectional view of the leadless chip carrier of Example 2. FIG.

FIG. 12 is a sectional view of a leadless chip carrier of Example 3.

FIG. 13 is a cross-sectional view of the leadless chip carrier of Example 4.

FIG. 14 is a perspective view of a leadless chip carrier of Example 4.

FIG. 15 is a sectional view of a laminated leadless chip carrier of Example 4.

FIG. 16 is a cross-sectional view of a conventional leadless chip carrier.

[Explanation of symbols]

1. ． ． Insulating substrate, 10. ． ． Mounting recess, 100,1
01. ． ． Leadless chip carrier, 11, 11
0. ． ． Slope wall, 13. ． ． Bottom, 15. ． ． Top, 1
6. ． ． Side, 160. ． ． Through-holes, 17. ． ． Bottom surface,
19. ． ． Individual piece, 191. ． ． Support part, 3. ． ． Electronic components, 30. ． ． Bonding wire, 4. ． ． Solder, 50. ． ． Bonding pad, 51. ． ． Slope circuit, 55, 59. ． ． Electronic circuit, 56. ． ． Side circuit,
57,571. ． ． Connection pad, 6. ． ． Sealing resin,

─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-4-158555 (JP, A) JP-A-60-194548 (JP, A) JP-B-54-44634 (JP, B1) JP-B-59- 8363 (JP, Y1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (4)

(57) [Claims] 1. A through hole for cutting is bored in an insulating substrate, and a mounting recess for mounting an electronic component is formed which has a sloped wall extending from the bottom to the outside of the upper part, and the upper end of the mounting recess. Is at a position higher than the upper end of the electronic component mounted in the mounting recess. Next, a metal plating film is applied to the entire surface of the insulating substrate, including the inside of the through hole, and a photosensitive etching is performed. A resist film is formed, and then an upper surface film for pattern formation is arranged on the upper surface of the insulating substrate, and parallel light is irradiated from above the upper surface film. Then, the insulating substrate is etched to form a bonding pad on the bottom of the mounting recess, a sloped circuit on the sloped wall of the mounting recess, and an electronic circuit on the upper surface of the insulating substrate.
A side surface circuit is formed on the side surface of the insulating substrate, and a connecting pad is formed on the lower surface of the insulating substrate. Then, the insulating substrate is cut along the through hole,
A method for manufacturing a leadless chip carrier, which is characterized by individualization or frame formation. 2. The method for manufacturing a leadless chip carrier according to claim 1, wherein a connecting pad is formed on the electronic circuit formed on the upper surface of the insulating substrate. 3. The method of claim 1, or 2, the insulation on the lower surface of the substrate, a manufacturing method of the leadless chip carrier and forming an electronic circuit. 4. The method of claim 1, 2, or 3, the etching resist film, a manufacturing method of the leadless chip carrier, characterized in that it is formed by a wet method such as electrodeposition coating method.