JP2004048085A - Leadless chip carrier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a leadless chip carrier capable of resin sealing an electronic part and a bonding wire with a simple structure without using a resin sealing frame. <P>SOLUTION: The side wall of a mounting recess 10 is made up of a slant wall 11 extending upward and outward from a bottom 13 thereof and the slant wall has a slant circuit 51 for connecting a bonding pad 50 and an electronic circuit 55. A top surface 15 of an insulating substrate 1 has the electronic circuit 55, an undersurface 17 thereof has a connecting pad 57, and a side 16 thereof has a side circuit 56 for connecting an electronic circuit 3 and the connecting pad. Within the mounting recess, the electronic part 3 and a bonding wire 30 are sealed with a sealing resin 6 without using the resin sealing frame. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a leadless chip carrier capable of resin-sealing an electronic component and a bonding wire with a simple structure without using a resin sealing frame required for mounting an electronic component.

Conventionally, as a leadless chip carrier, for example, as shown in FIG. 16, it has an insulating substrate 91, a mounting recess 90 for mounting electronic components, an electronic circuit 55, a side circuit 56, and a connection pad 57. There is something.
The mounting recess 90 and the electronic circuit 55 are provided on the upper surface 15 of the insulating substrate 91, the side circuit 56 is provided on the side surface 16, and the connection pad 57 is provided on the lower surface 17.
The connection pad 57 is bonded onto the external element by soldering or the like.
The bottom surface 13 of the mounting concave portion 90 has a pad 53 for mounting the electronic component 3. Around the mounting recess 90, a bonding pad 50 connected to the electronic circuit 55 is formed.
The electronic component 3 is connected to a bonding pad 50 by a bonding wire 30, and is further electrically connected to an external element via an electronic circuit 55, a side circuit 56, and a connection pad 57.

The mounting recess 90 is sealed with a sealing resin 6 for covering the electronic component 3 and the bonding wire 30. The sealing resin 6 is sealed by a resin sealing frame 99 provided around the mounting concave portion 90.
The resin sealing frame 99 is fixed to the upper surface 15 of the insulating substrate 91 by an adhesive 81.

However, in the above-mentioned conventional leadless chip carrier, since the resin sealing frame 99 is provided around the mounting concave portion 90, the structure of the leadless chip carrier becomes complicated. In addition, a great deal of labor and cost are required for processing the resin sealing frame 99 and bonding the resin sealing frame 99 to the insulating substrate 91.
When the resin sealing frame 99 is bonded, the components in the adhesive 81 pass through the sealing resin 6 to the bonding wires 30 and the electronic components 3 while the leadless chip carrier is used for a long time. And may corrode them. In recent years, high-density mounting has been required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a simple structure, without providing a resin sealing frame, capable of resin-sealing electronic components and bonding wires and achieving high-density mounting. It is intended to provide.

The present invention provides a leadless chip carrier having a mounting recess for mounting electronic components on an insulating substrate,
The side wall of the mounting recess is formed by a sloped wall that extends outward from the bottom of the mounting recess, and the bottom of the mounting recess has a bonding pad.
The upper surface of the insulating substrate has an electronic circuit, and the lower surface has connection pads,
The side surface of the insulating substrate has a side circuit connecting between the electronic circuit and the connection pad,
The slope wall of the mounting recess has a slope circuit connecting between the bonding pad and the electronic circuit,
Further, the leadless chip carrier is characterized in that the upper end of the mounting recess is higher than the upper end of the electronic component mounted in the mounting recess (claim 1).

The most remarkable thing in the present invention is that the mounting recess for mounting electronic components is provided on the upper surface of the insulating substrate, and the side wall of the mounting recess is formed by a slope wall extending upward and outward from the bottom surface. That is.
In the present invention, the mounting recess is opened on the upper surface of the insulating substrate, and the electronic component is mounted on the bottom surface.

The side wall of the mounting recess is formed by a slope wall extending from the bottom surface of the mounting recess to the outside of the upper end of the mounting recess. The slope wall may be formed as a flat surface, or may be formed as a concave or convex curved surface.
The upper end of the mounting recess is higher than the upper ends of the electronic components and the bonding wires mounted in the mounting recess.

A slope circuit is provided on the slope wall. The slope circuit is electrically connected to a bonding pad provided on the bottom surface of the mounting recess and an electronic circuit provided on the upper surface of the insulating substrate.
The electronic circuit is electrically connected to a side circuit provided on a side surface of the insulating substrate and a connection pad provided on a lower surface of the insulating substrate.
The connection pad is for electrically connecting to an external element such as a motherboard by soldering or the like.

It is preferable that the connection pads are provided not only on the lower surface of the insulating substrate but also on the upper surface of the insulating substrate. On the connection pads on the upper surface, another leadless chip carrier can be laminated and fixed via solder or the like, and a laminated leadless chip carrier in which a plurality of leadless chip carriers are integrally laminated. Can be obtained.

Although an electronic circuit is provided on the upper surface of the insulating substrate, an electronic circuit can be provided on the lower surface of the insulating substrate.
Further, a heat radiation layer for dissipating heat generated by the electronic component may be provided on the lower surface of the insulating substrate. Further, the insulating substrate may be provided with through holes for electrical conduction inside the insulating substrate or between the upper surface and the lower surface.
It is preferable that a sealing resin is sealed in the mounting recess.
In this case, the mounting recess can be sealed, and the electronic components and the like therein can be protected from corrosion.
Further, the electronic component and the bonding pad are electrically connected by a bonding wire, and the sealing is performed so as to cover the entire electronic component and the bonding wire in the mounting recess. It is preferable that the resin is sealed.
In this case, the electronic component and the bonding wire can be protected from corrosion.

電子 An electronic component is mounted on the bottom surface of the mounting concave portion, and the electronic component and the bonding pad are connected by a bonding wire. Furthermore, without providing a resin sealing frame, the inside of the mounting concave portion is resin-sealed so as to cover the entire electronic component and the bonding pad.

Next, as a method of manufacturing the leadless chip carrier of the present invention, for example, an electronic device having a through hole for cutting in an insulating substrate and an insulating substrate having an inclined wall extending from the bottom to the top outward from the bottom. Forming mounting recesses for component mounting,
And the upper end of the mounting recess is located higher than the upper end of the electronic component mounted in the mounting recess,
Next, on the entire surface of the insulating substrate, including the inside of the through-hole, a metal plating film is formed and a photosensitive etching resist film is formed,
Next, while arranging an upper film for pattern formation on the upper surface of the insulating substrate, irradiating parallel light from above the upper film, and then removing the upper film from the upper surface of the insulating substrate,
Next, the insulating substrate is etched to provide a bonding pad on the bottom surface of the mounting concave portion, a slope circuit on a slope wall of the mounting concave portion, an electronic circuit on an upper surface of the insulating substrate, and a side surface of the insulating substrate. Form a side circuit, and further form a connection pad on the lower surface of the insulating substrate,
Thereafter, there is a method of manufacturing a leadless chip carrier, wherein the insulating substrate is cut along the through-holes into individual pieces or frames.

Hereinafter, this will be described in detail.
First, a through-hole for singulation is punched out on an insulating substrate using a mold or the like. The through-hole is, for example, an elongated slit formed at a position corresponding to a side surface of a leadless chip carrier described later. The insulating substrate is partitioned into individual pieces constituting a leadless chip carrier and a support portion supporting the individual pieces by forming the through holes.

Next, the mounting recess having the inclined wall is formed on the upper surface side of the insulating substrate by counterboring or the like.
Next, panel plating is performed on the entire surface of the insulating substrate to form a metal plating film. At this time, a metal plating film is also formed in the through hole of the insulating substrate.
Next, a photosensitive etching resist film is formed on the entire surface of the insulating substrate including the inside of the through hole, and covers the entire surface of the metal plating film. The etching resist film is formed by, for example, a wet method such as an electrodeposition coating method.

Next, an upper surface film for forming the following pattern is arranged on the upper surface of the insulating substrate. The top film has a light blocking portion for blocking light, and the other films are configured to transmit light. The light-shielding portion has a pattern portion having the same shape as a pattern formed on the upper surface side of the insulating substrate, and an extended portion. The extending portion extends from the pattern portion so as to cover the through hole in which the side circuit is formed.
The pattern formed on the upper surface side of the insulating substrate refers to an electronic circuit formed on the upper surface of the insulating substrate, a slope circuit formed on the slope wall of the mounting concave portion, a bonding pad formed on the bottom surface, and the like. .

Next, parallel light is irradiated from above the insulating substrate. At this time, a light shadow is formed on the upper surface side of the insulating substrate by the pattern portion of the upper film, and a light shadow is formed on the inner wall of the through hole by the extended portion of the upper film, and the portion is not exposed and is not exposed. Part.

Next, a developing solution is applied to the exposed portion of the etching resist film. As a result, the unexposed portion of the etching resist film remains as it is, and the other exposed portions are removed, exposing the metal plating film. Next, the exposed portion of the metal plating film is removed by etching. Thereby, a pattern is formed on the upper surface side of the insulating substrate and the inner wall of the through hole.
Thereafter, the etching resist film remaining on the surface of the pattern is removed. Thus, an electronic circuit, a slope circuit, and a bonding pad are formed on the upper surface side of the insulating substrate, and a side circuit is formed on the inner wall of the through hole.

Next, connection pads are formed on the lower surface of the insulating substrate, for example, using a method in which a pattern of an electronic circuit or the like is formed on the upper surface side of the insulating substrate.
When the upper film is disposed on the upper surface of the insulating substrate, a similar lower film is disposed on the lower surface of the insulating substrate. In this state, parallel light is irradiated from both above and below the insulating substrate. Irradiation is preferred. Thereby, a pattern can be simultaneously formed on the lower surface as well as on the upper surface side and the side surface of the insulating substrate.

Next, the individual portions of the insulating substrate are separated into individual pieces along the through holes using a dicing saw or the like. Note that the cutting for individualization may be performed after the above-described resin sealing.
Thereby, a leadless chip carrier according to the present invention is obtained.
Thereafter, as described above, electronic components are mounted in the mounting recesses of the leadless chip carrier, and resin sealing is performed.

接 続 Electronic circuits on the upper surface of the insulating substrate may be provided with connection pads, and electronic circuits may be provided on the lower surface of the insulating substrate. These connection pads and electronic circuits can be formed simultaneously with the formation of other patterns when irradiating parallel light using the upper film for pattern formation or the like.

(Action and effect)
In the leadless chip carrier of the present invention, the upper end of the mounting recess is higher than the upper ends of the electronic component and the bonding wire. Further, the mounting concave portion is sealed up to its upper end with a sealing resin.
Therefore, the electronic component and the bonding wire are completely covered with the sealing resin.

Therefore, the mounting recess can be sealed without using the resin sealing frame which has been required conventionally, and the electronic components and the bonding wires therein can be protected from corrosion.
That is, in the present invention, since the resin sealing frame is not bonded on the insulating substrate, the bonding wire and the electronic component do not corrode due to the components of the adhesive.
Also, since no resin sealing frame is attached, a simple structure can be achieved.
Further, since the bonding wire is in the mounting concave portion, it is possible to secure electrical connectivity with the electronic component or the bonding pad without breaking.

The wall surface of the mounting recess is formed by a slope wall extending from the bottom surface of the mounting recess to the upper end of the mounting recess. Therefore, a slope circuit can be formed also on the wall surface of the mounting recess, and the slope wall can be effectively used.
Further, a side surface circuit of the insulating substrate is provided also on a side surface of the insulating substrate.

As described above, the pattern can be formed not only on the upper surface, the lower surface, and the side surface of the insulating substrate, but also on the bottom surface and the inclined wall of the mounting concave portion, and any surface of the insulating substrate can be used for pattern formation. it can. Therefore, high-density mounting of the leadless chip carrier can be achieved.

Next, in the method of manufacturing the leadless chip carrier, for example, an upper film for pattern formation is disposed on the upper surface of the insulating substrate, and the parallel light is irradiated from above. Therefore, the side circuit of the insulating substrate can be formed simultaneously with the formation of the pattern on the upper surface side of the insulating substrate (the electronic circuit, the inclined circuit, and the bonding pad), which is easy to manufacture.

Further, since the parallel light is used, even if there is a gap between the upper surface of the insulating substrate and the slope wall and the bottom surface, the pattern of the upper film is accurately projected on the slope wall. Therefore, a slope circuit can be formed with high accuracy.
Further, since the wall surface of the mounting concave portion is constituted by the above-mentioned slope wall, it can be easily formed by counterboring or the like.

As described above, according to the present invention, an electronic component and a bonding wire can be resin-sealed with a simple structure without providing a resin-sealing frame, and high-density mounting can be achieved. A chip carrier can be provided.

Example 1
A leadless chip carrier according to an embodiment of the present invention will be described with reference to FIGS.
As shown in FIGS. 1 and 2, the leadless chip carrier 100 of this embodiment has a mounting recess 10 for mounting electronic components on an insulating substrate 1.
The side wall of the mounting concave portion 10 is constituted by a slope wall 11 which spreads in a plane from the bottom surface 13 to the upper end outward. The bottom surface 13 of the mounting concave portion 10 has a bonding pad 50 and a pad 53.
The upper end 111 of the mounting recess 10 is located higher than the upper ends of the electronic component 3 and the bonding wire 30.

The upper surface 15 of the insulating substrate 1 has an electronic circuit 55, and the lower surface 17 has connection pads 57 and a heat radiation layer 58. The side surface 16 of the insulating substrate 1 has a side circuit 56 that connects between the electronic circuit 55 and the connection pad 57.
The slope wall 11 of the mounting recess 10 has a slope circuit 51 that connects between the bonding pad 50 and the electronic circuit 55.

In the leadless chip carrier 100 of this example, the electronic component 3 is mounted on the pad 53 in the mounting recess 10. The bonding pad 50 and the electronic component 3 are connected by the bonding wire 30. Further, the sealing resin 6 is sealed in the mounting recess 10 so as to cover the entire electronic component 3 and the bonding wires 30 without providing a resin sealing frame.

Next, a method of manufacturing the leadless chip carrier 100 will be described with reference to FIGS.
First, as shown in FIG. 3 and FIG. 4, elongated through holes 160 for cutting are formed in the insulating substrate 1 in four directions along the dimension line 165 of the leadless chip carrier. As a result, a piece 19 for producing a leadless chip carrier is formed inside the through hole 160, and a support 191 for supporting the piece 19 is formed outside the through hole 160.

Next, as shown in FIG. 5, mounting recesses 10 for mounting electronic components are formed in the individual portions 19 of the insulating substrate 1 by counterboring. The mounting recess 10 has a planar inclined wall 11 extending outward from the bottom 13 to the upper side. The mounting recess 10 is formed such that its upper end 111 is higher than the upper ends of the electronic component and the bonding wire when mounted in the mounting recess 10.
Next, as shown in FIG. 6, the entire surface of the insulating substrate 1 is subjected to panel plating, and a metal plating film 5 is formed. At this time, the metal plating film 5 is also formed inside the through hole 160.

Next, as shown in FIG. 7, an etching resist film 7 is formed on the entire surface of the insulating substrate 1 including the through holes 160 by a wet method.
As shown in FIGS. 7 and 8, an upper film 21 and a lower film 22 for pattern formation are arranged on the upper surface 15 and the lower surface 17 of the insulating substrate 1, respectively. The upper film 21 and the lower film 22 have light shielding portions 210 and 220 for shielding the pattern forming portion of the insulating substrate 1 respectively, and portions other than the light shielding portions 210 and 220 are transparent transparent portions 213 and 223. .

The light-shielding portions 210 and 220 are provided with pattern portions 211 and 221 having the same shape as the patterns formed on the upper surface 151 and the lower surface 17 of the insulating substrate 1, respectively. There are provided portions 212 and 222.

Next, the insulating substrate 1 is irradiated with the parallel light 8 from both the upper and lower sides. At this time, as shown in FIGS. 7 and 8, the parallel light 8 is blocked by the light shielding portions 210 and 220, and light shadows 81 are formed on the upper surface 151 and the lower surface of the insulating substrate 1, respectively. Also, a light shadow 82 is formed. Only the portions corresponding to the transparent portions 213 and 223 of the insulating substrate 1 are exposed without exposing the portions of the shadows 81 and 82.

Next, the upper film 21 and the lower film 22 are removed from the insulating substrate 1. Next, a developing solution is applied to the exposed portions of the etching resist film 7. Thus, the unexposed portion of the etching resist film remains as it is, and the other exposed portions are removed, exposing the metal plating film 5. Next, the exposed portion of the metal plating film is removed by etching. Thereby, as shown in FIG. 9, the etching resist film 7 and the metal plating film 5 in the exposed portions are removed from the insulating substrate 1.

Next, only the etching resist film 7 remaining on the insulating substrate 1 is removed. As a result, as shown in FIG. 10, the electronic circuit 55 is formed on the upper surface 15 of the insulating substrate 1, and the connection pads 57 and the heat radiation layer 58 are formed on the lower surface 17. A side circuit 56 is formed on the inner wall of the through hole 160, a slope circuit 51 is formed on the slope wall 11 of the mounting recess 10, and a bonding pad 50 and a pad 53 are formed on the bottom surface 13.
Next, the insulating substrate 1 is cut by a dicing saw along the through holes 160 and the dimension lines 165 shown in FIG. Thereby, the leadless chip carrier 100 shown in FIGS. 1 and 2 is obtained.

Next, the operation and effect of this example will be described.
In the leadless chip carrier 100 of the present example, as shown in FIGS. 1 and 2, the upper end 111 of the mounting recess 10 is located higher than the upper ends of the electronic component 3 and the bonding wire 30. The mounting recess 10 is sealed by the sealing resin 6 up to its upper end 111.

Therefore, the electronic component 3 and the bonding wire 30 are completely covered with the sealing resin 6.
Therefore, the mounting recess 10 can be sealed without using a resin sealing frame, and the electronic component 3 and the bonding wire 30 therein can be protected from corrosion.
That is, in this example, since the resin sealing frame is not bonded on the insulating substrate 1, the bonding wire 30 and the electronic component 3 do not corrode due to the components of the adhesive.

Also, since no resin sealing frame is attached, a simple structure can be achieved.
In addition, since the bonding wire 30 is located in the mounting concave portion 10, it is possible to secure electrical connectivity with the electronic component 3 or the bonding pad 50 without disconnection.

The wall surface of the mounting recess 10 is constituted by a slope wall 11 extending outward from the bottom surface 13 of the mounting recess 10 to the upper part of the mounting recess 10. Therefore, the slope circuit 51 can be formed also on the wall surface of the mounting recess 10, and the slope wall 11 can be effectively used. Further, a side surface circuit 56 is also provided on the side surface 16 of the insulating substrate 1.

As described above, the pattern can be formed not only on the upper surface 15, the lower surface 17, and the side surface 16 of the insulating substrate 1 but also on the bottom surface 13 and the inclined wall 11 of the mounting concave portion 10. Can be utilized for Therefore, high-density mounting of the leadless chip carrier 100 can be achieved.

Next, in the manufacturing method of the present embodiment, as shown in FIGS. 7 and 8, an upper film 21 and a lower film 22 for pattern formation are respectively arranged on the upper surface 15 and the lower surface 17 of the insulating substrate 1, and the upper and lower films are formed. Irradiate parallel light 8 from Therefore, the pattern is formed on the side surface 16 of the insulating substrate 1 at the same time as the pattern formation on the upper surface side 151 and the lower surface 17 of the insulating substrate 1, which facilitates manufacturing.

In addition, since the wall surface of the mounting concave portion 10 is constituted by the above-mentioned inclined wall 11, it is easy to form by counterbore processing or the like.
Further, since the parallel light 8 is used, even if there is a gap between the upper surface 15 of the insulating substrate 1 and the inclined wall 11 and the bottom surface 13, the pattern of the upper film 21 is accurately projected on the inclined wall 11. . Therefore, the slope circuit 51 can be formed with high accuracy.

Example 2
In the leadless chip carrier 100 of this example, as shown in FIG. 11, the slope wall 110 of the mounting concave portion 10 has a curved surface curved in a concave shape. Others are the same as the first embodiment.
In this example, since the slope wall 110 is a curved surface, stress can be reduced. Otherwise, the same effects as in the first embodiment can be obtained.

Example 3
In the leadless chip carrier 100 of this example, as shown in FIG. 12, an electronic circuit 59 is provided on the lower surface 17 of the insulating substrate 1. The electronic circuit 59 is formed around the heat radiation layer 58.
Others are the same as the first embodiment.
In this example, since the electronic circuit 59 is also provided on the lower surface 17 of the insulating substrate 1, further high-density mounting can be achieved. Otherwise, the same effects as in the first embodiment can be obtained.

Example 4
In the leadless chip carrier 101 of this example, as shown in FIGS. 13 to 15, a connection pad 571 is provided on an electronic circuit 55 formed on the upper surface 15 of the insulating substrate 1.
As shown in FIG. 15, the leadless chip carrier 100 shown in the first embodiment is stacked and fixed on the connection pads 571 using solder 4 or the like. The two leadless chip carriers 100 and 101 constitute a stacked leadless chip carrier 102.
Others are the same as the first embodiment.
In this embodiment, the same effects as in the first embodiment can be obtained.

FIG. 2 is a cross-sectional view of the leadless chip carrier according to the first embodiment. FIG. 2 is a perspective view of the leadless chip carrier according to the first embodiment. FIG. 4 is a cross-sectional view of an insulating substrate having a through hole in the method for manufacturing a leadless chip carrier according to the first embodiment. The top view of FIG. FIG. 5 is a cross-sectional view of the insulating substrate having mounting recesses formed therein in the method for manufacturing a leadless chip carrier according to the first embodiment. FIG. 4 is a cross-sectional view of an insulating substrate provided with a metal plating film in the method for manufacturing a leadless chip carrier according to the first embodiment. FIG. 4 is a cross-sectional view of the insulating substrate during irradiation of parallel light in the method for manufacturing a leadless chip carrier according to the first embodiment. FIG. 4 is a perspective view of a main part of the insulating substrate during irradiation of parallel light in the method for manufacturing a leadless chip carrier according to the first embodiment. FIG. 5 is a cross-sectional view of the insulating substrate after etching in the method for manufacturing a leadless chip carrier according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a cutting position of the insulating substrate in the method of manufacturing the leadless chip carrier according to the first embodiment. FIG. 6 is a cross-sectional view of a leadless chip carrier according to a second embodiment. FIG. 10 is a sectional view of a leadless chip carrier according to a third embodiment. FIG. 13 is a sectional view of a leadless chip carrier according to a fourth embodiment. FIG. 14 is a perspective view of a leadless chip carrier according to a fourth embodiment. FIG. 13 is a cross-sectional view of the laminated leadless chip carrier according to the fourth embodiment. Sectional drawing of the conventional leadless chip carrier.

Explanation of reference numerals

1 insulating substrate,
10 mounting recess,
100, 101 leadless chip carrier,
11, 110 slope wall,
13 bottom,
15 Top,
16 sides,
160 through holes,
17 lower surface,
19 pieces,
191 support,
3 electronic components,
30 bonding wires,
4 solder,
50 bonding pads,
51 slope circuit,
55, 59 electronic circuits,
56 side circuit,
57,571 connection pads,
6 sealing resin,

Claims (5)

In a leadless chip carrier having a mounting recess for mounting electronic components on an insulating substrate,
The side wall of the mounting recess is formed by a sloped wall that extends outward from the bottom of the mounting recess, and the bottom of the mounting recess has a bonding pad.
The upper surface of the insulating substrate has an electronic circuit, and the lower surface has connection pads,
The side surface of the insulating substrate has a side circuit connecting between the electronic circuit and the connection pad,
The slope wall of the mounting recess has a slope circuit connecting between the bonding pad and the electronic circuit,
A leadless chip carrier, wherein the upper end of the mounting recess is higher than the upper end of the electronic component mounted in the mounting recess. A leadless chip carrier according to claim 1, wherein connection pads are provided on the electronic circuit on the upper surface of the insulating substrate. A leadless chip carrier according to claim 2, wherein an electronic circuit is provided on a lower surface of the insulating substrate. 3. The leadless chip carrier according to claim 1, wherein a sealing resin is sealed in the mounting recess. The electronic component and the bonding pad according to claim 4, wherein the electronic component and the bonding pad are electrically connected by a bonding wire, and the mounting recess covers the entire electronic component and the bonding wire. A leadless chip carrier, wherein the sealing resin is sealed.

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