JP2895504B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2895504B2 JP2895504B2 JP1100910A JP10091089A JP2895504B2 JP 2895504 B2 JP2895504 B2 JP 2895504B2 JP 1100910 A JP1100910 A JP 1100910A JP 10091089 A JP10091089 A JP 10091089A JP 2895504 B2 JP2895504 B2 JP 2895504B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- plate
- semiconductor element
- resin
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、樹脂封止成形される半導体装置の構造に
関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device molded by resin molding.
〔従来の技術〕 第４図はフィルムキャリアテープを用いて半導体素子
を実装するTAB（Tape Automated Bonding）方式による
樹脂封止された半導体装置の構造を示す断面図であり、
第５図はこの半導体装置の樹脂封止前の状態を示す平面
図である。図において、１は半導体素子、２はこの半導
体素子１上に形成された突起電極である。３は例えばポ
リイミドを基材とするキャリアテープであり、その表面
にCu箔等で形成された配線パターン４がある。前記キャ
リアテープ３にはテープ送り用のスプロケットホール3a
があり、デバイスホール3b、アウタリードホール3c、サ
ポート部3d、架橋部3e等より成り立っている。また前記
配線パターン４は、前記デバイスホール3bに臨むインナ
ーリード部4a及び前記アウタリードホール3cに掛るアウ
タリード4b等よりなる。インナーリード4aは半導体素子
１の突起電極２と接続される。５は前記半導体素子１の
裏面電位を取るための導電性を有するキャップであり、
半田等の接合材６で半導体素子１の裏面と接続され、半
導体素子１の表面より取られたGNDラインとキャリアテ
ープ３の裏面接続用リード4cにより電気的に接続されて
いる。７はエポキシ等よりなる封止用樹脂で、半導体素
子１を外力や外部環境より保護するためのものである。[Prior Art] FIG. 4 is a cross-sectional view showing the structure of a resin-sealed semiconductor device using a TAB (Tape Automated Bonding) method for mounting semiconductor elements using a film carrier tape.
FIG. 5 is a plan view showing a state of the semiconductor device before resin sealing. In the figure, reference numeral 1 denotes a semiconductor element, and 2 denotes a projecting electrode formed on the semiconductor element 1. Reference numeral 3 denotes a carrier tape having, for example, a polyimide base material, and a wiring pattern 4 formed of Cu foil or the like on the surface thereof. The carrier tape 3 has a sprocket hole 3a for feeding the tape.
There are device holes 3b, outer lead holes 3c, support portions 3d, bridge portions 3e, and the like. The wiring pattern 4 includes an inner lead portion 4a facing the device hole 3b, an outer lead 4b extending to the outer lead hole 3c, and the like. The inner lead 4a is connected to the protruding electrode 2 of the semiconductor element 1. 5 is a conductive cap for taking the back potential of the semiconductor element 1;
It is connected to the back surface of the semiconductor element 1 by a bonding material 6 such as solder, and is electrically connected to a GND line taken from the front surface of the semiconductor element 1 by a lead 4c for connecting the back surface of the carrier tape 3. Reference numeral 7 denotes a sealing resin made of epoxy or the like for protecting the semiconductor element 1 from external force or external environment.
以上のように構成された半導体装置を組み立てるに
は、サポート部3d上に形成されたインナーリード部4aの
先端部と半導体素子１の突起電極２とを位置合わせし、
ボンディングツール（図示せず）を用いて両者4a,2を加
熱・圧着する。次に、キャップ５の底部に接合材６のは
んだを配置し、若しくは導電性接着剤を塗布し、前記キ
ャップ５上に前記半導体素子１を位置合わせして乗せ、
前記接合材６なるはんだを加熱・固化させて、若しくは
前記導電性接着剤を加熱・硬化させることにより、半導
体素子１とキャップ５とを接着する。そうして、接続用
リード4cとキャップ５とを接続する。次にサポート部3d
とキャップ５のフランジ部5a間を型締めした状態で封止
用樹脂７により封止して半導体装置が完成する。To assemble the semiconductor device configured as described above, the tip of the inner lead portion 4a formed on the support portion 3d is aligned with the projecting electrode 2 of the semiconductor element 1,
Using a bonding tool (not shown), both 4a and 2 are heated and pressed. Next, the solder of the bonding material 6 is placed on the bottom of the cap 5 or a conductive adhesive is applied, and the semiconductor element 1 is positioned and placed on the cap 5,
The semiconductor element 1 and the cap 5 are bonded to each other by heating and solidifying the solder as the bonding material 6 or by heating and curing the conductive adhesive. Then, the connection lead 4c and the cap 5 are connected. Next, support section 3d
The semiconductor device is completed by sealing with a sealing resin 7 in a state in which the mold and the flange 5a of the cap 5 are clamped.
その後、この様にキャリアテープ３上に形成された半
導体装置を、架橋部3c、アウタリード4b部より切り離し
て、プリント配線基板（図示せず）上へアウタリード4b
を電気的に接続させて実装している。Thereafter, the semiconductor device thus formed on the carrier tape 3 is separated from the bridging portion 3c and the outer lead 4b, and the outer lead 4b is placed on a printed wiring board (not shown).
Are electrically connected and mounted.
従来の半導体装置は以上のように構成されているの
で、パッケージとしてのシールド効果がなく、外部から
のノイズ等に対して半導体素子１の誤動作が生じたり、
又半導体素子１から出るノイズも外部へもれてしまうと
いう問題がある。さらに、半導体装置の発熱源である半
導体素子１の表面側（回路面）からの放熱が行われず、
樹脂封止パッケージの欠点である高熱抵抗という問題上
消費電力の大きい半導体素子１には安価な封止用樹脂は
使えないという問題点があった。又、一般に大消費電力
の半導体素子はセラミックパッケージに収められ、非常
に高価なものとなっている。Since the conventional semiconductor device is configured as described above, there is no shielding effect as a package, and a malfunction of the semiconductor element 1 occurs due to external noise or the like.
Further, there is a problem that noise emitted from the semiconductor element 1 leaks to the outside. Further, heat is not dissipated from the surface side (circuit surface) of the semiconductor element 1 which is a heat source of the semiconductor device,
Due to the problem of high thermal resistance, which is a drawback of the resin-sealed package, there has been a problem that inexpensive sealing resin cannot be used for the semiconductor element 1 with large power consumption. In general, a semiconductor device with large power consumption is housed in a ceramic package and is very expensive.
この発明は上記のような問題点を解消するためになさ
れたもので、半導体パッケージにシール効果をもたせる
ことができるとともに、樹脂封止パッケージでありなが
ら熱抵抗の小さい半導体装置を得ることを目的とする。The present invention has been made in order to solve the above-described problems, and it is an object of the present invention to provide a semiconductor device having a small thermal resistance while being able to have a sealing effect on a semiconductor package and being a resin-sealed package. I do.
この発明に係る半導体装置は、少なくとも半導体素子
の表面を覆いかつ当該表面からの熱を逃すべく表面に向
って凸状に形成され接近した導電性のプレートを備え、
前記プレートを電気的に接地するとともに、前記プレー
トの一部が封止樹脂表面に露出するように前記半導体素
子及び前記プレートを一体的に樹脂封止成形したもので
ある。また、前記プレートに高熱伝導性材料を使用した
ものである。The semiconductor device according to the present invention includes a conductive plate that covers at least the surface of the semiconductor element and is formed in a convex shape and approached toward the surface so as to release heat from the surface,
The semiconductor element and the plate are integrally resin-molded so that the plate is electrically grounded and a part of the plate is exposed on a sealing resin surface. Further, a high thermal conductive material is used for the plate.
この発明に係るプレートは、導電性を有し、電気的に
接地させているので、半導体パッケージの表面より入っ
てくる電磁気的ノイズに対してシールドの効果を持たせ
られるとともに、半導体素子から発せられる電磁気的ノ
イズも外部へもれることがなくなり、他の半導体素子等
に悪影響を与えることもなくなる。また、導電性のプレ
ートを半導体素子の表面に接近させ、プレートの一部を
封止樹脂表面に露出するように樹脂封止成形することに
より、半導体素子表面から発する熱を導電性プレートを
介して有効に外部に放出する。Since the plate according to the present invention has conductivity and is electrically grounded, the plate has a shielding effect against electromagnetic noise coming from the surface of the semiconductor package and is emitted from the semiconductor element. Electromagnetic noise does not leak to the outside, and does not adversely affect other semiconductor elements. Further, by bringing the conductive plate close to the surface of the semiconductor element and performing resin sealing molding so that a part of the plate is exposed on the sealing resin surface, heat generated from the semiconductor element surface is transmitted through the conductive plate. Effectively release to the outside.
さらに前記プレートを高熱伝導性の材料で構成するこ
とにより、半導体素子表面上の熱抵抗が、封止用樹脂の
みの構成に比べて減少する。Further, when the plate is made of a material having high thermal conductivity, the thermal resistance on the surface of the semiconductor element is reduced as compared with the structure using only the sealing resin.
以下この発明の一実施例を図について説明する。第１
図において、１〜７は従来の半導体装置に示したものと
同一又は相当部材を示すのでその説明を省略する。８は
導電性を有するプレートで、このプレート８はキャリア
テープ３上の配線パターン４と導電性樹脂を介して電気
的な接続がなされて、GNDに落とされている。又、半導
体素子１の裏面側もはんだ等の接合材６によりキャップ
５と接着され、GNDに落とされている。すなわちこの半
導体素子１はほぼ完全にシールドされた構造となる。こ
のプレート８は絶縁性材料のものでも良いが、少なくと
も片面は導電性の膜で覆うものとする。An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, reference numerals 1 to 7 denote the same or corresponding members as those shown in the conventional semiconductor device, and thus the description thereof will be omitted. Reference numeral 8 denotes a conductive plate. The plate 8 is electrically connected to the wiring pattern 4 on the carrier tape 3 via a conductive resin, and is dropped to GND. The back surface of the semiconductor element 1 is also bonded to the cap 5 with a bonding material 6 such as solder and dropped to GND. That is, the semiconductor element 1 has a structure almost completely shielded. The plate 8 may be made of an insulating material, but at least one surface is covered with a conductive film.
さらにプレート８を高熱伝導性の材料を用いることに
より、半導体素子１の発生源である該半導体素子１の表
面からの熱を、これまでの封止用樹脂７を介してのみ逃
がしていたのに比べ、効率よく半導体装置の外部へ伝え
ることができる。この際にプレート８はできるだけ半導
体素子１の表面に近づけ、さらにはプレート８の一部を
半導体装置の表面へ露出させ、これに放熱フィン９をつ
ければ、より放熱に対して効果的となる。Further, by using a material having high thermal conductivity for the plate 8, heat from the surface of the semiconductor element 1, which is a source of the semiconductor element 1, is released only through the conventional sealing resin 7. In comparison with this, it can be efficiently transmitted to the outside of the semiconductor device. At this time, if the plate 8 is brought as close as possible to the surface of the semiconductor element 1 and a part of the plate 8 is exposed to the surface of the semiconductor device, and the radiation fins 9 are attached to the plate 8, the radiation becomes more effective.
また、樹脂封止の際に封止用樹脂７が半導体素子１の
周囲へよく回り込めるように、プレート８には穴などを
設けたり、メッシュ状の材料を使うことも考えられる
（図示せず）。半導体装置の使用材料特性によっては、
パッケージに反り等が考えられ、それを防ぐ手段とし
て、封止用樹脂７の厚みでコントロールする際に、第２
図に示すようにキャップ５の裏面まで封止用樹脂７で覆
う場合もある。It is also conceivable to provide a hole or the like in the plate 8 or use a mesh-like material so that the sealing resin 7 can easily go around the semiconductor element 1 during resin sealing (not shown). ). Depending on the material properties of the semiconductor device,
The package may be warped or the like. As a means for preventing the warpage, a second method is used when controlling the thickness of the sealing resin 7.
As shown in the figure, the back surface of the cap 5 may be covered with the sealing resin 7 in some cases.
また、上記実施例においては、フィルムキャリアテー
プ等を用いた半導体装置について述べたが、第３図に示
すようにリードフレーム上に半導体素子を取付けて樹脂
封止成形するタイプの半導体装置にも適用でき、上記実
施例と同様の効果が得られる。すなわち第３図におい
て、８は導電性のプレートであり、リードフレームのう
ちGND電位のリード11と電気的に接続され、シールドの
役割を果す構造となっている。またこのプレート８を高
熱伝導性の材料より構成することにより放熱効果を高め
ることができる。なお、第３図中、10は金属細線を示
す。In the above embodiment, the semiconductor device using a film carrier tape or the like has been described. However, as shown in FIG. 3, the present invention is also applied to a semiconductor device in which a semiconductor element is mounted on a lead frame and molded with a resin. Thus, effects similar to those of the above embodiment can be obtained. That is, in FIG. 3, reference numeral 8 denotes a conductive plate, which is electrically connected to the lead 11 having the GND potential in the lead frame and has a structure serving as a shield. In addition, when the plate 8 is made of a material having high thermal conductivity, the heat radiation effect can be enhanced. In FIG. 3, reference numeral 10 denotes a thin metal wire.
以上のようにこの発明によれば、半導体素子の表面側
にも導電性を有するプレートを設置する構造としたの
で、半導体装置外部からの電磁気的ノイズの侵入及び内
部からの電磁気的ノイズの漏れを防ぐことができる。ま
た、導電性のプレートを半導体素子の表面に接近させプ
レートの一部を封止樹脂表面に露出するように樹脂封止
成形することにより、半導体素子表面から発する熱を導
電性プレートを介して有効に外部に放出することができ
る。またこのプレートを高熱伝導性の材料により構成し
たことで、半導体素子の表面からパッケージの表面まで
の熱抵抗を小さくし、放熱効果が上げられ、消費電力の
大きい半導体素子が使える。しかもトランスファーモー
ルドによる樹脂封止が可能なため、安価な半導体装置が
得られる。As described above, according to the present invention, since a plate having conductivity is provided also on the surface side of the semiconductor element, electromagnetic noise intrusion from outside the semiconductor device and leakage of electromagnetic noise from the inside can be prevented. Can be prevented. In addition, heat generated from the surface of the semiconductor element is effectively transmitted through the conductive plate by forming the conductive plate close to the surface of the semiconductor element and molding the resin so that a part of the plate is exposed on the sealing resin surface. Can be released to the outside. In addition, since this plate is made of a material having high thermal conductivity, the heat resistance from the surface of the semiconductor element to the surface of the package is reduced, the heat radiation effect is improved, and a semiconductor element with large power consumption can be used. Moreover, since resin molding can be performed by transfer molding, an inexpensive semiconductor device can be obtained.
第１図はこの発明の一実施例による半導体装置を示す断
面図、第２図及び第３図はこの発明の他の実施例による
半導体装置を示す断面図、第４図は従来の半導体装置を
示す断面図、第５図は前記従来の半導体装置の樹脂封止
前の状態を示す平面図である。 図中、１は半導体素子、２は突起電極、３はキャリアテ
ープ、3dはサポート部、４は配線パターン、4aはインナ
ーリード、4bはアウタリード、５はキャップ、６は接合
材、７は封止用樹脂、８はプレート、９は放熱フィンを
示す。 なお、図中同一符号は同一又は相当部分を示す。FIG. 1 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views showing a semiconductor device according to another embodiment of the present invention, and FIG. FIG. 5 is a plan view showing a state of the conventional semiconductor device before resin sealing. In the figure, 1 is a semiconductor element, 2 is a protruding electrode, 3 is a carrier tape, 3d is a support portion, 4 is a wiring pattern, 4a is an inner lead, 4b is an outer lead, 5 is a cap, 6 is a bonding material, and 7 is sealing. Resin, 8 is a plate, and 9 is a radiating fin. In the drawings, the same reference numerals indicate the same or corresponding parts.
フロントページの続き (72)発明者 関 博司 兵庫県伊丹市瑞原４丁目１番地 三菱電 機株式会社北伊丹製作所内 (72)発明者 寺岡 康宏 兵庫県伊丹市瑞原４丁目１番地 三菱電 機株式会社北伊丹製作所内 (72)発明者 上田 哲也 兵庫県伊丹市瑞原４丁目１番地 三菱電 機株式会社北伊丹製作所内 (56)参考文献 特開 昭59−72748（ＪＰ，Ａ) 実開 昭63−140698（ＪＰ，Ｕ) 実開 昭63−90845（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/00 - 23/56 Continued on the front page (72) Inventor Hiroshi Seki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. Kita-Itami Works (72) Inventor Yasuhiro Teraoka 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Inside Kita Itami Works (72) Inventor Tetsuya Ueda 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Inside Kita Itami Works Mitsubishi Electric Corporation (56) References JP-A-59-7748 (JP, A) 140698 (JP, U) Fully open 1988-90845 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 23/00-23/56
Claims (2)
の表面を覆いかつ当該表面からの熱を逃すべく表面に向
って凸状に形成され接近した導電性のプレートを備え、
前記プレートを電気的に接地するとともに、前記プレー
トの一部が封止樹脂表面に露出するように前記半導体素
子及び前記プレートを一体的に樹脂封止成形したことを
特徴とする半導体装置。1. A semiconductor device comprising: a semiconductor device; and a conductive plate formed at a position close to the surface of the semiconductor device so as to cover at least a surface of the semiconductor device and release heat from the surface.
A semiconductor device, wherein the plate is electrically grounded, and the semiconductor element and the plate are integrally resin-molded so that a part of the plate is exposed on a sealing resin surface.
構成した請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said plate is made of a material having high thermal conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100910A JP2895504B2 (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100910A JP2895504B2 (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02278752A JPH02278752A (en) | 1990-11-15 |
| JP2895504B2 true JP2895504B2 (en) | 1999-05-24 |
Family
ID=14286498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1100910A Expired - Fee Related JP2895504B2 (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2895504B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9601408B2 (en) | 2012-10-25 | 2017-03-21 | Mitsubishi Electric Corporation | Semiconductor device |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3322429B2 (en) * | 1992-06-04 | 2002-09-09 | 新光電気工業株式会社 | Semiconductor device |
| JPH0831988A (en) * | 1994-07-20 | 1996-02-02 | Nec Corp | Sealing structure of tape carrier package |
| KR100349379B1 (en) * | 1998-10-27 | 2002-12-16 | 주식회사 현대 디스플레이 테크놀로지 | Printed circuit board structure with electromagnetic wave blocking function |
| US7714419B2 (en) * | 2007-12-27 | 2010-05-11 | Stats Chippac Ltd. | Integrated circuit package system with shielding |
| JP5471364B2 (en) * | 2009-11-27 | 2014-04-16 | 日本電気株式会社 | Semiconductor package |
| JP5354376B2 (en) * | 2009-11-27 | 2013-11-27 | 大日本印刷株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP5626402B2 (en) * | 2013-04-24 | 2014-11-19 | 大日本印刷株式会社 | Semiconductor device, method for manufacturing semiconductor device, and shield plate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972748A (en) * | 1982-10-20 | 1984-04-24 | Nec Kyushu Ltd | Semiconductor device |
-
1989
- 1989-04-19 JP JP1100910A patent/JP2895504B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9601408B2 (en) | 2012-10-25 | 2017-03-21 | Mitsubishi Electric Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02278752A (en) | 1990-11-15 |
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