JP2970952B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2970952B2 JP2970952B2 JP3100078A JP10007891A JP2970952B2 JP 2970952 B2 JP2970952 B2 JP 2970952B2 JP 3100078 A JP3100078 A JP 3100078A JP 10007891 A JP10007891 A JP 10007891A JP 2970952 B2 JP2970952 B2 JP 2970952B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- semiconductor element
- semiconductor
- shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体素子を電磁的
外乱信号から遮蔽するための構造を有する半導体装置お
よびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device having a structure for shielding a semiconductor element from an electromagnetic disturbance signal .
And its manufacturing method .
【０００２】[0002]
【従来の技術】近年、電子技術の進歩は著しく、その応
用分野は民生、産業の分野を問わず拡がるとともに、様
々な機器に用いられている。また、その使用環境も様々
で、なかには電子機器及び、それを構成する半導体装置
の動作に対して極めて悪い影響を与える電磁的外乱信号
を有する環境も多く、逆に電子機器自身がその発生源と
成りうる場合も少なくない。電磁的外乱信号による影響
を防止する一つの対策として、導電性材料を用いて電子
機器自身あるいは、各半導体装置を個々に、電磁的外乱
信号から遮蔽保護する方法があげられる。2. Description of the Related Art In recent years, the progress of electronic technology has been remarkable, and its application fields have expanded in both consumer and industrial fields, and it has been used in various devices. In addition, the usage environment is various, and in many cases, there are many environments having an electromagnetic disturbance signal that has a very bad influence on the operation of the electronic device and the semiconductor device constituting the electronic device. There are many cases where this is possible. As one measure for preventing the influence of the electromagnetic disturbance signal, there is a method of shielding and protecting the electronic device itself or each semiconductor device individually from the electromagnetic disturbance signal using a conductive material.
【０００３】従来、この種の遮蔽器は被遮蔽物とは異な
った構成物を用い、電子機器への実装時に被遮蔽物とと
もに装着されるのが一般的で、以下、その構成について
図９および図１０を参照しながら説明する。図９は従来
の半導体装置の構造を示す外観透視斜視図、図１０は同
半導体装置の内部構造を示す側面断面図である。Conventionally, this type of shield uses a different structure from the shielded object, and is generally mounted together with the shielded object at the time of mounting to an electronic device. This will be described with reference to FIG. FIG. 9 is an external perspective perspective view showing the structure of a conventional semiconductor device, and FIG. 10 is a side sectional view showing the internal structure of the semiconductor device.
【０００４】図に示すごとく、従来の半導体装置は、半
導体素子１をリードフレームの半導体素子搭載部２に載
置し、半導体素子１の電極体を金属細線３によってリー
ドフレームの電極部５に電気的接続をしたのち、外囲器
４に封入し、その周囲を覆う導電性材料により形成され
た遮蔽器９が装着されている。この遮蔽器９は所定の電
位を与えられることではじめて、電磁的外乱信号を遮蔽
するという機能を有することになるが、上記構成のまま
では遮蔽器９はいずれからも電気的に絶縁されており、
目的とする遮蔽器としてまったく機能しない。所定の電
位を与えるには、半導体素子１の所定の電極体と選択的
に電気的接続をし、遮蔽器９を所定の電位に保つことが
あげられ、これは最も簡易的であるが、被遮蔽物と遮蔽
器の間の距離が最小ですむため最も効果がある接続方法
である。As shown in FIG. 1, in a conventional semiconductor device, a semiconductor element 1 is mounted on a semiconductor element mounting portion 2 of a lead frame, and an electrode body of the semiconductor element 1 is electrically connected to an electrode portion 5 of the lead frame by a thin metal wire 3. After making a proper connection, a shield 9 made of a conductive material that covers the periphery of the enclosure 4 and is sealed in the envelope 4 is attached. The shield 9 has a function of shielding an electromagnetic disturbance signal only when given a predetermined potential. However, the shield 9 is electrically insulated from any of the shields 9 in the above configuration. ,
Does not function as the intended shield at all. In order to apply a predetermined potential, it is necessary to selectively make electrical connection with a predetermined electrode body of the semiconductor element 1 and to keep the shield 9 at a predetermined potential. This is the most effective connection method because the distance between the shield and the shield is minimal.
【０００５】具体的には、半導体装置を回路基板等に実
装するうえで、リードフレームの所定の電極部５と遮蔽
器電極部１０を金属ロウ材等を用い電気的に接続をする
ことで、遮蔽器９には、接続される所定の電極部５と同
じ電位が与えられることになり、電磁的外乱信号を遮蔽
するという本来の機能を果たすことになる。Specifically, when mounting a semiconductor device on a circuit board or the like, predetermined electrode portions 5 of a lead frame and shield electrode portions 10 are electrically connected by using a metal brazing material or the like. The same potential as that of the predetermined electrode unit 5 to be connected is applied to the shield 9, and the shield 9 performs its original function of shielding electromagnetic disturbance signals.
【０００６】[0006]
【発明が解決しようとする課題】このような従来の半導
体装置において、遮蔽器９を機能させるためには、実装
時での電気的接続を必要とするため組み立て工数並び
に、部品点数が増すこと、また、外囲器４の外部に遮蔽
器９を設けた構造のため、装置の小型化が困難で高密度
実装には向かない等の問題があった。また、半導体素子
１は外囲器４を介して遮蔽器９と隔たることとなり、そ
の距離ｄ′は半導体素子１表面からの外囲器厚により規
制されてしまう。その効果をより高めるためには、この
距離ｄ′をできるかぎり小さくすることが不可欠とな
り、外囲器厚（距離ｄ′）が大きくなるような場合は、
電磁的外乱信号に対し十分な遮蔽効果を発揮できていな
いという問題もあった。In such a conventional semiconductor device, in order for the shield 9 to function, electrical connection is required at the time of mounting, so that the number of assembly steps and the number of parts are increased. In addition, the structure in which the shield 9 is provided outside the envelope 4 has a problem that it is difficult to reduce the size of the device and is not suitable for high-density mounting. Further, the semiconductor element 1 is separated from the shield 9 via the envelope 4, and the distance d 'is restricted by the thickness of the envelope from the surface of the semiconductor element 1. In order to further enhance the effect, it is essential to make the distance d 'as small as possible. If the thickness of the envelope (the distance d') becomes large,
There is also a problem that a sufficient shielding effect cannot be exerted on an electromagnetic disturbance signal.
【０００７】この発明の目的は、上記問題を解決するも
ので、実装工程が簡便にすみ、安価で小型の構造で、電
磁的外乱信号に対し高い遮蔽効果を有する半導体装置お
よびその製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. The semiconductor device and the semiconductor device have a simple mounting process, are inexpensive and have a small structure, and have a high shielding effect against electromagnetic disturbance signals .
And a method for producing the same.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の半導体装
置は、半導体素子と、半導体素子の載置部と半導体素子
の所定の電極体に電気的に接続される電極部とを有する
リードフレームと、半導体素子を介してリードフレーム
に対向配置され半導体素子の表面要域を所定距離離間し
て覆う遮蔽板とを設け、半導体素子とリードフレームと
遮蔽板とを一体的に外囲器に封入している。請求項２記
載の半導体装置は、請求項１記載の半導体装置におい
て、遮蔽板と半導体素子の所定の電極体とを電気的に接
続したことを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor element;
Having an electrode portion electrically connected to the predetermined electrode body
Lead frame and lead frame via semiconductor element
The required area of the surface of the semiconductor element
A shielding plate for covering the semiconductor element and the lead frame.
The shielding plate is integrally enclosed in an envelope . According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the shielding plate is electrically connected to a predetermined electrode body of the semiconductor element.
【０００９】請求項３記載の半導体装置は、請求項１記
載の半導体装置において、遮蔽板の端にリードフレーム
側へ折り曲げた屈曲部を設け、屈曲部の端を外囲器の外
に露出させてリードフレームの所定の電極部に接続する
ための遮蔽板の電極部としたことを特徴とする。請求項
４記載の半導体装置は、請求項１，２または３記載の半
導体装置において、外囲器を樹脂封止により形成したこ
とを特徴とする。請求項５記載の半導体装置の製造方法
は、第１のリードフレームの素子載置部に半導体素子を
載置し、第１のリードフレームの電極部の一部と半導体
素子の電極体とを金属細線で接続し、遮蔽板を有する第
２のリードフレームと第１のリードフレームとを位置合
わせすることにより遮蔽板を半導体素子を介して素子載
置部と対向させて配置し、半導体素子、金属配線および
遮蔽板を樹脂封止するものである。 請求項６記載の半導
体装置の製造方法は、請求項５記載の半導体装置の製造
方法において、第１のリードフレームに設けた位置合わ
せ穴と第２のリードフレームに設けた位置合わせ穴を用
いて、第１のリードフレームと第２のリードフレームと
を位置合わせすることを特徴とする。 According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a bent portion bent toward the lead frame is provided at an end of the shielding plate, and the end of the bent portion is exposed outside the envelope. And an electrode portion of a shielding plate for connection to a predetermined electrode portion of the lead frame. A semiconductor device according to a fourth aspect is the semiconductor device according to the first, second or third aspect, wherein the envelope is formed by resin sealing. A method for manufacturing a semiconductor device according to claim 5.
Is to mount the semiconductor element on the element mounting portion of the first lead frame.
A part of the electrode portion of the first lead frame is mounted and the semiconductor is mounted.
The electrode body of the element is connected with a thin metal wire, and the
Align the second lead frame with the first lead frame.
The shield plate is mounted on the device via the semiconductor device.
Semiconductor device, metal wiring and
The shielding plate is sealed with a resin. A semiconductor according to claim 6.
A method of manufacturing a semiconductor device, comprising the steps of:
In the method, an alignment provided on a first leadframe is provided.
Use the alignment holes provided on the second lead frame
And a first lead frame and a second lead frame
Is positioned.
【００１０】[0010]
【作用】この発明の構成によれば、半導体素子およびリ
ードフレームとともに半導体素子の表面要域を覆う遮蔽
板を一体的に外囲器に封入しているため、遮蔽板を半導
体素子に近接して配置することができ、遮蔽板を所定の
電位に保つことにより、半導体装置の動作に関わる電磁
的外乱信号の影響は排除され、安定で良好な動作を得る
ことができる。According to the structure of the present invention, the semiconductor device and the resource
A shield that covers the critical area of the surface of the semiconductor device together with the hardware frame
Since the plate is integrally enclosed in the envelope, the shield plate can be arranged close to the semiconductor element, and by maintaining the shield plate at a predetermined potential, electromagnetic disturbances related to the operation of the semiconductor device can be achieved. The influence of the signal is eliminated, and stable and good operation can be obtained.
【００１１】[0011]
【実施例】〔第１の実施例〕この発明の第１の実施例に
ついて図１，図２，図３および図４を参照しながら説明
する。図１はこの発明の第１の実施例の半導体装置の構
造を示す外観透視斜視図、図２は同半導体装置の内部構
造を示す側面断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. FIG. FIG. 1 is an external perspective perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a side sectional view showing the internal structure of the semiconductor device.
【００１２】この半導体装置は、まず、半導体素子１を
導電性接着剤等により第１リードフレームの半導体素子
搭載部２（素子載置部）に載置し、半導体素子１の電極
体を金属細線３によって第１リードフレームの電極部５
と電気的接続をする。次に遮蔽平板（導電性材料）１１
を半導体素子１を挟んで、半導体素子搭載部２と対向す
るように配置する。遮蔽平板１１は第２リードフレーム
と一体になっている。すなわち、第２リードフレームの
一部が遮蔽平板１１として構成されている。そして、半
導体素子１，金属細線３，半導体素子搭載部２および遮
蔽平板１１は樹脂からなる外囲器４に封入されている。
第１および第２リードフレームの一部は電極として外囲
器４の表面から取り出されている。半導体素子１と遮蔽
平板１１とは図２に示したように、所定の距離ｄをもっ
て離間している。この距離ｄは遮蔽平板１１と金属細線
３とが接触しない程度で、高い遮蔽効果を得るためでき
るだけ短く選ばれている。 In this semiconductor device, first, a semiconductor element 1 is mounted on a semiconductor element mounting section 2 (element mounting section) of a first lead frame with a conductive adhesive or the like, and an electrode body of the semiconductor element 1 is thinned with a thin metal wire. 3, the electrode part 5 of the first lead frame
The electrical connection with. Next, a shielding plate (conductive material) 11
Faces the semiconductor element mounting portion 2 with the semiconductor element 1 interposed therebetween.
So that The shielding plate 11 is the second lead frame
It is united with. That is, the second lead frame
A part is configured as a shielding flat plate 11. And half
Conductive element 1, metal thin wire 3, semiconductor element mounting part 2 and shielding
The shielding plate 11 is enclosed in an envelope 4 made of resin.
Part of the first and second lead frames are surrounded as electrodes
It has been removed from the surface of the container 4. Semiconductor element 1 and shielding
As shown in FIG. 2, the flat plate 11 has a predetermined distance d.
Away. This distance d is the distance between the shielding flat plate 11 and the thin metal wire.
3 can be used to obtain a high shielding effect without contact
As short as possible.
【００１３】図３および図４はこの発明の第１の実施例
における半導体装置の組立方法を示す概略図である。 ま
ず、図３に示したように第１リードフレームが用意され
る。第１リードフレームは符号２，５，６，７および８
で示された箇所全体を指す。第１リードフレームの半導
体素子搭載部２には半導体素子１が固着され、第１リー
ドフレームの電極部５と半導体素子１の所定の電極体と
が金属細線３によって接続されている。中桟部６は、半
導体素子１が搭載部２に固着される時、また、外囲器４
に封入される時の強度を保つために電極部５と他の電極
部５との間に架橋されている。下桟部７も中桟部６とほ
ぼ同じ目的で設けられているが、中桟部６に比べて幅広
い下桟部７には位置合わせ穴８が設けられ、組立時のイ
ンデックスとしても利用される。第２リードフレーム
は、遮蔽平板１１，遮蔽平板電極部１２，上桟部１３お
よび位置合わせ穴１４を備えている。遮蔽平板１１は第
２リードフレームにあらかじめ圧縮曲げ加工が施され、
上桟部１３とは所定の段差（距離）をもって構成されて
いる。その距離は、第１リードフレームに固着されてい
る半導体素子１および金属細線３の高さに応じて決めら
れる。 また、第２リードフレームは第１リードフレーム
に対して所定の位置に配置されるが、その位置決めは成
形金型（図示せず）に設けた案内ピンと、それぞれのリ
ードフレームの下桟部７，上桟部１３に設けた位置合わ
せ穴８，１４によって行われる。図４は第１リードフレ
ームと第２リードフレームとを位置合わせした状態を示
す。図４に示すように位置合わせが終わると成形金型に
配置され、所定の樹脂封止が行われ、外囲器４が形成さ
れる。その後、下桟部７，中桟部６および上桟部１３を
切断して取り除き単体に分離される。 FIGS. 3 and 4 show a first embodiment of the present invention .
FIG. 5 is a schematic view showing a method of assembling a semiconductor device in FIG. Ma
First, a first lead frame is prepared as shown in FIG.
You. The first lead frame has reference numerals 2, 5, 6, 7 and 8
Indicates the entire location indicated by. Semiconductor of the first lead frame
The semiconductor element 1 is fixed to the body element mounting portion 2, and the first lead
Electrode part 5 of the semiconductor frame 1 and a predetermined electrode body of the semiconductor element 1
Are connected by a thin metal wire 3. The middle pier 6 is half
When the conductor element 1 is fixed to the mounting portion 2,
The electrode part 5 and other electrodes to maintain the strength when sealed in
It is bridged between the portion 5. Lower part 7 is also similar to middle part 6
Although it is provided for the same purpose, it is wider than the middle pier 6
An alignment hole 8 is provided in the lower cross section 7 so that
Also used as an index. Second lead frame
Are the shield plate 11, the shield plate electrode part 12, the upper rail 13 and
And an alignment hole 14. The shielding plate 11 is
2 Compression bending is applied to the lead frame in advance,
The upper cross section 13 is configured with a predetermined step (distance).
I have. The distance is fixed to the first lead frame.
Determined according to the height of the semiconductor element 1 and the metal wire 3
It is. The second lead frame is the first lead frame.
Is located at a predetermined position with respect to
Guide pins provided on a mold (not shown)
Alignment provided on the lower and upper cross sections 7 and 13 of the frame
The holes 8 and 14 are used. Figure 4 shows the first lead frame.
Shows the state where the camera and the second lead frame are aligned.
You. When the alignment is completed as shown in FIG.
It is placed, a predetermined resin sealing is performed, and the envelope 4 is formed.
It is. Thereafter, the lower cross section 7, the middle cross section 6, and the upper cross section 13 are removed.
It is cut off and separated into single pieces.
【００１４】このように構成された本発明の半導体装置
は、回路基板に実装されるときに、遮蔽平板１１に所定
の電位、たとえば接地電位が与えられる。半導体素子搭
載部２を有する第１リードフレームの電極部５の電位が
たとえば接地電位であれば、遮蔽平板電極部１２を電極
部５と共通接続すればよい。この場合、半導体素子１の
全体が接地電位で挟み覆われるようになり、半導体装置
の外部からの不所望な電磁波、ノイズ、静電気などから
遮蔽することができる。なお、遮蔽平板電極部１２に与
える電位は接地電位に限定されない。たとえば、電源電
圧や所定の直流電圧であってもよい。 [0014] The semiconductor device of the present invention thus configured.
Is fixed on the shielding plate 11 when mounted on the circuit board.
, For example, a ground potential. Semiconductor device
The potential of the electrode portion 5 of the first lead frame having the mounting portion 2 is
For example, if the ground potential, the shield plate electrode section 12
What is necessary is just to connect in common with the part 5. In this case, the semiconductor element 1
The whole is now sandwiched and covered by ground potential,
From unwanted electromagnetic waves, noise, static electricity, etc.
Can be shielded. It should be noted that the shielding plate electrode portion 12
The potential obtained is not limited to the ground potential. For example, power supply
Pressure or a predetermined DC voltage.
【００１５】以上のように、この発明の第１の実施例に
よれば、遮蔽平板１１が半導体装置の外囲器４内部に一
体的に形成され、半導体素子１の表面全要域を覆うとと
もに、その表面より物理的に可能な限り最小の距離ｄに
配設され、かつ、所定の電位に保たれた遮蔽平板１１に
より半導体装置の動作に関わる電磁的外乱信号の影響は
排除され、安定で良好な動作を得ることができる。As described above, according to the first embodiment of the present invention, the shielding plate 11 is formed integrally inside the envelope 4 of the semiconductor device, and covers the entire surface of the semiconductor element 1. The shield plate 11, which is disposed at the minimum distance d physically possible from the surface thereof and is kept at a predetermined potential, eliminates the influence of an electromagnetic disturbance signal related to the operation of the semiconductor device, and is stable. Good operation can be obtained.
【００１６】〔第２の実施例〕この発明の第２の実施例
について図５，図６，図７および図８を参照しながら説
明する。図５はこの発明の第２の実施例の半導体装置の
構造を示す外観透視斜視図、図６は同半導体装置の内部
構造を示す側面断面図である。Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. 5, 6, 7 and 8. FIG. 5 is an external perspective perspective view showing the structure of a semiconductor device according to a second embodiment of the present invention, and FIG. 6 is a side sectional view showing the internal structure of the semiconductor device.
【００１７】この半導体装置は、第１の実施例と同様、
同じ部品材料によって構成され、また、その組み立て方
法、電磁的外乱信号を遮蔽する構造に関して何ら変わる
ことなく同様の効果を有するが、第１の実施例と異なる
点は、その構造において既に第２リードフレームの遮蔽
平板（導電性材料）３１が、その遮蔽平板電極部３２を
介して、第１リードフレームの所定の電極部２２（半導
体素子１が載置された半導体素子搭載部２１を有する電
極部）と選択的に電気的接続されている点である。この
第１の実施例と異なる点について、図７および図８を参
照しながら説明する。This semiconductor device is similar to that of the first embodiment.
It is made of the same component material, and has the same effect without any change in the method of assembling and the structure for shielding the electromagnetic disturbance signal, except that the second embodiment differs from the first embodiment in the structure of the second lead. The shielding plate (conductive material) 31 of the frame is connected to the predetermined electrode portion 22 (the electrode portion having the semiconductor element mounting portion 21 on which the semiconductor element 1 is mounted) of the first lead frame via the shielding plate electrode portion 32. ) Is selectively electrically connected to Differences from the first embodiment will be described with reference to FIGS.
【００１８】図７および図８は同半導体装置の組み立て
工程の構成を示す斜視図である。第１、第２それぞれの
リードフレームの配設状態が、第１の実施例とは異な
り、第１リードフレームの電極部２２の伸長方向と一致
した方向に第２リードフレームの電極部３２が位置する
ため、外囲器４を形成後、それぞれが重複することにな
る。ただし、この状態ではそれぞれが面接触をするに過
ぎず、残る組み立て工程におき、第１、第２リードフレ
ームの下桟部２４、３５、中桟部２３、３４を切断、取
り除いたのち、外囲器４より露出したそれぞれの電極部
２２、３２を金属ロウ材で被覆するよう表面処理を施す
と、それぞれは必然的に電気的接続されることとなる。
また、この表面処理は、電極部材の酸化防止、実装での
ロウ付け性向上等、製品価値を高める目的から従来より
実施されているもので、ここで、あえて用いたものでは
なく、組み立ての工数を増すものではない。最後にそれ
ぞれのリードフレームの上桟部２５、３６が切断、単体
に分離される。なお、２６ａ，２６ｂは第１リードフレ
ームの位置あわせ穴、３３は不完全電極、３７ａ，３７
ｂは第２リードフレームの位置あわせ穴である。FIGS. 7 and 8 are perspective views showing a structure of an assembling process of the semiconductor device. The arrangement state of the first and second lead frames is different from that of the first embodiment, and the electrode section 32 of the second lead frame is positioned in the direction coinciding with the extension direction of the electrode section 22 of the first lead frame. Therefore, after the envelopes 4 are formed, they overlap each other. However, in this state, they are only in surface contact with each other. In the remaining assembling process, the lower and upper rails 24, 35 and the middle rails 23, 34 of the first and second lead frames are cut and removed. When surface treatment is performed so as to cover the respective electrode portions 22 and 32 exposed from the enclosure 4 with a metal brazing material, they are inevitably electrically connected.
In addition, this surface treatment is conventionally performed for the purpose of enhancing the product value, such as preventing oxidation of the electrode member and improving the brazing property in mounting. Does not increase. Finally, the upper rails 25 and 36 of each lead frame are cut and separated into single pieces. 26a and 26b are positioning holes of the first lead frame, 33 is an incomplete electrode, 37a and 37
b is an alignment hole of the second lead frame.
【００１９】以上のように、この発明の第２の実施例に
よれば第１の実施例と同様の効果が得られることはいう
までもなく、そのうえ半導体装置の構造において既に第
２リードフレームの遮蔽平板３１が第１リードフレーム
の所定の電極部２２と選択的に電気的接続されているた
め、回路基板等への実装において、あえてこれらを電気
的接続する作業が必要でなく、工数の削減も可能とす
る。As described above, according to the second embodiment of the present invention, it is needless to say that the same effect as that of the first embodiment can be obtained. Since the shield flat plate 31 is selectively electrically connected to the predetermined electrode portion 22 of the first lead frame, there is no need to dare to electrically connect these in mounting on a circuit board or the like, thereby reducing man-hours. Is also possible.
【００２０】なお、各実施例において、半導体素子１の
種別は何ら限定していないが、全ての半導体素子に関し
応用することができる。In each embodiment, the type of the semiconductor element 1 is not limited at all, but can be applied to all the semiconductor elements.
【００２１】[0021]
【発明の効果】この発明の半導体装置によれば、半導体
素子の表面要域を覆い所定の電位に保たれる遮蔽板を半
導体素子に近接して配置し、外囲器内部に一体的に形成
することにより、実装工程が簡便にすみ、安価で小型の
構造を有するとともに、電磁的外乱信号に対し高い遮蔽
効果を有し、安定で良好な動作を得ることができる。Effects of the Invention] According to the semiconductor equipment of the present invention, in close proximity to the shield plate that is maintained at a predetermined potential covers the surface principal frequency of the semiconductor element on the semiconductor element is disposed, inside the envelope integrally By the formation, the mounting process can be simplified, the structure can be inexpensive and small, and a high shielding effect against electromagnetic disturbance signals can be obtained, and stable and favorable operation can be obtained.
【図１】この発明の第１の実施例の半導体装置の構造を
示す外観透視斜視図である。FIG. 1 is an external perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention.
【図２】同半導体装置の内部構造を示す側面断面図であ
る。FIG. 2 is a side sectional view showing an internal structure of the semiconductor device.
【図３】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 3 is a perspective view showing a configuration of an assembling step of the semiconductor device.
【図４】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 4 is a perspective view showing a configuration of an assembling step of the semiconductor device.
【図５】この発明の第２の実施例の半導体装置の構造を
示す外観透視斜視図である。FIG. 5 is an external perspective view showing the structure of a semiconductor device according to a second embodiment of the present invention.
【図６】同半導体装置の内部構造を示す側面断面図であ
る。FIG. 6 is a side sectional view showing the internal structure of the semiconductor device.
【図７】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 7 is a perspective view showing a configuration of an assembling step of the semiconductor device.
【図８】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 8 is a perspective view showing a configuration of an assembling step of the semiconductor device.
【図９】従来の半導体装置の構造を示す外観透視斜視図
である。FIG. 9 is an external perspective view showing the structure of a conventional semiconductor device.
【図１０】同半導体装置の内部構造を示す側面断面図で
ある。FIG. 10 is a side sectional view showing the internal structure of the semiconductor device.
１ 半導体素子 ２ 第１リードフレーム半導体素子搭載部 ３ 金属細線 ４ 外囲器 ５ 第１リードフレーム電極部 ８ 第１リードフレーム位置合わせ穴 １１ 第２リードフレーム遮蔽平板 １２ 第２リードフレーム遮蔽平板電極部 １４ 第２リードフレーム位置合わせ穴 ２１ 第１リードフレーム半導体素子搭載部 ２２ 第１リードフレーム電極部 ２６ａ・２６ｂ 第１リードフレーム位置合わせ穴 ３１ 第２リードフレーム遮蔽平板 ３２ 第２リードフレーム遮蔽平板電極部 ３７ａ・３７ｂ 第２リードフレーム位置合わせ穴 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 1st lead frame semiconductor element mounting part 3 Metal thin wire 4 Enclosure 5 1st lead frame electrode part 8 1st lead frame positioning hole 11 2nd lead frame shielding plate 12 Second lead frame shielding plate electrode part 14 second lead frame positioning hole 21 first lead frame semiconductor element mounting portion 22 first lead frame electrode portion 26a / 26b first lead frame positioning hole 31 second lead frame shielding plate 32 second lead frame shielding plate electrode portion 37a / 37b 2nd lead frame alignment hole
Claims (6)
と前記半導体素子の所定の電極体に電気的に接続される
電極部とを有するリードフレームと、前記半導体素子を
介して前記リードフレームに対向配置され前記半導体素
子の表面要域を所定距離離間して覆う遮蔽板とを設け、
前記半導体素子と前記リードフレームと前記遮蔽板とを
一体的に外囲器に封入した半導体装置。A lead frame having a semiconductor element, a mounting part of the semiconductor element, and an electrode part electrically connected to a predetermined electrode body of the semiconductor element; and the lead frame via the semiconductor element. A shielding plate that is disposed opposite to and covers a required area of the surface of the semiconductor element at a predetermined distance,
A semiconductor device in which the semiconductor element, the lead frame, and the shielding plate are integrally sealed in an envelope.
電気的に接続したことを特徴とする請求項１記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the shielding plate and a predetermined electrode body of the semiconductor element are electrically connected.
げた屈曲部を設け、前記屈曲部の端を外囲器の外に露出
させてリードフレームの所定の電極部に接続するための
前記遮蔽板の電極部としたことを特徴とする請求項１記
載の半導体装置。3. A shield for bending an end of the shield plate toward the lead frame side, exposing the end of the bent portion to the outside of the envelope, and connecting the end to a predetermined electrode portion of the lead frame. 2. The semiconductor device according to claim 1, wherein the electrode is a plate.
特徴とする請求項１，２または３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the envelope is formed by resin sealing.
導体素子を載置し、前記第１のリードフレームの電極部An electrode portion of the first lead frame on which a conductive element is mounted;
の一部と前記半導体素子の電極体とを金属細線で接続Is connected to the electrode body of the semiconductor element with a thin metal wire.
し、遮蔽板を有する第２のリードフレームと前記第１のAnd a second lead frame having a shielding plate and the first lead frame.
リードフレームとを位置合わせすることにより前記遮蔽Shielding by aligning with lead frame
板を前記半導体素子を介して前記素子載置部と対向させA plate is opposed to the element mounting portion via the semiconductor element.
て配置し、前記半導体素子、前記金属配線および前記遮And the semiconductor element, the metal wiring, and the shielding
蔽板を樹脂封止する半導体装置の製造方法。A method for manufacturing a semiconductor device in which a shielding plate is resin-sealed.
せ穴と第２のリードフレームに設けた位置合わせ穴を用Use the alignment holes provided on the second lead frame
いて、前記第１のリードフレームと前記第２のリードフThe first lead frame and the second lead frame.
レームとを位置合わせすることを特徴とする請求項５記6. The frame according to claim 5, wherein said frame is aligned with said frame.
載の半導体装置の製造方法。Manufacturing method of the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100078A JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100078A JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04329657A JPH04329657A (en) | 1992-11-18 |
| JP2970952B2 true JP2970952B2 (en) | 1999-11-02 |
Family
ID=14264413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3100078A Expired - Fee Related JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2970952B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06254633A (en) * | 1993-03-08 | 1994-09-13 | Uchinuki:Kk | Punching machine |
-
1991
- 1991-05-01 JP JP3100078A patent/JP2970952B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04329657A (en) | 1992-11-18 |
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