JP4159636B2 - Electronic component package and a method of manufacturing the same - Google Patents

Electronic component package and a method of manufacturing the same Download PDF

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JP4159636B2
JP4159636B2 JP32301697A JP32301697A JP4159636B2 JP 4159636 B2 JP4159636 B2 JP 4159636B2 JP 32301697 A JP32301697 A JP 32301697A JP 32301697 A JP32301697 A JP 32301697A JP 4159636 B2 JP4159636 B2 JP 4159636B2
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substrate
electronic component
surface
electrode pattern
plating layer
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JPH11163583A (en
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和真 深澤
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シチズン電子株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Abstract

PROBLEM TO BE SOLVED: To provide an electronic parts package for an EL driver enabling a shielding process to be performed as easily as possible to reduce number of man-hours needed to produce the package without using a pressed shielding cover. SOLUTION: An electrode pattern 16b for grounding which is electrically connected with a ground line is formed on the top surface of a substrate 12. A coil 14, an IC, and a capacitor 15 for an EL driver are mounted on the substrate 12, and these electronic parts are sealed with an epoxy resin. The surface of a sealed body 18 is coated with a nickel plating layer 20, and the nickel plating layer 20 is electrically connected with the electrode pattern 16b. The coating of the nickel plating layer 20 to the surface of a sealed body 18 enables the electronic parts to be shielded from electric field noise and magnetic field noise. This eliminates the need for pressing a shielding cover to simply shield electronic parts packages without increasing the number of man-hours needed to produce the packages.

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、コイルやICなどの電子部品を基板上に実装し、これをエポキシ樹脂によって封止した電子部品パッケージ及びその製造方法に関する。 The present invention is an electronic component such as a coil and an IC mounted on a substrate, which relates to an electronic component package and a manufacturing method thereof sealed with epoxy resin.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
一般に、基板上にコイルやICなどの電子部品を実装してパッケージ化した場合、コイルやICが外部からの磁場や電波に対して影響を受けるため、パッケージ全体をシールドする必要がある。 In general, when packaged by mounting electronic components such as a coil and IC on the substrate, the coil and IC are affected to the magnetic field and radio waves from the outside, it is necessary to shield the entire package. 従来、電子部品パッケージ全体をシールドしたものとしては、例えば図9に示したものが知られている。 Conventionally, the entire electronic component package as those shields are known that shown for example in FIG. この電子部品パッケージ1は、側面にグランド接続用端子2が形成された基板3の上にコイル及びICを含む電子部品(図示せず)を実装し、この電子部品をエポキシ樹脂等の封止体4で封止した後、封止体4の上から箱型のシールドカバー5をすっぽり被せることによって全体をシールドしたものである。 The electronic component package 1, and mounting an electronic component including a coil and an IC on a substrate 3 to the grounding terminal 2 to the side surface is formed (not shown), the sealing body of the electronic component such as an epoxy resin after sealing 4 is obtained by shielding the entire by covering comfortably the shield cover 5 of the box-type from the top of the sealing body 4. シールドカバー5を被せた時に、シールドカバー5の一隅に設けたグランド用突起部6が基板3のグランド接続用端子2と接触する。 When covered with the shield cover 5, the ground projections 6 provided on one corner of the shield cover 5 is in contact with the grounding terminal 2 of the substrate 3. そして、このグランド接続用端子2は、電子部品パッケージ1をマザーボードに表面実装したとき、マザーボードのグランドラインと導通する。 Then, the ground connecting terminal 2, when the surface-mounted electronic component package 1 on a mother board, conducting with the ground line of the motherboard. 従って、グランド用突起部6がグランド接続用端子2を介してマザーボードのグランドラインと導通し、結果的にシールドカバー5が接地されて電子部品は電界ノイズからシールドされることになる。 Therefore, conduction with the ground line of the motherboard ground protrusion 6 via the ground connecting terminals 2, resulting in the shield cover 5 is an electronic component is grounded will be shielded from the electric field noise. また、シールドカバー5は、ニッケル合金等の磁性材を箱型にプレス成形したものであるので、電子部品を外部の磁界ノイズからもシールドすることができる。 The shield cover 5, so is obtained by press-molding a magnetic material such as nickel alloy in a box shape, it is possible to shield also the electronic components from the outside of the magnetic field noise.
【0003】 [0003]
また、図10に示した電子部品パッケージ1は、箱型のシールドカバー5の下面にスプリング8を装着した例である。 The electronic component package 1 shown in FIG. 10 is an example of mounting the spring 8 on the lower surface of the box-shaped shield cover 5. シールドカバー5を封止体4に被せた時に、スプリング8を封止体4に設けた穴部7に挿入することで、スプリング8が基板3上面に形成した接地用電極パターン(図示せず)と接触し、シールドカバー5が接地されるものである。 When covered with the shield cover 5 in the sealing body 4, by inserting into the hole 7 provided with a spring 8 in the sealing body 4, the spring 8 (not shown) for grounding electrode pattern formed on the substrate 3 top in contact with one in which the shield cover 5 is grounded. 従って、この場合にもシールドカバー5によって、電子部品を磁界ノイズ及び電界ノイズからシールドすることができる。 Therefore, the shield cover 5 also in this case, it is possible to shield the electronic components from the magnetic field noise and electric field noise.
【0004】 [0004]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら、上記従来の電子部品パッケージ1にあっては、いずれの例でも電子部品等の実装工程とは別工程でシールドカバー5をプレス成形しなければならない他、封止体に被せる際の位置合わせなどコスト面、作業面で問題があった。 However, the above there conventional electronic component package 1, except that must shield cover 5 was press-molded in a separate process from the mounting process of electronic components in each of the examples, the alignment when placed over the sealing body cost, etc., there has been a problem in the work surface.
【0005】 [0005]
そこで、本発明は、上記従来のシールドカバーを用いることなく、シールド工程を出来るだけ簡易にして工数の掛からないようにした電子部品パッケージ及びその製造方法を提供することを目的とする。 The present invention aims at providing the without the use of a conventional shield cover, the electronic component package and a manufacturing method thereof so as not applied the steps in the simple as possible shielding process.
【0006】 [0006]
【課題を解決するための手段】 In order to solve the problems]
上記課題を解決するために本発明の電子部品パッケージは、コイル及びICを含む電子部品が実装された四角形状の基板と、 該基板の四隅に形成されるスルーホール電極と、前記基板上に前記電子部品を封止する封止体と、前記基板の上面に形成され、 前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンと、前記封止体の表面に形成され、前記接地用電極パターンの露出面に導通するニッケルメッキ層とを備えたことを特徴とする。 Electronic component package of the present invention in order to solve the above problems, a rectangular substrate on which electronic components are mounted, including a coil and IC, and the through-hole electrode formed at the four corners of the substrate, wherein the substrate a sealing member for sealing the electronic component, is formed on the upper surface of the substrate, extends toward the side surface of the substrate in contact from said any one of the through-hole electrodes to the through-hole electrodes, the side surface of the sealing body a ground electrode pattern having one end exposed, the formed on the surface of the sealing body, characterized in that a nickel plating layer electrically connected to the exposed surface of the ground electrode patterns.
【0010】 [0010]
本発明の電子部品パッケージの製造方法は、格子状のダイシングラインが設定され、このダイシングラインの各角部にスルーホールを有する集合基板を形成する集合基板形成工程と、隣接する前記スルーホールの間のダイシングラインを横断するようにして各スルーホールを繋ぐ接地用電極パターンを形成する接地用電極パターン形成工程と、前記ダイシングラインによって仕切られる各単一基板毎の上面にコイル及びICを含む電子部品をそれぞれ実装する実装工程と、前記電子部品を含む集合基板の上面全面にエポキシ樹脂を充填して封止する樹脂封止工程と、前記エポキシ樹脂の上から前記接地用電極パターン及び集合基板の一部までを前記ダイシングラインに沿ってダイシングするハーフダイシング工程と、前記エポキシ樹脂の全表 Method of manufacturing an electronic component package of the present invention, the lattice-like dicing line is set, and the aggregate substrate forming step of forming an aggregate substrate with a Suruho Le at each corner of the dicing line, between the Suruho Le adjacent electronic components comprising a ground electrode pattern forming step, a coil and an IC on the top surface of each single substrate partitioned by the dicing lines forming a grounding electrode pattern connecting each Suruho Le so as to cross the dicing lines a mounting step of mounting each of the resin sealing step of sealing by filling the entire upper surface to the epoxy resin of the collective substrate including an electronic component, one electrode pattern and collective substrate said ground over the epoxy resin a half-dicing step of dicing along the up parts on the dicing line, a full table of the epoxy resin 及びハーフダイシングしたエポキシ樹脂の溝周面、さらに溝周面に露出した接地用電極パターンの端部にニッケルメッキ層を形成すると同時に、該端部とニッケルメッキ層とを導通させるメッキコーティング工程と、前記ニッケルメッキ層の形成によって電子部品がシールドされた前記集合基板を各単一基板毎にフルダイシングして一つ一つに分割する分割工程とを備え、分割された前記基板の四隅にスルーホール電極を形成し、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンを形成することを特徴とする。 And the half groove peripheral surface of the dicing epoxy resin, further forming a nickel plating layer on the end portion of the ground electrode pattern exposed in the groove circumferential surface at the same time, the plating coating step of electrically connecting the end portion and the nickel plating layer, and a dividing step for dividing the aggregate board on which electronic components are shielded by the formation of the nickel plating layer on one by one in a full diced for each single substrate, divided through holes at the four corners of the substrate that the electrode is formed, extending toward the side surface of the substrate in contact from said any one of the through-hole electrodes to the through-hole electrodes, to form a grounding electrode pattern having one end exposed on a side surface of the sealing body and features.
【0011】 [0011]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、添付図面に基づいて本発明に係る電子部品パッケージ及びその製造方法について詳細に説明する。 Hereinafter, an electronic component package and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings. 図1及び図2は、本発明に係る電子部品パッケージ11をELドライバモジュールとして構成した時の一実施例を示したものである。 1 and 2, in which the electronic component package 11 of the present invention illustrating one embodiment when configured as an EL driver module. この実施例において、電子部品パッケージ11は、矩形状の基板12の上面にELドライバ用のIC13、コイル14及びコンデンサ15を実装したものである。 In this embodiment, the electronic component package 11, IC 13 for EL driver on an upper surface of a rectangular substrate 12, is an implementation of the coil 14 and a capacitor 15. これらの電子部品は、図2に示したように、電極パターン16a上にダイボンドやワイヤボンドなどの手段により接続されたり、リフローで半田付けされる。 These electronic components, as shown in FIG. 2, or are connected by means such as die bonding and wire bonding on the electrode pattern 16a, are soldered by reflow. 基板12は、ガラスエポキシ樹脂等の絶縁材からなり、その側面の四隅には基板12の下面に連なるスルーホール電極17a,17b,17c,17dが形成されると共に、その内の一つのスルーホール電極17aがグランド接続用端子として構成されている。 Substrate 12 is made of an insulating material such as glass epoxy resin, the through-hole electrodes 17a continuous with the lower surface of the substrate 12 at four corners of its aspects, 17b, 17c, together with 17d are formed, one through-hole electrode of which 17a is configured as a ground connection terminal. このグランド接続用端子17aは、電子部品用パッケージ11がマザーボード(図示せず)に実装された時に、マザーボードのグランドラインと導通するものである。 The ground connecting terminals 17a are those electronic component package 11 when it is mounted on a motherboard (not shown), conducts a ground line of the motherboard. また、上記基板12の上面には、前述の電極パターン16aの他に、グランド接続用端子17aと導通する接地用電極パターン16bが形成されている。 Further, the top surface of the substrate 12, in addition to the above-mentioned electrode patterns 16a, grounding electrode pattern 16b for conduction with ground connecting terminals 17a are formed.
【0012】 [0012]
上述のようにして、IC13、コイル14及びコンデンサ15が実装された基板12の上面は、エポキシ樹脂からなる封止体18によって封止される。 As described above, IC 13, the upper surface of the coil 14 and the substrate 12 the capacitor 15 is mounted is sealed by a sealing body 18 made of epoxy resin. この封止体18は、基板12の平面形状と略同一形状であり、両者が一体となって樹脂封止パッケージを構成する。 The sealing body 18 is a plan shape substantially the same shape of the substrate 12, both constituting the resin sealing package together. 封止体18に用いられるエポキシ樹脂は、耐湿性、耐候性、絶縁性及び耐熱性等に優れると共に、前述のガラスエポキシ板とは異なる成分構成からなり、封止体18の表面にメッキが実用的強度で形成されるのを可能としている。 Epoxy resin used in the sealing body 18, moisture resistance, weather resistance, excellent in insulating properties and heat resistance and the like, made of different components constituting the glass-epoxy plate above, plating practical to the surface of the sealing body 18 thereby enabling from being formed in strength. なお、この実施例では、図1及び図2に示したように、接地用電極パターン16bの一端部19を、封止体18から外部に露出させてある。 In this embodiment, as shown in FIGS. 1 and 2, one end portion 19 of the ground electrode pattern 16b, are exposed from the sealing body 18 to the outside.
【0013】 [0013]
前記封止体18の全表面にはニッケルメッキ層20が形成されている。 Nickel plating layer 20 is formed on the entire surface of the sealing body 18. このニッケルメッキ層20は、無電解メッキ法によってエポキシ樹脂の上に付着形成される。 The nickel plating layer 20 is deposited over the epoxy resin by an electroless plating method. また、ニッケルメッキ層20は、封止体18の周面にも形成されることから、封止体18から露出している接地用電極パターン16bの一端部19にも付着形成されることになる。 Further, nickel plated layer 20, since it is also formed on the peripheral surface of the sealing body 18, will be deposited in one end portion 19 of the ground electrode patterns 16b exposed from the encapsulant 18 . その結果、ニッケルメッキ層20は、接地用電極パターン16b及びグランド接続用端子17aと導通し、マザーボードのグランドラインに接地されることになるため、外部の電界ノイズから電子部品をシールドすることができる。 As a result, the nickel plating layer 20 is conducted to the grounding electrode pattern 16b and the grounding terminals 17a, because that will be grounded to the ground line of the motherboard, it can be shielded electronic components from the outside of the field noise . さらに、ニッケルメッキ層20の厚さを自由に設定することができ、例えば、従来のシールドカバーと同程度の厚さで形成した場合にシールド効果を得ることができ、外部からの磁界ノイズはニッケルメッキ層20によって吸収され、コイル14を磁界ノイズからシールドすることができる。 Furthermore, it is possible to freely set the thickness of the nickel plating layer 20, for example, be when a thickness comparable to the conventional shield cover obtain a shielding effect, magnetic field noise from the outside of nickel is absorbed by the plating layer 20, it is possible to shield the coil 14 from the magnetic field noise.
【0014】 [0014]
このように、エポキシ樹脂からなる封止体18の表面にニッケルメッキ層20をコーティングするだけで、電子部品を電界ノイズ及び磁界ノイズからシールドすることができるため、従来のようにシールドカバーをプレス成形する必要がなく、作業工数を掛けることなく簡単に電子部品パッケージをシールドすることができる。 Thus, by simply coating a nickel plated layer 20 on the surface of the sealing body 18 made of epoxy resin, since the electronic component can be shielded from the electric field noise and magnetic noise, the shield cover press-forming as in the prior art there is no need to, it is possible to shield easily the electronic component package without applying the number of working steps. また、ニッケルメッキ層20のメッキ厚も簡単に変更できるため、必要とするシールド特性に応じてメッキ厚を変更することが可能である。 Further, since the plating thickness of the nickel plating layer 20 can be easily changed, it is possible to change the plating thickness according to the shield characteristics required.
【0015】 [0015]
図3乃至図8は、上記構成からなる電子部品パッケージの一製造方法を示したものである。 3 to 8, there is shown a manufacturing method of an electronic component package having the above structure. この製造工程では、先ず図3に示すように、各単一基板12毎にダイシングライン21が想定される集合基板22にグランド接続用端子17aとなるスルーホール電極を設けると共に、集合基板22の上面にはグランド接続用端子17aをつなぐ接地用電極パターン16bを連続的に形成する。 In this manufacturing process, first, as shown in FIG. 3, provided with a through-hole electrode serving as a ground connection terminal 17a to the aggregate substrate 22 the dicing line 21 is assumed to each single substrate 12 each, the upper surface of the assembly substrate 22 continuously forming a grounding electrode pattern 16b for connecting the ground connecting terminals 17a to. この時、グランド接続用端子17a以外のスルーホール電極及び電子部品用の電極パターン(図示せず)も同時に形成する。 At this time, the electrode pattern (not shown) for through-hole electrodes and electronic components other than the ground connecting terminals 17a are also formed at the same time.
【0016】 [0016]
次の工程では、図4に示すように、基板12毎にIC13、コイル14及びコンデンサ15を所定位置に載置し、ダイボンド及びワイヤボンド、リフロなどの手段で基板12上に実装する。 In the next step, as shown in FIG. 4, IC 13 for each substrate 12, a coil 14 and a capacitor 15 is placed in position, the die bonding and wire bonding, is mounted on the substrate 12 by means such as reflow. 次いで、図5に示すように、集合基板22の上面全体にエポキシ樹脂を充填し、基板12の上に均一な厚さの封止体18を形成して電子部品を樹脂封止する。 Then, as shown in FIG. 5, the epoxy resin was filled into the entire upper surface of the aggregate substrate 22, the electronic component is sealed with resin to form a sealing body 18 of uniform thickness on the substrate 12. なお、集合基板22の外周に型枠を設けたり、スルーホールに樹脂が流れ込まないように、マスク材として薄いテープを貼るなどの方法を用いて樹脂封止するが、これらの加工方法は製造の実情に合わせて実施すればよい。 Incidentally, or provided mold the outer periphery of the assembly substrate 22, so as not resin from flowing into the through-hole, although the resin sealing by a method such as sticking a thin tape as a mask material, these processing methods producing it may be performed in accordance with the actual situation.
【0017】 [0017]
次の工程では、図6及び図7に示すように、ダイシングライン21に沿って封止体18の上から格子状に切込み23を入れ、集合基板22の略下半部を残した状態でハーフダイシングを行なう。 In the next step, as shown in FIGS. 6 and 7, put a grid to cut 23 from the top of the sealing body 18 along the dicing line 21, a half, leaving a substantially lower half of the assembly substrate 22 diced. このハーフダイシングによって封止体18は各単一基板12毎に溝周面が露出すると共に、集合基板22の略上半部にも切込み23が入るために、接地用電極パターン16bの一端部19も封止体18から露出することになる。 With sealing body 18 groove circumference in each single substrate 12 each are exposed by the half-dicing, for even cuts 23 into the substantially upper half of the assembly substrate 22, one end 19 of the ground electrode pattern 16b It will also be exposed from the sealing body 18. そして、図8に示した次の工程で、封止体18の外表面に無電解メッキ法によってニッケルメッキ層20を形成する。 In the next step shown in FIG. 8, to form a nickel plating layer 20 by electroless plating on the outer surface of the sealing body 18. この時、ハーフダイシングした封止体18の切込み23にもメッキが回り込んで、各単一基板12毎に封止体18の周囲にニッケルメッキ層20が形成されるために、ニッケルメッキ層20が接地用電極パターン16bの露出している一端部19にも付着し、スルーホールからなるグランド接続用端子17aまでが導通し接地される。 At this time, in also wraps around the plated notch 23 of the sealing body 18 that is half-dicing, for the nickel plating layer 20 is formed around the sealing body 18 in the single substrate 12 each, nickel plated layer 20 There is also attached to one end portion 19 which is exposed in the ground electrode patterns 16b, to the ground connection terminal 17a consisting of the through hole is made conductive to ground. 従って、ニッケルメッキ層20がシールド作用を発揮し、電子部品を電界ノイズや磁界ノイズからシールドすることができる。 Therefore, it is possible to nickel plating layer 20 exhibits a shield effect, shielding the electronic components from the field noise and magnetic noise.
【0018】 [0018]
このように、集合基板22の全面にエポキシ樹脂を充填し、ハーフダイシングすることにより封止体18の各単一基板12毎の溝周面を露出させ、一度に多数同時にニッケルメッキ層20を形成することができる。 Thus, the epoxy resin was filled into the entire surface of the collective substrate 22 to expose the groove peripheral surface of each single substrate 12 for each of the sealing body 18 by half-dicing, form multiple simultaneous nickel plating layer 20 at a time can do. そして、最後に集合基板22に想定されたダイシングライン21に沿って再びダイシングし、各単一基板12毎に完全に切り離して一つ一つの電子部品パッケージ11に分割する。 Finally, diced again along the dicing line 21 which is assumed to aggregate substrate 22 is divided into each one of the electronic component package 11 completely disconnected to each single substrate 12 each. 分割された電子部品パッケージ11は、完成品として図示外のマザーボード上に実装される。 Electronic component package 11 which split is mounted on an unillustrated motherboard as a finished product.
【0019】 [0019]
上述のように、ハーフダイシング工程を用いたことで接地用電極パターン16bの端部を露出させることができ、この露出部分にメッキを行なうことで接地用電極パターン16bを導通させることができる。 As described above, it is possible to expose the end portion of the ground electrode pattern 16b by using the half-dicing step, it is possible to conduct the grounding electrode pattern 16b by performing plating on the exposed portion. また、電子部品パッケージ11は、封止体18の外表面及び接地用電極パターン16bの一端部19にニッケルメッキ層20を被覆形成することでシールドされるため、一貫した生産ラインで簡単にシールド付き電子部品パッケージ11の製造が可能になる。 The electronic component package 11, because it is shielded by coating forming a nickel plating layer 20 at one end 19 of the outer surface and the ground electrode pattern 16b of the sealing body 18, easily shielded with integrated production line it is possible to manufacture an electronic component package 11.
【0020】 [0020]
なお、上記実施例では基板12上にIC13、コイル14及びコンデンサ15を実装したELドライバについて説明したが、本発明はこれに限定されることなく、種々の電子部品パッケージに適用できるものである。 Incidentally, IC 13 on the substrate 12 in the above embodiment has been described EL driver that implements the coil 14 and the capacitor 15, but the present invention is not limited thereto, but applicable to various electronic component package. また、基板12の上面に形成した接地用電極パターン16bの形状および一端部19の露出個所などは上記実施例に限定されないことは勿論である。 Moreover, the such exposure point of the shape and the one end portion 19 of the ground electrode pattern 16b formed on the upper surface of the substrate 12 is not limited to the above embodiments is a matter of course.
【0021】 [0021]
【発明の効果】 【Effect of the invention】
以上説明したように、本発明に係る電子部品パッケージによれば、電子部品の封止体としてエポキシ樹脂を用い、無電解メッキによってその表面にシールド効果が備わったニッケルメッキ層を簡単に形成することができるため、従来のような工数の掛かるプレス加工による金属カバーの成形に比べて製造コストを大幅に下げることができた。 As described above, according to the electronic component package according to the present invention, that an epoxy resin as a sealing material of an electronic component, to easily form a nickel plating layer shielding effect is provided on the surface thereof by electroless plating because it was able to reduce the manufacturing costs considerably compared to the molding of the metal cover by pressing consuming conventional steps like.
【0022】 [0022]
また、グランドラインと導通する接地用の電極パターンを基板の上面に形成し、この接地用の電極パターンの一端にニッケルメッキ層を形成して導通させたので、ニッケルメッキ層の接地を容易且つ確実に行なうことができた。 Further, an electrode pattern for grounding which conducts with the ground line formed on the upper surface of the substrate, because this was the one end of the electrode pattern for grounding is rendered conductive by forming a nickel plating layer, easy and reliable grounding of the nickel plating layer it was able to do to.
【0023】 [0023]
また、本発明に係る電子部品パッケージの製造方法によれば、エポキシ樹脂からなる封止体の表面にニッケルメッキ層を形成することでシールドできるために、従来のような工数の掛かる金属カバーのプレス加工が不要となり、一貫した生産ラインで電子部品パッケージを製造することができる。 Further, according to the method for producing an electronic component package according to the present invention, in order to be shielded by forming a nickel plating layer on the surface of the sealing body made of an epoxy resin, a metal cover consuming conventional steps such as the press processing becomes unnecessary, it is possible to manufacture the electronic component package in a consistent production line.
【0024】 [0024]
さらに、本発明に係る電子部品パッケージの製造方法によれば、エポキシ樹脂からなる封止体の表面にニッケルメッキ層を形成することでシールドできるために、集合基板を用いた製造が可能となり、一度に多数の電子部品パッケージを製造することで、コストの大幅低下を達成することができた。 Further, according to the method for producing an electronic component package according to the present invention, in order to be shielded by forming a nickel plating layer on the surface of the sealing body made of epoxy resin, it is possible to manufacture using collective board, once a number of electronic component package was to prepare, it was possible to achieve a significant reduction in cost.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明に係る電子部品パッケージの一実施例を示す斜視図である。 Is a perspective view showing an embodiment of an electronic component package according to the present invention; FIG.
【図2】上記図1のA−A線断面図である。 2 is a sectional view along line A-A of FIG 1.
【図3】上記実施例に係る電子部品パッケージの接地用電極パターンの形成工程図である。 3 is a forming process drawing of the ground electrode pattern of the electronic component package according to the embodiment.
【図4】上記実施例に係る電子部品パッケージの電子部品の実装工程図である。 4 is a mounting process diagrams of an electronic component of an electronic component package according to the embodiment.
【図5】上記実施例に係る電子部品パッケージの樹脂封止工程図である。 5 is a resin sealing step view of the electronic component package according to the embodiment.
【図6】上記実施例に係る電子部品パッケージのハーフダイシング工程図である。 6 is a half-dicing process diagram of an electronic component package according to the embodiment.
【図7】上記図6のB−B線断面図である。 7 is a sectional view taken along line B-B of FIG 6.
【図8】上記実施例に係る電子部品パッケージのメッキコーティング工程図である。 8 is a plated coating process diagram of an electronic component package according to the embodiment.
【図9】従来の電子部品パッケージの一例を示す斜視図である。 9 is a perspective view showing an example of a conventional electronic component package.
【図10】従来の電子部品パッケージの他の例を示す斜視図である。 10 is a perspective view showing another example of a conventional electronic component package.
【符号の説明】 DESCRIPTION OF SYMBOLS
11 電子部品パッケージ12 基板13 IC 11 electronic component package 12 substrate 13 IC
14 コイル16b 接地用電極パターン18 封止体20 ニッケルメッキ層21 ダイシングライン22 集合基板 14 coil 16b grounding electrode pattern 18 sealing body 20 the nickel plating layer 21 dicing lines 22 aggregate substrate

Claims (2)

  1. コイル及びICを含む電子部品が実装された四角形状の基板と、 A rectangular substrate on which electronic components are mounted, including a coil and IC,
    該基板の四隅に形成されるスルーホール電極と、 And a through hole electrode formed at the four corners of the substrate,
    前記基板上に前記電子部品を封止する封止体と、 A sealing member for sealing the electronic component on the substrate,
    前記基板の上面に形成され、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンと、 Is formed on the upper surface of the substrate, extends toward the side surface of the substrate in contact from said any one of the through-hole electrodes to the through hole electrode, and the grounding electrode pattern having one end exposed on a side surface of the sealing body,
    前記封止体の表面に形成され、前記接地用電極パターンの露出面に導通するニッケルメッキ層とを備えたことを特徴とする電子部品パッケージ。 Wherein formed on the surface of the sealing body, an electronic component package, characterized in that a nickel plating layer electrically connected to the exposed surface of the ground electrode patterns.
  2. 格子状のダイシングラインが設定され、このダイシングラインの各角部にスルーホールを有する集合基板を形成する集合基板形成工程と、 Is set lattice dicing lines, and the collective substrate forming step of forming an aggregate substrate with a Suruho Le at each corner of the dicing line,
    隣接する前記スルーホールの間のダイシングラインを横断するようにして各スルーホールを繋ぐ接地用電極パターンを形成する接地用電極パターン形成工程と、 A grounding electrode pattern forming step of forming a grounding electrode pattern so as to cross the dicing line between adjacent said Suruho Le connecting each Suruho Le,
    前記ダイシングラインによって仕切られる各単一基板毎の上面にコイル及びICを含む電子部品をそれぞれ実装する実装工程と、 A mounting step of each mounting an electronic component including a coil and an IC on the top surface of each single substrate partitioned by the dicing lines,
    前記電子部品を含む集合基板の上面全面にエポキシ樹脂を充填して封止する樹脂封止工程と、 A resin sealing step of sealing by filling the epoxy resin on the entire upper surface of the collective substrate including the electronic component,
    前記エポキシ樹脂の上から前記接地用電極パターン及び集合基板の一部までを前記ダイシングラインに沿ってダイシングするハーフダイシング工程と、 A half-dicing step of dicing the over of the epoxy resin to a part of the grounding electrode pattern and aggregate substrate along the dicing line,
    前記エポキシ樹脂の全表面及びハーフダイシングしたエポキシ樹脂の溝周面、さらに溝周面に露出した接地用電極パターンの端部にニッケルメッキ層を形成すると同時に、該端部とニッケルメッキ層とを導通させるメッキコーティング工程と、 At the same time the entire surface and a groove peripheral surface of the half-dicing the epoxy resin of the epoxy resin, further forming a nickel plating layer on the end portion of the ground electrode pattern exposed in the groove circumferential surface, conduction between said end portion and a nickel plating layer and the plating coating step of,
    前記ニッケルメッキ層の形成によって電子部品がシールドされた前記集合基板を各単一基板毎にフルダイシングして一つ一つに分割する分割工程とを備え And a dividing step for dividing the aggregate board on which electronic components are shielded by the formation of the nickel plating layer on one by one in a full diced for each single substrate,
    分割された前記基板の四隅にスルーホール電極を形成し、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンを形成することを特徴とする電子部品パッケージの製造方法。 The through-hole electrodes are formed at four corners of the divided said substrate, extends toward the side surface of the substrate in contact from said any one of the through-hole electrodes to the through hole electrode, one end exposed on a side surface of the sealing body method for producing an electronic component package and forming a grounding electrode pattern.
JP32301697A 1997-11-25 1997-11-25 Electronic component package and a method of manufacturing the same Expired - Fee Related JP4159636B2 (en)

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