JP4159636B2 - Electronic component package and manufacturing method thereof - Google Patents

Electronic component package and manufacturing method thereof Download PDF

Info

Publication number
JP4159636B2
JP4159636B2 JP32301697A JP32301697A JP4159636B2 JP 4159636 B2 JP4159636 B2 JP 4159636B2 JP 32301697 A JP32301697 A JP 32301697A JP 32301697 A JP32301697 A JP 32301697A JP 4159636 B2 JP4159636 B2 JP 4159636B2
Authority
JP
Japan
Prior art keywords
substrate
electrode pattern
electronic component
plating layer
nickel plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32301697A
Other languages
Japanese (ja)
Other versions
JPH11163583A (en
Inventor
和真 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Electronics Co Ltd
Original Assignee
Citizen Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Electronics Co Ltd filed Critical Citizen Electronics Co Ltd
Priority to JP32301697A priority Critical patent/JP4159636B2/en
Publication of JPH11163583A publication Critical patent/JPH11163583A/en
Application granted granted Critical
Publication of JP4159636B2 publication Critical patent/JP4159636B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Abstract

PROBLEM TO BE SOLVED: To provide an electronic parts package for an EL driver enabling a shielding process to be performed as easily as possible to reduce number of man-hours needed to produce the package without using a pressed shielding cover. SOLUTION: An electrode pattern 16b for grounding which is electrically connected with a ground line is formed on the top surface of a substrate 12. A coil 14, an IC, and a capacitor 15 for an EL driver are mounted on the substrate 12, and these electronic parts are sealed with an epoxy resin. The surface of a sealed body 18 is coated with a nickel plating layer 20, and the nickel plating layer 20 is electrically connected with the electrode pattern 16b. The coating of the nickel plating layer 20 to the surface of a sealed body 18 enables the electronic parts to be shielded from electric field noise and magnetic field noise. This eliminates the need for pressing a shielding cover to simply shield electronic parts packages without increasing the number of man-hours needed to produce the packages.

Description

【０００１】
【発明の属する技術分野】
本発明は、コイルやＩＣなどの電子部品を基板上に実装し、これをエポキシ樹脂によって封止した電子部品パッケージ及びその製造方法に関する。
【０００２】
【従来の技術】
一般に、基板上にコイルやＩＣなどの電子部品を実装してパッケージ化した場合、コイルやＩＣが外部からの磁場や電波に対して影響を受けるため、パッケージ全体をシールドする必要がある。従来、電子部品パッケージ全体をシールドしたものとしては、例えば図９に示したものが知られている。この電子部品パッケージ１は、側面にグランド接続用端子２が形成された基板３の上にコイル及びＩＣを含む電子部品（図示せず）を実装し、この電子部品をエポキシ樹脂等の封止体４で封止した後、封止体４の上から箱型のシールドカバー５をすっぽり被せることによって全体をシールドしたものである。シールドカバー５を被せた時に、シールドカバー５の一隅に設けたグランド用突起部６が基板３のグランド接続用端子２と接触する。そして、このグランド接続用端子２は、電子部品パッケージ１をマザーボードに表面実装したとき、マザーボードのグランドラインと導通する。従って、グランド用突起部６がグランド接続用端子２を介してマザーボードのグランドラインと導通し、結果的にシールドカバー５が接地されて電子部品は電界ノイズからシールドされることになる。また、シールドカバー５は、ニッケル合金等の磁性材を箱型にプレス成形したものであるので、電子部品を外部の磁界ノイズからもシールドすることができる。
【０００３】
また、図１０に示した電子部品パッケージ１は、箱型のシールドカバー５の下面にスプリング８を装着した例である。シールドカバー５を封止体４に被せた時に、スプリング８を封止体４に設けた穴部７に挿入することで、スプリング８が基板３上面に形成した接地用電極パターン（図示せず）と接触し、シールドカバー５が接地されるものである。従って、この場合にもシールドカバー５によって、電子部品を磁界ノイズ及び電界ノイズからシールドすることができる。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記従来の電子部品パッケージ１にあっては、いずれの例でも電子部品等の実装工程とは別工程でシールドカバー５をプレス成形しなければならない他、封止体に被せる際の位置合わせなどコスト面、作業面で問題があった。
【０００５】
そこで、本発明は、上記従来のシールドカバーを用いることなく、シールド工程を出来るだけ簡易にして工数の掛からないようにした電子部品パッケージ及びその製造方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
上記課題を解決するために本発明の電子部品パッケージは、コイル及びＩＣを含む電子部品が実装された四角形状の基板と、該基板の四隅に形成されるスルーホール電極と、前記基板上に前記電子部品を封止する封止体と、前記基板の上面に形成され、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンと、前記封止体の表面に形成され、前記接地用電極パターンの露出面に導通するニッケルメッキ層とを備えたことを特徴とする。
【００１０】
本発明の電子部品パッケージの製造方法は、格子状のダイシングラインが設定され、このダイシングラインの各角部にスルーホールを有する集合基板を形成する集合基板形成工程と、隣接する前記スルーホールの間のダイシングラインを横断するようにして各スルーホールを繋ぐ接地用電極パターンを形成する接地用電極パターン形成工程と、前記ダイシングラインによって仕切られる各単一基板毎の上面にコイル及びＩＣを含む電子部品をそれぞれ実装する実装工程と、前記電子部品を含む集合基板の上面全面にエポキシ樹脂を充填して封止する樹脂封止工程と、前記エポキシ樹脂の上から前記接地用電極パターン及び集合基板の一部までを前記ダイシングラインに沿ってダイシングするハーフダイシング工程と、前記エポキシ樹脂の全表面及びハーフダイシングしたエポキシ樹脂の溝周面、さらに溝周面に露出した接地用電極パターンの端部にニッケルメッキ層を形成すると同時に、該端部とニッケルメッキ層とを導通させるメッキコーティング工程と、前記ニッケルメッキ層の形成によって電子部品がシールドされた前記集合基板を各単一基板毎にフルダイシングして一つ一つに分割する分割工程とを備え、分割された前記基板の四隅にスルーホール電極を形成し、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンを形成することを特徴とする。
【００１１】
【発明の実施の形態】
以下、添付図面に基づいて本発明に係る電子部品パッケージ及びその製造方法について詳細に説明する。図１及び図２は、本発明に係る電子部品パッケージ１１をＥＬドライバモジュールとして構成した時の一実施例を示したものである。この実施例において、電子部品パッケージ１１は、矩形状の基板１２の上面にＥＬドライバ用のＩＣ１３、コイル１４及びコンデンサ１５を実装したものである。これらの電子部品は、図２に示したように、電極パターン１６ａ上にダイボンドやワイヤボンドなどの手段により接続されたり、リフローで半田付けされる。基板１２は、ガラスエポキシ樹脂等の絶縁材からなり、その側面の四隅には基板１２の下面に連なるスルーホール電極１７ａ，１７ｂ，１７ｃ，１７ｄが形成されると共に、その内の一つのスルーホール電極１７ａがグランド接続用端子として構成されている。このグランド接続用端子１７ａは、電子部品用パッケージ１１がマザーボード（図示せず）に実装された時に、マザーボードのグランドラインと導通するものである。また、上記基板１２の上面には、前述の電極パターン１６ａの他に、グランド接続用端子１７ａと導通する接地用電極パターン１６ｂが形成されている。
【００１２】
上述のようにして、ＩＣ１３、コイル１４及びコンデンサ１５が実装された基板１２の上面は、エポキシ樹脂からなる封止体１８によって封止される。この封止体１８は、基板１２の平面形状と略同一形状であり、両者が一体となって樹脂封止パッケージを構成する。封止体１８に用いられるエポキシ樹脂は、耐湿性、耐候性、絶縁性及び耐熱性等に優れると共に、前述のガラスエポキシ板とは異なる成分構成からなり、封止体１８の表面にメッキが実用的強度で形成されるのを可能としている。なお、この実施例では、図１及び図２に示したように、接地用電極パターン１６ｂの一端部１９を、封止体１８から外部に露出させてある。
【００１３】
前記封止体１８の全表面にはニッケルメッキ層２０が形成されている。このニッケルメッキ層２０は、無電解メッキ法によってエポキシ樹脂の上に付着形成される。また、ニッケルメッキ層２０は、封止体１８の周面にも形成されることから、封止体１８から露出している接地用電極パターン１６ｂの一端部１９にも付着形成されることになる。その結果、ニッケルメッキ層２０は、接地用電極パターン１６ｂ及びグランド接続用端子１７ａと導通し、マザーボードのグランドラインに接地されることになるため、外部の電界ノイズから電子部品をシールドすることができる。さらに、ニッケルメッキ層２０の厚さを自由に設定することができ、例えば、従来のシールドカバーと同程度の厚さで形成した場合にシールド効果を得ることができ、外部からの磁界ノイズはニッケルメッキ層２０によって吸収され、コイル１４を磁界ノイズからシールドすることができる。
【００１４】
このように、エポキシ樹脂からなる封止体１８の表面にニッケルメッキ層２０をコーティングするだけで、電子部品を電界ノイズ及び磁界ノイズからシールドすることができるため、従来のようにシールドカバーをプレス成形する必要がなく、作業工数を掛けることなく簡単に電子部品パッケージをシールドすることができる。また、ニッケルメッキ層２０のメッキ厚も簡単に変更できるため、必要とするシールド特性に応じてメッキ厚を変更することが可能である。
【００１５】
図３乃至図８は、上記構成からなる電子部品パッケージの一製造方法を示したものである。この製造工程では、先ず図３に示すように、各単一基板１２毎にダイシングライン２１が想定される集合基板２２にグランド接続用端子１７ａとなるスルーホール電極を設けると共に、集合基板２２の上面にはグランド接続用端子１７ａをつなぐ接地用電極パターン１６ｂを連続的に形成する。この時、グランド接続用端子１７ａ以外のスルーホール電極及び電子部品用の電極パターン（図示せず）も同時に形成する。
【００１６】
次の工程では、図４に示すように、基板１２毎にＩＣ１３、コイル１４及びコンデンサ１５を所定位置に載置し、ダイボンド及びワイヤボンド、リフロなどの手段で基板１２上に実装する。次いで、図５に示すように、集合基板２２の上面全体にエポキシ樹脂を充填し、基板１２の上に均一な厚さの封止体１８を形成して電子部品を樹脂封止する。なお、集合基板２２の外周に型枠を設けたり、スルーホールに樹脂が流れ込まないように、マスク材として薄いテープを貼るなどの方法を用いて樹脂封止するが、これらの加工方法は製造の実情に合わせて実施すればよい。
【００１７】
次の工程では、図６及び図７に示すように、ダイシングライン２１に沿って封止体１８の上から格子状に切込み２３を入れ、集合基板２２の略下半部を残した状態でハーフダイシングを行なう。このハーフダイシングによって封止体１８は各単一基板１２毎に溝周面が露出すると共に、集合基板２２の略上半部にも切込み２３が入るために、接地用電極パターン１６ｂの一端部１９も封止体１８から露出することになる。そして、図８に示した次の工程で、封止体１８の外表面に無電解メッキ法によってニッケルメッキ層２０を形成する。この時、ハーフダイシングした封止体１８の切込み２３にもメッキが回り込んで、各単一基板１２毎に封止体１８の周囲にニッケルメッキ層２０が形成されるために、ニッケルメッキ層２０が接地用電極パターン１６ｂの露出している一端部１９にも付着し、スルーホールからなるグランド接続用端子１７ａまでが導通し接地される。従って、ニッケルメッキ層２０がシールド作用を発揮し、電子部品を電界ノイズや磁界ノイズからシールドすることができる。
【００１８】
このように、集合基板２２の全面にエポキシ樹脂を充填し、ハーフダイシングすることにより封止体１８の各単一基板１２毎の溝周面を露出させ、一度に多数同時にニッケルメッキ層２０を形成することができる。そして、最後に集合基板２２に想定されたダイシングライン２１に沿って再びダイシングし、各単一基板１２毎に完全に切り離して一つ一つの電子部品パッケージ１１に分割する。分割された電子部品パッケージ１１は、完成品として図示外のマザーボード上に実装される。
【００１９】
上述のように、ハーフダイシング工程を用いたことで接地用電極パターン１６ｂの端部を露出させることができ、この露出部分にメッキを行なうことで接地用電極パターン１６ｂを導通させることができる。また、電子部品パッケージ１１は、封止体１８の外表面及び接地用電極パターン１６ｂの一端部１９にニッケルメッキ層２０を被覆形成することでシールドされるため、一貫した生産ラインで簡単にシールド付き電子部品パッケージ１１の製造が可能になる。
【００２０】
なお、上記実施例では基板１２上にＩＣ１３、コイル１４及びコンデンサ１５を実装したＥＬドライバについて説明したが、本発明はこれに限定されることなく、種々の電子部品パッケージに適用できるものである。また、基板１２の上面に形成した接地用電極パターン１６ｂの形状および一端部１９の露出個所などは上記実施例に限定されないことは勿論である。
【００２１】
【発明の効果】
以上説明したように、本発明に係る電子部品パッケージによれば、電子部品の封止体としてエポキシ樹脂を用い、無電解メッキによってその表面にシールド効果が備わったニッケルメッキ層を簡単に形成することができるため、従来のような工数の掛かるプレス加工による金属カバーの成形に比べて製造コストを大幅に下げることができた。
【００２２】
また、グランドラインと導通する接地用の電極パターンを基板の上面に形成し、この接地用の電極パターンの一端にニッケルメッキ層を形成して導通させたので、ニッケルメッキ層の接地を容易且つ確実に行なうことができた。
【００２３】
また、本発明に係る電子部品パッケージの製造方法によれば、エポキシ樹脂からなる封止体の表面にニッケルメッキ層を形成することでシールドできるために、従来のような工数の掛かる金属カバーのプレス加工が不要となり、一貫した生産ラインで電子部品パッケージを製造することができる。
【００２４】
さらに、本発明に係る電子部品パッケージの製造方法によれば、エポキシ樹脂からなる封止体の表面にニッケルメッキ層を形成することでシールドできるために、集合基板を用いた製造が可能となり、一度に多数の電子部品パッケージを製造することで、コストの大幅低下を達成することができた。
【図面の簡単な説明】
【図１】本発明に係る電子部品パッケージの一実施例を示す斜視図である。
【図２】上記図１のＡ−Ａ線断面図である。
【図３】上記実施例に係る電子部品パッケージの接地用電極パターンの形成工程図である。
【図４】上記実施例に係る電子部品パッケージの電子部品の実装工程図である。
【図５】上記実施例に係る電子部品パッケージの樹脂封止工程図である。
【図６】上記実施例に係る電子部品パッケージのハーフダイシング工程図である。
【図７】上記図６のＢ−Ｂ線断面図である。
【図８】上記実施例に係る電子部品パッケージのメッキコーティング工程図である。
【図９】従来の電子部品パッケージの一例を示す斜視図である。
【図１０】従来の電子部品パッケージの他の例を示す斜視図である。
【符号の説明】
１１ 電子部品パッケージ
１２ 基板
１３ ＩＣ
１４ コイル
１６ｂ 接地用電極パターン
１８ 封止体
２０ ニッケルメッキ層
２１ ダイシングライン
２２ 集合基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component package in which electronic components such as coils and ICs are mounted on a substrate and sealed with an epoxy resin, and a method for manufacturing the same.
[0002]
[Prior art]
In general, when an electronic component such as a coil or IC is mounted on a substrate and packaged, the entire package must be shielded because the coil and IC are affected by external magnetic fields and radio waves. Conventionally, for example, the one shown in FIG. 9 is known as a shielded whole electronic component package. In this electronic component package 1, an electronic component (not shown) including a coil and an IC is mounted on a substrate 3 having a ground connection terminal 2 formed on a side surface, and the electronic component is sealed with an epoxy resin or the like. After the sealing at 4, the whole is shielded by covering the sealing body 4 with a box-shaped shield cover 5. When the shield cover 5 is put on, the ground projection 6 provided at one corner of the shield cover 5 comes into contact with the ground connection terminal 2 of the substrate 3. The ground connection terminal 2 is electrically connected to the ground line of the motherboard when the electronic component package 1 is surface-mounted on the motherboard. Therefore, the ground protrusion 6 is electrically connected to the ground line of the motherboard via the ground connection terminal 2, and as a result, the shield cover 5 is grounded and the electronic component is shielded from electric field noise. Further, since the shield cover 5 is formed by pressing a magnetic material such as a nickel alloy into a box shape, the electronic component can be shielded from external magnetic field noise.
[0003]
Further, the electronic component package 1 shown in FIG. 10 is an example in which a spring 8 is mounted on the lower surface of a box-shaped shield cover 5. A grounding electrode pattern (not shown) formed on the upper surface of the substrate 3 by inserting the spring 8 into the hole 7 provided in the sealing body 4 when the shield cover 5 is put on the sealing body 4. And the shield cover 5 is grounded. Accordingly, in this case as well, the electronic component can be shielded from magnetic field noise and electric field noise by the shield cover 5.
[0004]
[Problems to be solved by the invention]
However, in the conventional electronic component package 1 described above, in any example, the shield cover 5 must be press-molded in a separate process from the mounting process of the electronic component, etc. There were problems in terms of cost and work.
[0005]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic component package and a method for manufacturing the same that do not use the above-described conventional shield cover, simplify the shield process as much as possible, and reduce the number of steps.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems, an electronic component package of the present invention includes a rectangular substrate on which electronic components including a coil and an IC are mounted, through-hole electrodes formed at four corners of the substrate, and the above- described substrate on the substrate. A sealing body for sealing an electronic component; and formed on an upper surface of the substrate, extending from the one through-hole electrode toward a side surface of the substrate in contact with the through-hole electrode, and on the side surface of the sealing body A grounding electrode pattern having one end exposed, and a nickel plating layer formed on the surface of the sealing body and conducting to the exposed surface of the grounding electrode pattern.
[0010]
Method of manufacturing an electronic component package of the present invention, the lattice-like dicing line is set, and the aggregate substrate forming step of forming an aggregate substrate with a Suruho Le at each corner of the dicing line, between the Suruho Le adjacent electronic components comprising a ground electrode pattern forming step, a coil and an IC on the top surface of each single substrate partitioned by the dicing lines forming a grounding electrode pattern connecting each Suruho Le so as to cross the dicing lines A mounting process for mounting each of the above, a resin sealing process for filling the entire upper surface of the collective substrate including the electronic components with an epoxy resin and sealing, and one of the grounding electrode pattern and the collective substrate from above the epoxy resin. A half dicing step for dicing up to a portion along the dicing line, and a complete table of the epoxy resin And a plating coating step for forming a nickel plating layer at the end of the groove peripheral surface of the epoxy resin that has been half-diced, and the ground electrode pattern exposed on the peripheral surface of the groove, and at the same time conducting the end and the nickel plating layer; A dividing step of dividing the collective substrate in which electronic components are shielded by the formation of the nickel plating layer into full single dicing for each single substrate, and dividing the substrate into one by one, and through holes are formed in the four corners of the divided substrate Forming an electrode and forming a grounding electrode pattern extending from any one of the through-hole electrodes toward a side surface of the substrate in contact with the through-hole electrode and having one end exposed on the side surface of the sealing body. Features.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electronic component package and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment when the electronic component package 11 according to the present invention is configured as an EL driver module. In this embodiment, an electronic component package 11 is obtained by mounting an EL driver IC 13, a coil 14, and a capacitor 15 on an upper surface of a rectangular substrate 12. As shown in FIG. 2, these electronic components are connected to the electrode pattern 16a by means such as die bonding or wire bonding, or soldered by reflow. The substrate 12 is made of an insulating material such as glass epoxy resin, and through-hole electrodes 17a, 17b, 17c, and 17d that are connected to the lower surface of the substrate 12 are formed at four corners of the side surface, and one of the through-hole electrodes is included therein. 17a is configured as a ground connection terminal. The ground connection terminal 17a is electrically connected to the ground line of the mother board when the electronic component package 11 is mounted on the mother board (not shown). In addition to the electrode pattern 16a described above, a ground electrode pattern 16b that is electrically connected to the ground connection terminal 17a is formed on the upper surface of the substrate 12.
[0012]
As described above, the upper surface of the substrate 12 on which the IC 13, the coil 14, and the capacitor 15 are mounted is sealed with the sealing body 18 made of epoxy resin. The sealing body 18 has substantially the same shape as the planar shape of the substrate 12, and both form a resin sealing package. The epoxy resin used for the sealing body 18 is excellent in moisture resistance, weather resistance, insulation, heat resistance, etc., and has a component configuration different from that of the glass epoxy plate described above, and plating is practically used on the surface of the sealing body 18. It is possible to be formed with specific strength. In this embodiment, as shown in FIGS. 1 and 2, one end portion 19 of the ground electrode pattern 16 b is exposed to the outside from the sealing body 18.
[0013]
A nickel plating layer 20 is formed on the entire surface of the sealing body 18. The nickel plating layer 20 is formed on the epoxy resin by electroless plating. Further, since the nickel plating layer 20 is also formed on the peripheral surface of the sealing body 18, the nickel plating layer 20 is also attached to the one end portion 19 of the ground electrode pattern 16 b exposed from the sealing body 18. . As a result, the nickel plating layer 20 is electrically connected to the grounding electrode pattern 16b and the ground connection terminal 17a and is grounded to the ground line of the motherboard, so that the electronic component can be shielded from external electric field noise. . Furthermore, the thickness of the nickel plating layer 20 can be freely set. For example, when the nickel plating layer 20 is formed with the same thickness as a conventional shield cover, a shielding effect can be obtained. Absorbed by the plating layer 20, the coil 14 can be shielded from magnetic field noise.
[0014]
Thus, since the electronic component can be shielded from electric field noise and magnetic field noise by simply coating the surface of the sealing body 18 made of epoxy resin with the nickel plating layer 20, the shield cover is press-molded as in the past. Therefore, the electronic component package can be easily shielded without increasing the number of work steps. In addition, since the plating thickness of the nickel plating layer 20 can be easily changed, the plating thickness can be changed according to the required shield characteristics.
[0015]
3 to 8 show a method for manufacturing an electronic component package having the above-described configuration. In this manufacturing process, first, as shown in FIG. 3, a through-hole electrode serving as a ground connection terminal 17 a is provided on a collective substrate 22 where a dicing line 21 is assumed for each single substrate 12, and an upper surface of the collective substrate 22 is provided. In this case, a ground electrode pattern 16b connecting the ground connection terminals 17a is continuously formed. At this time, a through-hole electrode other than the ground connection terminal 17a and an electrode pattern (not shown) for electronic components are also formed at the same time.
[0016]
In the next step, as shown in FIG. 4, the IC 13, the coil 14, and the capacitor 15 are placed at predetermined positions for each substrate 12 and mounted on the substrate 12 by means such as die bonding, wire bonding, and reflow. Next, as shown in FIG. 5, the entire upper surface of the collective substrate 22 is filled with epoxy resin, a sealing body 18 having a uniform thickness is formed on the substrate 12, and the electronic component is resin-sealed. In addition, resin sealing is performed using a method such as providing a mold on the outer periphery of the collective substrate 22 or applying a thin tape as a mask material so that the resin does not flow into the through hole. It may be implemented according to the actual situation.
[0017]
In the next step, as shown in FIG. 6 and FIG. 7, a cut 23 is formed in a lattice pattern from above the sealing body 18 along the dicing line 21, and the half of the collective substrate 22 is left in a substantially left half state. Dicing is performed. The half-dicing exposes the groove peripheral surface of each sealing substrate 18 for each single substrate 12 and also makes a cut 23 in substantially the upper half of the collective substrate 22, so that one end 19 of the ground electrode pattern 16 b is formed. Is also exposed from the sealing body 18. Then, in the next step shown in FIG. 8, a nickel plating layer 20 is formed on the outer surface of the sealing body 18 by an electroless plating method. At this time, the plating also penetrates into the notch 23 of the half-diced sealing body 18, and the nickel plating layer 20 is formed around the sealing body 18 for each single substrate 12. Is also attached to the exposed one end portion 19 of the ground electrode pattern 16b, and the ground connection terminal 17a consisting of a through hole is conducted and grounded. Therefore, the nickel plating layer 20 exhibits a shielding action, and the electronic component can be shielded from electric field noise and magnetic field noise.
[0018]
In this way, the entire surface of the collective substrate 22 is filled with epoxy resin, and half dicing is performed to expose the groove peripheral surface of each single substrate 12 of the sealing body 18, and a large number of nickel plating layers 20 are formed simultaneously at the same time. can do. Finally, dicing is performed again along the dicing line 21 assumed for the collective substrate 22, and each single substrate 12 is completely separated and divided into individual electronic component packages 11. The divided electronic component package 11 is mounted on a mother board (not shown) as a finished product.
[0019]
As described above, the end of the ground electrode pattern 16b can be exposed by using the half dicing process, and the ground electrode pattern 16b can be made conductive by plating the exposed portion. Further, since the electronic component package 11 is shielded by covering the outer surface of the sealing body 18 and the one end portion 19 of the ground electrode pattern 16b with a nickel plating layer 20, it is easily shielded on a consistent production line. The electronic component package 11 can be manufactured.
[0020]
In the above embodiment, the EL driver in which the IC 13, the coil 14, and the capacitor 15 are mounted on the substrate 12 has been described. However, the present invention is not limited to this and can be applied to various electronic component packages. Of course, the shape of the ground electrode pattern 16b formed on the upper surface of the substrate 12 and the exposed portion of the one end portion 19 are not limited to the above embodiment.
[0021]
【The invention's effect】
As described above, according to the electronic component package according to the present invention, an epoxy resin is used as a sealing body for the electronic component, and a nickel plating layer having a shielding effect on the surface is easily formed by electroless plating. Therefore, the manufacturing cost can be greatly reduced as compared with the conventional metal cover molding by press working which requires man-hours.
[0022]
In addition, a grounding electrode pattern that is electrically connected to the ground line is formed on the upper surface of the substrate, and a nickel plating layer is formed on one end of the grounding electrode pattern so as to be electrically connected. Could be done.
[0023]
In addition, according to the method for manufacturing an electronic component package according to the present invention, since a nickel plating layer can be formed on the surface of a sealing body made of an epoxy resin, it can be shielded. No processing is required, and electronic component packages can be manufactured on a consistent production line.
[0024]
Furthermore, according to the method for manufacturing an electronic component package according to the present invention, since the nickel plating layer can be shielded by forming the surface of the sealing body made of epoxy resin, the manufacturing using the collective substrate becomes possible. By manufacturing a large number of electronic component packages, a significant reduction in cost could be achieved.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an embodiment of an electronic component package according to the present invention.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
FIG. 3 is a process diagram of forming a grounding electrode pattern of the electronic component package according to the embodiment.
FIG. 4 is a mounting process diagram of an electronic component of the electronic component package according to the embodiment.
FIG. 5 is a resin sealing process diagram of the electronic component package according to the embodiment.
FIG. 6 is a half dicing process diagram of the electronic component package according to the embodiment.
7 is a cross-sectional view taken along line BB in FIG.
FIG. 8 is a plating coating process diagram of the electronic component package according to the embodiment.
FIG. 9 is a perspective view showing an example of a conventional electronic component package.
FIG. 10 is a perspective view showing another example of a conventional electronic component package.
[Explanation of symbols]
11 Electronic Component Package 12 Substrate 13 IC
14 Coil 16b Electrode pattern 18 for grounding Encapsulant 20 Nickel plating layer 21 Dicing line 22 Collected substrate

Claims (2)

コイル及びＩＣを含む電子部品が実装された四角形状の基板と、
該基板の四隅に形成されるスルーホール電極と、
前記基板上に前記電子部品を封止する封止体と、
前記基板の上面に形成され、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンと、
前記封止体の表面に形成され、前記接地用電極パターンの露出面に導通するニッケルメッキ層とを備えたことを特徴とする電子部品パッケージ。A rectangular substrate on which electronic components including a coil and an IC are mounted;
Through-hole electrodes formed at the four corners of the substrate;
A sealing body for sealing the electronic component on the substrate;
An electrode pattern for grounding formed on the upper surface of the substrate, extending from one of the through-hole electrodes toward the side surface of the substrate in contact with the through-hole electrode, and having one end exposed on the side surface of the sealing body;
An electronic component package comprising: a nickel plating layer formed on a surface of the sealing body and electrically connected to an exposed surface of the ground electrode pattern. 格子状のダイシングラインが設定され、このダイシングラインの各角部にスルーホールを有する集合基板を形成する集合基板形成工程と、
隣接する前記スルーホールの間のダイシングラインを横断するようにして各スルーホールを繋ぐ接地用電極パターンを形成する接地用電極パターン形成工程と、
前記ダイシングラインによって仕切られる各単一基板毎の上面にコイル及びＩＣを含む電子部品をそれぞれ実装する実装工程と、
前記電子部品を含む集合基板の上面全面にエポキシ樹脂を充填して封止する樹脂封止工程と、
前記エポキシ樹脂の上から前記接地用電極パターン及び集合基板の一部までを前記ダイシングラインに沿ってダイシングするハーフダイシング工程と、
前記エポキシ樹脂の全表面及びハーフダイシングしたエポキシ樹脂の溝周面、さらに溝周面に露出した接地用電極パターンの端部にニッケルメッキ層を形成すると同時に、該端部とニッケルメッキ層とを導通させるメッキコーティング工程と、
前記ニッケルメッキ層の形成によって電子部品がシールドされた前記集合基板を各単一基板毎にフルダイシングして一つ一つに分割する分割工程とを備え、
分割された前記基板の四隅にスルーホール電極を形成し、前記いずれか一のスルーホール電極からこのスルーホール電極に接する基板の側面に向かうように延び、前記封止体の側面に一端部が露出する接地用電極パターンを形成することを特徴とする電子部品パッケージの製造方法。Is set lattice dicing lines, and the collective substrate forming step of forming an aggregate substrate with a Suruho Le at each corner of the dicing line,
A grounding electrode pattern forming step of forming a grounding electrode pattern so as to cross the dicing line between adjacent said Suruho Le connecting each Suruho Le,
A mounting step of mounting electronic components including coils and ICs on the upper surface of each single substrate partitioned by the dicing line;
A resin sealing step of filling and sealing the entire upper surface of the collective substrate including the electronic components with an epoxy resin;
A half dicing step of dicing along the dicing line from the top of the epoxy resin to the ground electrode pattern and a part of the collective substrate;
A nickel plating layer is formed on the entire surface of the epoxy resin, the groove peripheral surface of the epoxy resin half-diced, and the end of the ground electrode pattern exposed on the groove peripheral surface, and at the same time, the end and the nickel plating layer are electrically connected. A plating coating process,
A division step of dividing the collective substrate in which electronic components are shielded by the formation of the nickel plating layer into full single dicing for each single substrate ,
Through-hole electrodes are formed at the four corners of the divided substrate, extend from any one of the through-hole electrodes toward the side surface of the substrate in contact with the through-hole electrode, and one end portion is exposed on the side surface of the sealing body A method of manufacturing an electronic component package, comprising forming a grounding electrode pattern .
JP32301697A 1997-11-25 1997-11-25 Electronic component package and manufacturing method thereof Expired - Fee Related JP4159636B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32301697A JP4159636B2 (en) 1997-11-25 1997-11-25 Electronic component package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32301697A JP4159636B2 (en) 1997-11-25 1997-11-25 Electronic component package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH11163583A JPH11163583A (en) 1999-06-18
JP4159636B2 true JP4159636B2 (en) 2008-10-01

Family

ID=18150195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32301697A Expired - Fee Related JP4159636B2 (en) 1997-11-25 1997-11-25 Electronic component package and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4159636B2 (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339016A (en) * 2000-05-30 2001-12-07 Alps Electric Co Ltd Surface mounting electronic circuit unit
JP4554831B2 (en) * 2001-02-13 2010-09-29 ローム株式会社 Method for manufacturing individual substrate, individual substrate and collective substrate
DE10125745A1 (en) * 2001-05-21 2002-12-05 Siemens Ag Method for shielding an electrical circuit implemented on a printed circuit board and a corresponding combination of a printed circuit board with a shield
EP1416532A4 (en) * 2002-07-19 2005-08-17 Matsushita Electric Ind Co Ltd Module component
JP4178880B2 (en) * 2002-08-29 2008-11-12 松下電器産業株式会社 Module parts
JP4357817B2 (en) 2002-09-12 2009-11-04 パナソニック株式会社 Module with built-in circuit components
JP3966172B2 (en) * 2002-12-09 2007-08-29 松下電器産業株式会社 Manufacturing method of module parts
US6998532B2 (en) 2002-12-24 2006-02-14 Matsushita Electric Industrial Co., Ltd. Electronic component-built-in module
US7187060B2 (en) 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
JP4489575B2 (en) * 2004-12-17 2010-06-23 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
JP2006203086A (en) 2005-01-24 2006-08-03 Citizen Electronics Co Ltd Electronic part package and manufacturing method thereof
JP4614278B2 (en) * 2005-05-25 2011-01-19 アルプス電気株式会社 Electronic circuit unit and manufacturing method thereof
US8053872B1 (en) 2007-06-25 2011-11-08 Rf Micro Devices, Inc. Integrated shield for a no-lead semiconductor device package
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US20090000815A1 (en) 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Conformal shielding employing segment buildup
US8062930B1 (en) 2005-08-08 2011-11-22 Rf Micro Devices, Inc. Sub-module conformal electromagnetic interference shield
WO2007060784A1 (en) * 2005-11-28 2007-05-31 Murata Manufacturing Co., Ltd. Circuit module and method for fabricating the same
KR100844791B1 (en) 2006-11-29 2008-07-07 엘지이노텍 주식회사 Electromagnetic wave shielding apparatus, high-frequency module with thereof and manufacturing method thereof
WO2008062982A1 (en) * 2006-11-21 2008-05-29 Lg Innotek Co., Ltd Electromagnetic shielding device, radio frequency module having the same, and method of manufacturing the radio frequency module
KR100844790B1 (en) * 2006-11-29 2008-07-07 엘지이노텍 주식회사 Electromagnetic wave shielding apparatus, high-frequency module with thereof and manufacturing method thereof
JP2009016371A (en) * 2007-06-29 2009-01-22 Casio Comput Co Ltd Method of manufacturing module with shield function
CN101978492B (en) 2008-03-24 2012-10-03 株式会社村田制作所 Method for manufacturing electronic component module
JP5273154B2 (en) * 2008-10-23 2013-08-28 株式会社村田製作所 Manufacturing method of electronic component module
CN102550140B (en) * 2009-10-01 2015-05-27 松下电器产业株式会社 Module and process for production thereof
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
WO2012165111A1 (en) * 2011-05-31 2012-12-06 株式会社村田製作所 Method for producing multi-layer substrate and multi-layer substrate
JP6136152B2 (en) * 2012-09-11 2017-05-31 日本電気株式会社 Manufacturing method of module parts
US9807890B2 (en) 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
JP6091460B2 (en) 2014-04-11 2017-03-08 シマネ益田電子株式会社 Manufacturing method of electronic parts
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules

Also Published As

Publication number Publication date
JPH11163583A (en) 1999-06-18

Similar Documents

Publication Publication Date Title
JP4159636B2 (en) Electronic component package and manufacturing method thereof
JP4662324B2 (en) Circuit module
US4974057A (en) Semiconductor device package with circuit board and resin
US7261596B2 (en) Shielded semiconductor device
AU690920B2 (en) Multi-chip module
US20010054756A1 (en) Multi-layered semiconductor device and method for producing the same
JPH07326688A (en) Semiconductor device
KR20060129519A (en) Overmolded semiconductor package with an integrated emi and rfi shield
JPH10214923A (en) Chip-on-board shielding structure and its manufacture
JP4010624B2 (en) Method for manufacturing transformer or circuit module having transformer
JPH09102561A (en) Semiconductor package
JP2705408B2 (en) Hybrid integrated circuit device
JPH10233593A (en) Smd driver module for el with electromagnetic shield and its manufacture
JP2000133658A (en) Manufacture of electronic component
JPS62235799A (en) Hybrid integrated circuit device
JPH0878954A (en) Oscillator and manufacture thereof
JPH0517709B2 (en)
JPH11150035A (en) Surface-mount type coil package and manufacture thereof
JPH07122701A (en) Semiconductor device, its manufacture, and lead frame for pga
JPH06216492A (en) Electronic device
JP2827950B2 (en) Hybrid integrated circuit device
JPH0249758Y2 (en)
JP3264760B2 (en) Connection board and package for mounting semiconductor, and method of manufacturing semiconductor device
JPH0278298A (en) Electronic device
JPH11102991A (en) Semiconductor element mounting frame

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040916

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070228

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070426

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070928

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071126

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080509

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080530

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080702

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080716

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees