JPH01239916A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01239916A JPH01239916A JP6753688A JP6753688A JPH01239916A JP H01239916 A JPH01239916 A JP H01239916A JP 6753688 A JP6753688 A JP 6753688A JP 6753688 A JP6753688 A JP 6753688A JP H01239916 A JPH01239916 A JP H01239916A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- substrate
- single crystal
- sio2 film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に基板の構造に関する′〔従来
の技術〕
従来の半導体装置の基板は、大口径化の容易さ、低価格
等の理由によりＳｌが主流であった。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, particularly the structure of substrates. For some reason, Sl was the mainstream.
しかし前述の従来技術ではＳｌの移動度は室温で１５０
０ｉ／Ｖ−Ｓ程度であり、信号処理速度に限界があると
いう課題があった。However, in the prior art described above, the mobility of Sl is 150 at room temperature.
There was a problem that the signal processing speed was about 0i/VS, and there was a limit to the signal processing speed.
この課題を解決するために常温で８１の５倍以上の移動
度を持つＧａＡｓを用いる手段があるがＧａＡｓは高価
であり、また大口径化が非常に困難であるために大量生
産には向かない。To solve this problem, there is a way to use GaAs, which has a mobility more than 5 times that of 81 at room temperature, but GaAs is expensive and it is very difficult to increase the diameter, so it is not suitable for mass production. .
そこで本発明は、このような課題を解決するもので、そ
の目的とするところは、ＳｉとＧａＡｅのそれぞれの長
所だけを生かし、安価かつ大口径化可能で高速処理もで
きる半導体装置を提供することにある。The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that is inexpensive, can have a large diameter, and can perform high-speed processing by taking advantage of the respective advantages of Si and GaAe. It is in.
本発明の半導体装置は、８１基板の一部にＧａＡｓが埋
め込まれていることを特徴とする。またこの時ＳｉとＧ
ａＡｓはＳｉ０．により絶縁されていることが好ましい
。The semiconductor device of the present invention is characterized in that GaAs is embedded in a part of the 81 substrate. At this time, Si and G
aAs is Si0. It is preferable to be insulated by.
以下図面により本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の実施例を表わす断面図であり、１０１
はＰ型Ｓｉ基板、１０２は５１０２膜、１０５は単結晶
ＧａＡｓである。FIG. 1 is a sectional view showing an embodiment of the present invention, 101
102 is a P-type Si substrate, 102 is a 5102 film, and 105 is single crystal GaAs.
また本発明の半導体装置の製造方法を第２図に示す。Further, a method for manufacturing a semiconductor device according to the present invention is shown in FIG.
工程（１）・・・・・・第２図（α）
Ｐ型Ｓｉ基板２０１上の一部にレジストパターン２ｏ４
を設ｋｊＲ工Ｅ法により前記８１基板２０１を２μ程度
エツチングし溝部２０５を形成する工程（２）・・・・
・・第２図（ｂ）
全面を熱酸化し５ｏｏｏＸ程度の３１０２膜２０２を形
成する。Step (1)...Figure 2 (α) Resist pattern 2o4 is formed on a part of the P-type Si substrate 201
Step (2) of etching the 81 substrate 201 by about 2 μm using the kjR E method to form the groove portion 205.
...FIG. 2(b) The entire surface is thermally oxidized to form a 3102 film 202 of approximately 5oooX.
工程（３）・・・・・・第２図（ｃ）
４５０℃〜５００℃という低温で２００ ＸＨ度の多結
晶ＧａＡｓ２０６を付着させる。Step (3)...Figure 2(c) Polycrystalline GaAs 206 of 200 XH degree is deposited at a low temperature of 450 to 500 degrees Celsius.
工程（４）・・・・・・第２図（ｄ）
前記多結晶ＧａＡθ２０６をＡ日ガスの雰囲気中で、通
常のＧａＡｓの成長温度６５０〜７００℃で数分間熱処
理を行うことで、付着した（）ａＡ８２０６は単結晶と
なりその上にＧ ａ Ａ ｓ’の成長を続行し単結晶Ｇ
ａＡｓ２０５を３μ程度得る。Step (4)...Figure 2(d) The polycrystalline GaAθ206 is heat-treated for several minutes at the normal GaAs growth temperature of 650 to 700°C in an atmosphere of A day gas to form the adhered polycrystalline GaAθ206. () aA8206 becomes a single crystal and continues to grow G a A s' on it to form a single crystal G
Obtain about 3μ of aAs205.
工程（５）・・・・・・第２図（６）
ＲＩＥ法で全面をエツチングすることで前記溝部２０５
の内部のみに前記単結晶ＧａＡｓ２０５が残る。Step (5)...Figure 2 (6) The groove portion 205 is etched by etching the entire surface by RIE method.
The single crystal GaAs 205 remains only inside.
この後に溝外部の８１０．膜をＨＩＦ水溶液でエツチン
グ除去することにより第１図の構造が得られる。After this, 810 outside the groove. The structure shown in FIG. 1 is obtained by etching away the film with an aqueous HIF solution.
尚、この基板上の素子の形成は、従来技術により容易に
達成し帰るのでここでは省略する。It should be noted that the formation of elements on this substrate can be easily accomplished using conventional techniques, and will therefore be omitted here.
以上のように発明によれば、ＧａＡ９．Ｓｉハイブリッ
ドエＯを作製することが可能であり、基板に８１を用い
ることで、大口径・安価等のメリットを持ち、またＧａ
Ａｓ層を有することで信号の高速処理が容易になるとい
う多大の効果を有する。As described above, according to the invention, GaA9. It is possible to fabricate Si hybrid E-O, and by using 81 as the substrate, it has advantages such as large diameter and low cost.
Having the As layer has the great effect of facilitating high-speed processing of signals.
第１図は本発明の半導体装置の構造を表わす断面図、第
２図（α）〜（−）は本発明の半導体装置の主要工程を
表わす断面図。
ｉｏｌ、２０１・・・・・・Ｐ型Ｓｉ基板１０２．２０
２・・・・・・Ｓｉ０．膜１０５ 、２０５−−−−・
・単結晶ＧａＡｓ２０４ ・・・・・・レジスト
、パターン２０５ ・・・・・・溝 部
２０６ ・・・・・・多結晶ＧａＡｓ以上
出願人 セイコーエプソン株式会社
代理人 弁理士最上務、（他１名）
Ｙ 工 目FIG. 1 is a cross-sectional view showing the structure of a semiconductor device of the present invention, and FIGS. 2 (α) to (-) are cross-sectional views showing main steps of the semiconductor device of the present invention. iol, 201...P-type Si substrate 102.20
2...Si0. Membrane 105, 205----
・Single crystal GaAs204...Resist, pattern 205...Groove portion 206...Polycrystalline GaAs and above Applicant: Seiko Epson Corporation Representative, Patent Attorney, Senior Vice President, (1 other person) )Y
Claims (2)
とを特徴とする半導体装置。(1) A semiconductor device characterized in that GaAs is embedded in a portion of a Si substrate.
されていることを特徴とする請求項１記載の半導体装置
。(2) The semiconductor device according to claim 1, wherein the Si and the GaAs are insulated by SiO_2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6753688A JPH01239916A (en) | 1988-03-22 | 1988-03-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6753688A JPH01239916A (en) | 1988-03-22 | 1988-03-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01239916A true JPH01239916A (en) | 1989-09-25 |
Family
ID=13347797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6753688A Pending JPH01239916A (en) | 1988-03-22 | 1988-03-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01239916A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0481741A2 (en) * | 1990-10-18 | 1992-04-22 | Hitachi, Ltd. | High frequency power amplifier circuit and mobile radio communication apparatus using the same |
-
1988
- 1988-03-22 JP JP6753688A patent/JPH01239916A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0481741A2 (en) * | 1990-10-18 | 1992-04-22 | Hitachi, Ltd. | High frequency power amplifier circuit and mobile radio communication apparatus using the same |
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