JPH01233530A - Fault diagnostic system - Google Patents

Abstract

PURPOSE:To prevent processing from being suspended and to smoothly execute data transfer processing by detecting the fault of a data register and transferring the data by using only a normal data register. CONSTITUTION:When discordance is detected in a data discordance detecting circuit 11, its fact is informed to a fault diagnostic control circuit 18, and an instruction is issued so that the check of data registers 7, 8 is performed. A data discordance detecting circuit 16 compares the test data of the data registers 7, 8 with the test data generated by a test data generating circuit 15, and informs the result of comparison to the control circuit 18. The control circuit 18 detects a normal data register 7 or 8, and transfers the data by using only the normal data register 7 or 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data register for storing data in a data processing device. This relates to a method of diagnosing a fault when it occurs.

(Prior Art) Conventionally, a fault diagnosis method for this type of data register failure has been to check the normality of data using a parity bit transferred from another data processing device, and when an abnormality is detected, to notify the host device of the problem. It only reported a hardware error.

(Problem to be Solved by the Invention) In the conventional failure diagnosis method described above, when abnormal data is confirmed, data transfer from the data processing device is interrupted at that point, and a data transfer request is executed again to retrieve the data. If the data is transferred again, sufficient failure diagnosis has not been performed, so there is a problem in that abnormal data may be repeatedly input.

(Means for Solving the Problems) In order to solve the above problems, the fault diagnosis method provided by the present invention has an interface using handshake,
A method for diagnosing a failure in a data register storing data transferred from a data processing device having the same interface in a data processing device having multiplexed data registers connected to a data processing device having the same interface. means for checking whether a plurality of multiplexed data registers storing data transferred from the data processing device having the same interface and data loaded from the plurality of data registers all match. and means for suppressing a next data transfer request to the data processing device having the same interface when at least one mismatch is detected by the checking means, and the suppressing means suppresses a next data transfer request. and means for writing the same test data into each of the plurality of data registers, and the test data written to the plurality of data registers by the writing means and the test data loaded from these data registers. Means for detecting a data register in which a mismatch has occurred by comparing each data register, and prohibiting the storage of subsequent data in the data register in which a mismatch detected by the detecting means has occurred, and a normal data register. The data processing apparatus is characterized in that it has a means for transferring the data loaded from only to a lower level, and for permitting a request to transfer the next data to the data processing apparatus having the same interface.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data processing device to which an embodiment of the present invention is applied.

In order to realize the above-mentioned means, this data processing device 1:
A data transfer control circuit 2 that controls data transfer between other data processing devices 3 using a data request line and a data strobe line, a test data generation circuit 15 that generates test data, and a data transfer control circuit 2 a data selection circuit 6 that selects whether to send input data to a lower level or to send out test data input from the test data generation circuit 15; and two circuits that store data selected by the data selection circuit 6. Data registers 7 and 8, auxiliary registers 9 and 10 for temporarily saving output values output from data registers 7 and 8, and data values stored in data registers 7 and 8. A data number generation circuit 11 checks whether or not the numbers match, and when a mismatch is detected by this data number generation circuit 11, the other data processing device 3
The test data generation circuit 15 is instructed to generate test data, and the test data generated by the test data generation circuit 15 and selected and outputted by the data selection circuit 6 is transferred to the data register 7. and a fault diagnosis control circuit 18 that instructs writing to 8.
A data selection circuit 12 selects test data from one of the data registers 7 and 8 to which test data has been written in accordance with instructions from the fault diagnosis control circuit 18; A data register output circuit 16 that compares the test data generated by the test data generation circuit 15 and data registers other than data registers that are determined to be abnormal due to a mismatch detected by the data output circuit 16. data selection circuit 1 that selects the output from the auxiliary register 9 or 10
7, and a data selection circuit 13 that selects data from data register 7 or 8 during normal operation and selects data from auxiliary register 9 or 10 during abnormal operation and outputs the selected data to data processing circuit 14.
It has

When the data transfer control circuit 2 sends a data request signal 4 to the data processing device 3, the data processing device 3 starts transferring data to the data processing device 1.

The data transferred from the data processing device 3 is received by the data transfer control circuit 2 together with the data strobe signal 5,
It is output to the data selection circuit 6.

The data selection circuit 6 selects data from the data transfer control circuit 2 under the control of the failure diagnosis control circuit 18 and outputs it to the data registers 7 and 8.

As a result, the transfer data from the data processing device 3 is simultaneously written into the data registers 7 and 8, and the contents are stored from the data register 7 and into the auxiliary registers 9 and 10, respectively. At this time, at the same time, the data number output circuit 1
1 checks whether the contents of data registers 7 and 8 match, and if they match, it is determined that both data registers 7 and 8 are normal, and the fault diagnosis control circuit 18 is controlled. Accordingly, the data selection circuit 12 selects the contents of the data register 7 or 8. This content is selected by the data selection circuit 13 and the data processing device 14
is output to and processed.

Further, if a discrepancy is detected in the data number output circuit 11, this fact is notified to the fault diagnosis control circuit 18, and the fault diagnosis control circuit 18, which has received this notification, checks the data registers 7 and 8. In order to implement this, the data transfer control circuit 2 is instructed to suppress the data request signal 4 for the next data, and the test data generation circuit 15 is instructed to generate test data. The test data generated by the test data generation circuit 15 is output to the data number output circuit 16, and is also selected by the data selection circuit 6 under the control of the fault diagnosis control circuit 18 and output to the data registers 7 and 8. Stored.

The data number output circuit 16 compares the test data stored in the data register and selected by the data selection circuit 12 with the test data generated by the test data generation circuit 15, and sends the comparison result to the fault diagnosis control circuit 18. Notify. Similarly, the test data for the data register 8 is compared, and the comparison result is notified to the fault diagnosis control circuit 18.

The failure diagnosis control circuit 18 determines that the data register 7 or 8 that has become inconsistent based on the notification contents from the data number output circuit 16 is abnormal, discards the data in this data register 7 or 8, and restores the normal state. The data selection circuit 17 is instructed to select the auxiliary register 9 or 10 that stores the contents of the data register 7 or 8 determined to be the data register.

The data selected and output from the data selection circuit 17 is selected by the data selection circuit 13 and output to the data processing device 14 for processing.

In this way, in this data processing device 1, even if the data register 7 or 8 fails, the failed data register 7 or 8 is detected and the data is transferred using only the normal data register 7 or 8. can do.

(Effects of the Invention) As explained above, in a data processing device having a plurality of multiplexed data registers, when a failure occurs in any of the data registers, the present invention detects the failed data register. By transferring data using only normal data registers, there is no need to interrupt the processing as in the conventional method, and the data transfer processing can be carried out smoothly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device to which an embodiment of the present invention is applied. 1.3... Data processing device, 2... Data transfer control circuit, 4... Data request signal, 5... Data strobe signal, 6.12.13.17... Data selection circuit, 7゜8...Data register, 9.10...Auxiliary register, 11, 16...Data number configuration circuit, 14
. . . data processing circuit, 15 . . . test data generation circuit, 18 . . . failure diagnosis control circuit.

Claims (1)

[Claims] In a data processing device having a handshake interface and having multiplexed data registers connected to data processing devices having the same interface, data transferred from the data processing device having the same interface A method for diagnosing a failure of a data register storing data, the method comprising: a plurality of multiplexed data registers storing data transferred from the data processing device having the same interface; means for checking whether or not all data match; and means for suppressing a request to transfer the next data to the data processing device having the same interface when at least one discrepancy is detected by the checking means. and means for writing the same test data into each of the plurality of data registers after the next data transfer request is suppressed by the suppression means; and test data written to the plurality of data registers by the writing means. and test data loaded from these data registers for each data register to detect a data register in which a mismatch has occurred; It is characterized by having means for prohibiting subsequent data storage, transferring data loaded only from normal data registers to a lower level, and permitting a request to transfer the next data to the data processing device having the same interface. A fault diagnosis method that uses